1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /*
3 * Copyright (c) 2019 Fuzhou Rockchip Electron
4 * Copyright (c) 2019 Vamrs Limited
5 * Copyright (c) 2019 Amarula Solutions(India)
6 */
7
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/pinctrl/rockchip.h>
10 #include <dt-bindings/pwm/pwm.h>
11
12 / {
13 compatible = "vamrs,rk3399pro-vmarc-so
14
15 aliases {
16 ethernet0 = &gmac;
17 mmc0 = &sdhci;
18 mmc1 = &sdmmc;
19 };
20
21 vcc3v3_pcie: vcc-pcie-regulator {
22 compatible = "regulator-fixed"
23 enable-active-high;
24 gpio = <&gpio4 RK_PD4 GPIO_ACT
25 pinctrl-names = "default";
26 pinctrl-0 = <&pcie_pwr>;
27 regulator-name = "vcc3v3_pcie"
28 regulator-always-on;
29 regulator-boot-on;
30 vin-supply = <&vcc5v0_sys>;
31 };
32 };
33
34 &cpu_l0 {
35 cpu-supply = <&vdd_cpu_l>;
36 };
37
38 &cpu_l1 {
39 cpu-supply = <&vdd_cpu_l>;
40 };
41
42 &cpu_l2 {
43 cpu-supply = <&vdd_cpu_l>;
44 };
45
46 &cpu_l3 {
47 cpu-supply = <&vdd_cpu_l>;
48 };
49
50 &emmc_phy {
51 status = "okay";
52 };
53
54 &gmac {
55 assigned-clocks = <&cru SCLK_RMII_SRC>
56 phy-supply = <&vcc_lan>;
57 snps,reset-gpio = <&gpio3 RK_PB7 GPIO_
58 };
59
60 &hdmi {
61 ddc-i2c-bus = <&i2c3>;
62 pinctrl-names = "default";
63 pinctrl-0 = <&hdmi_cec>;
64 };
65
66 &i2c0 {
67 clock-frequency = <400000>;
68 i2c-scl-falling-time-ns = <30>;
69 i2c-scl-rising-time-ns = <180>;
70 status = "okay";
71
72 rk809: pmic@20 {
73 compatible = "rockchip,rk809";
74 reg = <0x20>;
75 interrupt-parent = <&gpio1>;
76 interrupts = <RK_PC2 IRQ_TYPE_
77 #clock-cells = <1>;
78 clock-output-names = "rk808-cl
79 pinctrl-names = "default";
80 pinctrl-0 = <&pmic_int_l>;
81 rockchip,system-power-controll
82 wakeup-source;
83
84 vcc1-supply = <&vcc5v0_sys>;
85 vcc2-supply = <&vcc5v0_sys>;
86 vcc3-supply = <&vcc5v0_sys>;
87 vcc4-supply = <&vcc5v0_sys>;
88 vcc5-supply = <&vcc_buck5>;
89 vcc6-supply = <&vcc_buck5>;
90 vcc7-supply = <&vcc5v0_sys>;
91 vcc8-supply = <&vcc3v3_sys>;
92 vcc9-supply = <&vcc5v0_sys>;
93
94 regulators {
95 vdd_log: DCDC_REG1 {
96 regulator-name
97 regulator-alwa
98 regulator-boot
99 regulator-min-
100 regulator-max-
101 regulator-init
102 regulator-stat
103 regula
104 regula
105 };
106 };
107
108 vdd_cpu_l: DCDC_REG2 {
109 regulator-name
110 regulator-alwa
111 regulator-boot
112 regulator-min-
113 regulator-max-
114 regulator-ramp
115 regulator-init
116 regulator-stat
117 regula
118 };
119 };
120
121 vcc_ddr: DCDC_REG3 {
122 regulator-name
123 regulator-alwa
124 regulator-boot
125 regulator-init
126 regulator-stat
127 regula
128 };
129 };
130
131 vcc3v3_sys: DCDC_REG4
132 regulator-name
133 regulator-alwa
134 regulator-boot
135 regulator-min-
136 regulator-max-
137 regulator-init
138 regulator-stat
139 regula
140 regula
141 };
142 };
143
144 vcc_buck5: DCDC_REG5 {
145 regulator-name
146 regulator-alwa
147 regulator-boot
148 regulator-min-
149 regulator-max-
150 regulator-stat
151 regula
152 regula
153 };
154 };
155
156 vcca_0v9: LDO_REG1 {
157 regulator-name
158 regulator-alwa
159 regulator-boot
160 regulator-min-
161 regulator-max-
162 regulator-stat
163 regula
164 regula
165 };
166 };
167
168 vcc_1v8: LDO_REG2 {
169 regulator-name
170 regulator-alwa
171 regulator-boot
172 regulator-min-
173 regulator-max-
174 regulator-stat
175 regula
176 regula
177 };
178 };
179
180 vcc_0v9: LDO_REG3 {
181 regulator-name
182 regulator-alwa
183 regulator-boot
184 regulator-min-
185 regulator-max-
186 regulator-stat
187 regula
188 regula
189 };
190 };
191
192 vcca_1v8: LDO_REG4 {
193 regulator-name
194 regulator-alwa
195 regulator-boot
196 regulator-min-
197 regulator-max-
198 regulator-stat
199 regula
200 regula
201 };
202 };
203
204 /*
205 * As per BSP, but sch
206 * pin for LD05.
207 */
208 vdd1v5_dvp: LDO_REG5 {
209 regulator-name
210 regulator-alwa
211 regulator-boot
212 regulator-min-
213 regulator-max-
214 regulator-stat
215 regula
216 };
217 };
218
219 vcc_1v5: LDO_REG6 {
220 regulator-name
221 regulator-alwa
222 regulator-boot
223 regulator-min-
224 regulator-max-
225 regulator-stat
226 regula
227 };
228 };
229
230 vccio_3v0: LDO_REG7 {
231 regulator-name
232 regulator-alwa
233 regulator-boot
234 regulator-min-
235 regulator-max-
236 regulator-stat
237 regula
238 };
239 };
240
241 vccio_sd: LDO_REG8 {
242 regulator-name
243 regulator-alwa
244 regulator-boot
245 regulator-min-
246 regulator-max-
247 regulator-stat
248 regula
249 };
250 };
251
252 /*
253 * As per BSP, but sch
254 * pin for LD09.
255 */
256 vcc_sd: LDO_REG9 {
257 regulator-name
258 regulator-alwa
259 regulator-boot
260 regulator-min-
261 regulator-max-
262 regulator-stat
263 regula
264 };
265 };
266
267 vcc5v0_usb2: SWITCH_RE
268 regulator-name
269 regulator-min-
270 regulator-max-
271 regulator-stat
272 regula
273 regula
274 };
275 };
276
277 vccio_3v3: vcc_lan: SW
278 regulator-name
279 regulator-alwa
280 regulator-boot
281 regulator-min-
282 regulator-max-
283 regulator-stat
284 regula
285 };
286 };
287 };
288 };
289 };
290
291 &i2c1 {
292 i2c-scl-falling-time-ns = <30>;
293 i2c-scl-rising-time-ns = <140>;
294 status = "okay";
295 };
296
297 &i2c2 {
298 clock-frequency = <400000>;
299 status = "okay";
300
301 hym8563: rtc@51 {
302 compatible = "haoyu,hym8563";
303 reg = <0x51>;
304 #clock-cells = <0>;
305 clock-output-names = "hym8563"
306 pinctrl-names = "default";
307 pinctrl-0 = <&hym8563_int>;
308 interrupt-parent = <&gpio4>;
309 interrupts = <RK_PD6 IRQ_TYPE_
310 };
311 };
312
313 &i2c3 {
314 i2c-scl-rising-time-ns = <450>;
315 i2c-scl-falling-time-ns = <15>;
316 status = "okay";
317 };
318
319 &io_domains {
320 status = "okay";
321 bt656-supply = <&vcca_1v8>;
322 gpio1830-supply = <&vccio_3v0>;
323 sdmmc-supply = <&vccio_sd>;
324 };
325
326 &pcie_phy {
327 status = "okay";
328 };
329
330 &pcie0 {
331 ep-gpios = <&gpio0 RK_PB4 GPIO_ACTIVE_
332 num-lanes = <4>;
333 pinctrl-0 = <&pcie_clkreqnb_cpm>;
334 pinctrl-names = "default";
335 vpcie0v9-supply = <&vcca_0v9>; /* VCC
336 vpcie1v8-supply = <&vcca_1v8>; /* VCC
337 vpcie3v3-supply = <&vcc3v3_pcie>;
338 status = "okay";
339 };
340
341 &pinctrl {
342 hym8563 {
343 hym8563_int: hym8563-int {
344 rockchip,pins = <4 RK_
345 };
346 };
347
348 pcie {
349 pcie_pwr: pcie-pwr {
350 rockchip,pins = <4 RK_
351 };
352 };
353
354 pmic {
355 pmic_int_l: pmic-int-l {
356 rockchip,pins = <1 RK_
357 };
358 };
359
360 sdio-pwrseq {
361 wifi_enable_h: wifi-enable-h {
362 rockchip,pins = <2 RK_
363 };
364 };
365
366 vbus_host {
367 usb1_en_oc: usb1-en-oc {
368 rockchip,pins = <4 RK_
369 };
370 };
371
372 vbus_typec {
373 usb0_en_oc: usb0-en-oc {
374 rockchip,pins = <4 RK_
375 };
376 };
377 };
378
379 &pmu_io_domains {
380 status = "okay";
381 pmu1830-supply = <&vcc_1v8>;
382 };
383
384 &sdio_pwrseq {
385 /*
386 * On the module itself this is one of
387 * on the actual card populated):
388 * - SDIO_RESET_L_WL_REG_ON
389 * - PDN (power down when low)
390 */
391 reset-gpios = <&gpio2 RK_PD3 GPIO_ACTI
392 };
393
394 &sdhci {
395 bus-width = <8>;
396 mmc-hs400-1_8v;
397 mmc-hs400-enhanced-strobe;
398 non-removable;
399 status = "okay";
400 };
401
402 &sdmmc {
403 cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_
404 max-frequency = <150000000>;
405 };
406
407 &tcphy0 {
408 status = "okay";
409 };
410
411 &tsadc {
412 rockchip,hw-tshut-mode = <1>;
413 rockchip,hw-tshut-polarity = <1>;
414 status = "okay";
415 };
416
417 &u2phy0 {
418 status = "okay";
419
420 u2phy0_otg: otg-port {
421 phy-supply = <&vbus_typec>;
422 status = "okay";
423 };
424
425 u2phy0_host: host-port {
426 phy-supply = <&vbus_host>;
427 status = "okay";
428 };
429 };
430
431
432 &u2phy1 {
433 status = "okay";
434
435 u2phy1_host: host-port {
436 phy-supply = <&vbus_host>;
437 status = "okay";
438 };
439 };
440
441 &usb_host0_ehci {
442 status = "okay";
443 };
444
445 &usb_host0_ohci {
446 status = "okay";
447 };
448
449 &usb_host1_ehci {
450 status = "okay";
451 };
452
453 &usb_host1_ohci {
454 status = "okay";
455 };
456
457 &usbdrd3_0 {
458 status = "okay";
459 };
460
461 &usbdrd_dwc3_0 {
462 status = "okay";
463 };
464
465 &vbus_host {
466 enable-active-high;
467 gpio = <&gpio4 RK_PD1 GPIO_ACTIVE_HIGH
468 pinctrl-names = "default";
469 pinctrl-0 = <&usb1_en_oc>;
470 };
471
472 &vbus_typec {
473 enable-active-high;
474 gpio = <&gpio4 RK_PD2 GPIO_ACTIVE_HIGH
475 pinctrl-names = "default";
476 pinctrl-0 = <&usb0_en_oc>;
477 };
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