1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2
3 /dts-v1/;
4 #include <dt-bindings/gpio/gpio.h>
5 #include <dt-bindings/leds/common.h>
6 #include <dt-bindings/pinctrl/rockchip.h>
7 #include <dt-bindings/soc/rockchip,vop2.h>
8 #include "rk3566.dtsi"
9
10 / {
11 model = "EmbedFire LubanCat 1";
12 compatible = "embedfire,lubancat-1", "
13
14 aliases {
15 ethernet0 = &gmac1;
16 mmc0 = &sdmmc0;
17 mmc1 = &sdhci;
18 };
19
20 chosen: chosen {
21 stdout-path = "serial2:1500000
22 };
23
24 gmac1_clkin: external-gmac1-clock {
25 compatible = "fixed-clock";
26 clock-frequency = <125000000>;
27 clock-output-names = "gmac1_cl
28 #clock-cells = <0>;
29 };
30
31 hdmi-con {
32 compatible = "hdmi-connector";
33 type = "a";
34
35 port {
36 hdmi_con_in: endpoint
37 remote-endpoin
38 };
39 };
40 };
41
42 gpio-leds {
43 compatible = "gpio-leds";
44
45 sys_led: sys-led {
46 label = "sys_led";
47 linux,default-trigger
48 default-state = "on";
49 gpios = <&gpio0 RK_PC5
50 pinctrl-names = "defau
51 pinctrl-0 = <&sys_led_
52 };
53 };
54
55 usb_5v: usb-5v-regulator {
56 compatible = "regulator-fixed"
57 regulator-name = "usb_5v";
58 regulator-always-on;
59 regulator-boot-on;
60 regulator-min-microvolt = <500
61 regulator-max-microvolt = <500
62 };
63
64 vcc5v0_sys: vcc5v0-sys-regulator {
65 compatible = "regulator-fixed"
66 regulator-name = "vcc5v0_sys";
67 regulator-always-on;
68 regulator-boot-on;
69 regulator-min-microvolt = <500
70 regulator-max-microvolt = <500
71 vin-supply = <&usb_5v>;
72 };
73
74 vcc3v3_sys: vcc3v3-sys-regulator {
75 compatible = "regulator-fixed"
76 regulator-name = "vcc3v3_sys";
77 regulator-always-on;
78 regulator-boot-on;
79 regulator-min-microvolt = <330
80 regulator-max-microvolt = <330
81 vin-supply = <&vcc5v0_sys>;
82 };
83
84 vcc3v3_pcie: vcc3v3-pcie-regulator {
85 compatible = "regulator-fixed"
86 regulator-name = "vcc3v3_pcie"
87 regulator-min-microvolt = <330
88 regulator-max-microvolt = <330
89 enable-active-high;
90 gpio = <&gpio0 RK_PD3 GPIO_ACT
91 startup-delay-us = <5000>;
92 vin-supply = <&vcc5v0_sys>;
93 };
94
95 vcc5v0_usb20_host: vcc5v0-usb20-host-r
96 compatible = "regulator-fixed"
97 enable-active-high;
98 gpio = <&gpio2 RK_PB6 GPIO_ACT
99 pinctrl-names = "default";
100 pinctrl-0 = <&vcc5v0_usb20_hos
101 regulator-name = "vcc5v0_usb20
102 regulator-always-on;
103 };
104
105 vcc5v0_usb30_host: vcc5v0-usb30-host-r
106 compatible = "regulator-fixed"
107 enable-active-high;
108 gpio = <&gpio2 RK_PB5 GPIO_ACT
109 pinctrl-names = "default";
110 pinctrl-0 = <&vcc5v0_usb30_hos
111 regulator-name = "vcc5v0_usb30
112 regulator-always-on;
113 };
114 };
115
116 &uart2 {
117 status = "okay";
118 };
119
120 &combphy1 {
121 status = "okay";
122 };
123
124 &combphy2 {
125 status = "okay";
126 };
127
128 &cpu0 {
129 cpu-supply = <&vdd_cpu>;
130 };
131
132 &cpu1 {
133 cpu-supply = <&vdd_cpu>;
134 };
135
136 &cpu2 {
137 cpu-supply = <&vdd_cpu>;
138 };
139
140 &cpu3 {
141 cpu-supply = <&vdd_cpu>;
142 };
143
144 &gpu {
145 mali-supply = <&vdd_gpu>;
146 status = "okay";
147 };
148
149 &hdmi {
150 avdd-0v9-supply = <&vdda0v9_image>;
151 avdd-1v8-supply = <&vcca1v8_image>;
152 status = "okay";
153 };
154
155 &hdmi_in {
156 hdmi_in_vp0: endpoint {
157 remote-endpoint = <&vp0_out_hd
158 };
159 };
160
161 &hdmi_out {
162 hdmi_out_con: endpoint {
163 remote-endpoint = <&hdmi_con_i
164 };
165 };
166
167 &hdmi_sound {
168 status = "okay";
169 };
170
171 &i2c0 {
172 status = "okay";
173
174 vdd_cpu: regulator@1c {
175 compatible = "tcs,tcs4525";
176 reg = <0x1c>;
177 fcs,suspend-voltage-selector =
178 regulator-name = "vdd_cpu";
179 regulator-always-on;
180 regulator-boot-on;
181 regulator-min-microvolt = <800
182 regulator-max-microvolt = <115
183 regulator-ramp-delay = <2300>;
184 vin-supply = <&vcc5v0_sys>;
185
186 regulator-state-mem {
187 regulator-off-in-suspe
188 };
189 };
190
191 rk809: pmic@20 {
192 compatible = "rockchip,rk809";
193 reg = <0x20>;
194 interrupt-parent = <&gpio0>;
195 interrupts = <RK_PA3 IRQ_TYPE_
196 clock-output-names = "rk808-cl
197
198 pinctrl-names = "default";
199 pinctrl-0 = <&pmic_int>;
200 rockchip,system-power-controll
201 wakeup-source;
202 #clock-cells = <1>;
203
204 vcc1-supply = <&vcc3v3_sys>;
205 vcc2-supply = <&vcc3v3_sys>;
206 vcc3-supply = <&vcc3v3_sys>;
207 vcc4-supply = <&vcc3v3_sys>;
208 vcc5-supply = <&vcc3v3_sys>;
209 vcc6-supply = <&vcc3v3_sys>;
210 vcc7-supply = <&vcc3v3_sys>;
211 vcc8-supply = <&vcc3v3_sys>;
212 vcc9-supply = <&vcc3v3_sys>;
213
214 regulators {
215 vdd_logic: DCDC_REG1 {
216 regulator-name
217 regulator-alwa
218 regulator-boot
219 regulator-min-
220 regulator-max-
221 regulator-ramp
222 regulator-init
223
224 regulator-stat
225 regula
226 };
227 };
228
229 vdd_gpu: DCDC_REG2 {
230 regulator-name
231 regulator-alwa
232 regulator-boot
233 regulator-min-
234 regulator-max-
235 regulator-ramp
236 regulator-init
237
238 regulator-stat
239 regula
240 };
241 };
242
243 vcc_ddr: DCDC_REG3 {
244 regulator-name
245 regulator-alwa
246 regulator-boot
247 regulator-init
248
249 regulator-stat
250 regula
251 };
252 };
253
254 vdd_npu: DCDC_REG4 {
255 regulator-name
256 regulator-alwa
257 regulator-boot
258 regulator-min-
259 regulator-max-
260 regulator-ramp
261 regulator-init
262
263 regulator-stat
264 regula
265 };
266 };
267
268 vcc_1v8: DCDC_REG5 {
269 regulator-name
270 regulator-alwa
271 regulator-boot
272 regulator-min-
273 regulator-max-
274
275 regulator-stat
276 regula
277 };
278 };
279
280 vdda0v9_image: LDO_REG
281 regulator-name
282 regulator-boot
283 regulator-alwa
284 regulator-min-
285 regulator-max-
286
287 regulator-stat
288 regula
289 };
290 };
291
292 vdda_0v9: LDO_REG2 {
293 regulator-name
294 regulator-alwa
295 regulator-boot
296 regulator-min-
297 regulator-max-
298
299 regulator-stat
300 regula
301 };
302 };
303
304 vdda0v9_pmu: LDO_REG3
305 regulator-name
306 regulator-alwa
307 regulator-boot
308 regulator-min-
309 regulator-max-
310
311 regulator-stat
312 regula
313 regula
314 };
315 };
316
317 vccio_acodec: LDO_REG4
318 regulator-name
319 regulator-alwa
320 regulator-boot
321 regulator-min-
322 regulator-max-
323
324 regulator-stat
325 regula
326 };
327 };
328
329 vccio_sd: LDO_REG5 {
330 regulator-name
331 regulator-alwa
332 regulator-boot
333 regulator-min-
334 regulator-max-
335
336 regulator-stat
337 regula
338 };
339 };
340
341 vcc3v3_pmu: LDO_REG6 {
342 regulator-name
343 regulator-alwa
344 regulator-boot
345 regulator-min-
346 regulator-max-
347
348 regulator-stat
349 regula
350 regula
351 };
352 };
353
354 vcca_1v8: LDO_REG7 {
355 regulator-name
356 regulator-alwa
357 regulator-boot
358 regulator-min-
359 regulator-max-
360
361 regulator-stat
362 regula
363 };
364 };
365
366 vcca1v8_pmu: LDO_REG8
367 regulator-name
368 regulator-alwa
369 regulator-boot
370 regulator-min-
371 regulator-max-
372
373 regulator-stat
374 regula
375 regula
376 };
377 };
378
379 vcca1v8_image: LDO_REG
380 regulator-name
381 regulator-alwa
382 regulator-boot
383 regulator-min-
384 regulator-max-
385
386 regulator-stat
387 regula
388 };
389 };
390
391 vcc_3v3: SWITCH_REG1 {
392 regulator-name
393 regulator-alwa
394 regulator-boot
395
396 regulator-stat
397 regula
398 };
399 };
400
401 vcc3v3_sd: SWITCH_REG2
402 regulator-name
403 regulator-alwa
404 regulator-boot
405
406 regulator-stat
407 regula
408 };
409 };
410 };
411 };
412 };
413
414 &i2s1_8ch {
415 rockchip,trcm-sync-tx-only;
416 status = "okay";
417 };
418
419 &gmac1 {
420 phy-mode = "rgmii";
421 clock_in_out = "output";
422 snps,reset-gpio = <&gpio2 RK_PB0 GPIO_
423 snps,reset-active-low;
424 /* Reset time is 75ms, 100ms */
425 snps,reset-delays-us = <0 75000 100000
426 assigned-clocks = <&cru SCLK_GMAC1_RX_
427 assigned-clock-parents = <&cru SCLK_GM
428 assigned-clock-rates = <0>, <125000000
429 pinctrl-names = "default";
430 pinctrl-0 = <&gmac1m1_miim
431 &gmac1m1_tx_bus2_level
432 &gmac1m1_rx_bus2
433 &gmac1m1_rgmii_clk_lev
434 &gmac1m1_rgmii_bus_lev
435 tx_delay = <0x1a>;
436 rx_delay = <0x0c>;
437 phy-handle = <&rgmii_phy1>;
438 status = "okay";
439 };
440
441 &mdio1 {
442 rgmii_phy1: phy@0 {
443 compatible = "ethernet-phy-iee
444 reg = <0x0>;
445 };
446 };
447
448 &pcie2x1 {
449 reset-gpios = <&gpio0 RK_PB6 GPIO_ACTI
450 vpcie3v3-supply = <&vcc3v3_pcie>;
451 status = "okay";
452 };
453
454 &pinctrl {
455 leds {
456 sys_led_pin: sys-status-led-pi
457 rockchip,pins = <0 RK_
458 };
459 };
460
461 usb {
462 vcc5v0_usb20_host_en: vcc5v0-u
463 rockchip,pins = <2 RK_
464 };
465
466 vcc5v0_usb30_host_en: vcc5v0-u
467 rockchip,pins = <2 RK_
468 };
469 };
470
471 pmic {
472 pmic_int: pmic_int {
473 rockchip,pins =
474 <0 RK_PA3 RK_F
475 };
476 };
477 };
478
479 &pmu_io_domains {
480 pmuio2-supply = <&vcc3v3_pmu>;
481 vccio1-supply = <&vccio_acodec>;
482 vccio3-supply = <&vccio_sd>;
483 vccio4-supply = <&vcc_3v3>;
484 vccio5-supply = <&vcc_3v3>;
485 vccio6-supply = <&vcc_1v8>;
486 vccio7-supply = <&vcc_3v3>;
487 status = "okay";
488 };
489
490 &saradc {
491 vref-supply = <&vcca_1v8>;
492 status = "okay";
493 };
494
495 &tsadc {
496 rockchip,hw-tshut-mode = <1>;
497 rockchip,hw-tshut-polarity = <0>;
498 status = "okay";
499 };
500
501 &sdhci {
502 assigned-clocks = <&cru BCLK_EMMC>, <&
503 assigned-clock-rates = <200000000>, <2
504 bus-width = <8>;
505 max-frequency = <200000000>;
506 mmc-hs200-1_8v;
507 non-removable;
508 pinctrl-names = "default";
509 pinctrl-0 = <&emmc_bus8 &emmc_clk &emm
510 status = "okay";
511 };
512
513 &sdmmc0 {
514 max-frequency = <150000000>;
515 supports-sd;
516 bus-width = <4>;
517 cap-mmc-highspeed;
518 cap-sd-highspeed;
519 disable-wp;
520 sd-uhs-sdr104;
521 vmmc-supply = <&vcc3v3_sd>;
522 vqmmc-supply = <&vccio_sd>;
523 pinctrl-names = "default";
524 pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk
525 status = "okay";
526 };
527
528 /* USB OTG/USB Host_1 USB 2.0 Comb */
529 &usb2phy0 {
530 status = "okay";
531 };
532
533 &usb2phy0_host {
534 status = "okay";
535 };
536
537 &usb2phy0_otg {
538 status = "okay";
539 };
540
541 &usb_host0_ehci {
542 status = "okay";
543 };
544
545 &usb_host0_ohci {
546 status = "okay";
547 };
548
549 /* USB Host_2/USB Host_3 USB 2.0 Comb */
550 &usb2phy1 {
551 status = "okay";
552 };
553
554 &usb2phy1_host {
555 status = "okay";
556 };
557
558 &usb2phy1_otg {
559 status = "okay";
560 };
561
562 &usb_host1_ehci {
563 status = "okay";
564 };
565
566 &usb_host1_ohci {
567 status = "okay";
568 };
569
570 /* USB3.0 Host */
571 &usb_host1_xhci {
572 status = "okay";
573 };
574
575 &vop {
576 assigned-clocks = <&cru DCLK_VOP0>, <&
577 assigned-clock-parents = <&pmucru PLL_
578 status = "okay";
579 };
580
581 &vop_mmu {
582 status = "okay";
583 };
584
585 &vp0 {
586 vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_E
587 reg = <ROCKCHIP_VOP2_EP_HDMI0>
588 remote-endpoint = <&hdmi_in_vp
589 };
590 };
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