1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2
3 /dts-v1/;
4
5 #include <dt-bindings/gpio/gpio.h>
6 #include <dt-bindings/pinctrl/rockchip.h>
7 #include <dt-bindings/soc/rockchip,vop2.h>
8 #include "rk3566.dtsi"
9
10 / {
11 model = "Pine64 Quartz64 Model B";
12 compatible = "pine64,quartz64-b", "roc
13
14 aliases {
15 ethernet0 = &gmac1;
16 mmc0 = &sdmmc0;
17 mmc1 = &sdhci;
18 mmc2 = &sdmmc1;
19 };
20
21 chosen: chosen {
22 stdout-path = "serial2:1500000
23 };
24
25 gmac1_clkin: external-gmac1-clock {
26 compatible = "fixed-clock";
27 clock-frequency = <125000000>;
28 clock-output-names = "gmac1_cl
29 #clock-cells = <0>;
30 };
31
32 hdmi-con {
33 compatible = "hdmi-connector";
34 type = "a";
35
36 port {
37 hdmi_con_in: endpoint
38 remote-endpoin
39 };
40 };
41 };
42
43 leds {
44 compatible = "gpio-leds";
45
46 led-user {
47 label = "user-led";
48 default-state = "on";
49 gpios = <&gpio0 RK_PA0
50 linux,default-trigger
51 pinctrl-names = "defau
52 pinctrl-0 = <&user_led
53 retain-state-suspended
54 };
55 };
56
57 sound {
58 compatible = "simple-audio-car
59 simple-audio-card,format = "i2
60 simple-audio-card,name = "Anal
61 simple-audio-card,mclk-fs = <2
62
63 simple-audio-card,cpu {
64 sound-dai = <&i2s1_8ch
65 };
66
67 simple-audio-card,codec {
68 sound-dai = <&rk809>;
69 };
70 };
71
72 sdio_pwrseq: sdio-pwrseq {
73 status = "okay";
74 compatible = "mmc-pwrseq-simpl
75 clocks = <&rk809 1>;
76 clock-names = "ext_clock";
77 pinctrl-names = "default";
78 pinctrl-0 = <&wifi_enable_h>;
79 reset-gpios = <&gpio0 RK_PC0 G
80 post-power-on-delay-ms = <100>
81 power-off-delay-us = <5000000>
82 };
83
84 vcc3v3_pcie_p: vcc3v3-pcie-p-regulator
85 compatible = "regulator-fixed"
86 enable-active-high;
87 gpio = <&gpio0 RK_PA6 GPIO_ACT
88 pinctrl-names = "default";
89 pinctrl-0 = <&pcie_enable_h>;
90 regulator-name = "vcc3v3_pcie_
91 regulator-min-microvolt = <330
92 regulator-max-microvolt = <330
93 vin-supply = <&vcc_3v3>;
94 };
95
96 vcc5v0_in: vcc5v0-in-regulator {
97 compatible = "regulator-fixed"
98 regulator-name = "vcc5v0_in";
99 regulator-always-on;
100 regulator-boot-on;
101 regulator-min-microvolt = <500
102 regulator-max-microvolt = <500
103 };
104
105 vcc5v0_sys: vcc5v0-sys-regulator {
106 compatible = "regulator-fixed"
107 regulator-name = "vcc5v0_sys";
108 regulator-always-on;
109 regulator-boot-on;
110 regulator-min-microvolt = <500
111 regulator-max-microvolt = <500
112 vin-supply = <&vcc5v0_in>;
113 };
114
115 vcc3v3_sys: vcc3v3-sys-regulator {
116 compatible = "regulator-fixed"
117 regulator-name = "vcc3v3_sys";
118 regulator-min-microvolt = <330
119 regulator-max-microvolt = <330
120 regulator-always-on;
121 vin-supply = <&vcc5v0_sys>;
122 };
123
124 vcc5v0_usb30_host: vcc5v0-usb30-host-r
125 compatible = "regulator-fixed"
126 regulator-name = "vcc5v0_usb30
127 enable-active-high;
128 gpio = <&gpio0 RK_PC5 GPIO_ACT
129 pinctrl-names = "default";
130 pinctrl-0 = <&vcc5v0_usb30_hos
131 regulator-always-on;
132 regulator-min-microvolt = <500
133 regulator-max-microvolt = <500
134 vin-supply = <&vcc5v0_sys>;
135 };
136
137 vcc5v0_usb_otg: vcc5v0-usb-otg-regulat
138 compatible = "regulator-fixed"
139 regulator-name = "vcc5v0_usb_o
140 enable-active-high;
141 gpio = <&gpio0 RK_PC6 GPIO_ACT
142 pinctrl-names = "default";
143 pinctrl-0 = <&vcc5v0_usb_otg_e
144 regulator-always-on;
145 regulator-min-microvolt = <500
146 regulator-max-microvolt = <500
147 vin-supply = <&vcc5v0_sys>;
148 };
149 };
150
151 &combphy1 {
152 status = "okay";
153 };
154
155 &combphy2 {
156 status = "okay";
157 };
158
159 &cpu0 {
160 cpu-supply = <&vdd_cpu>;
161 };
162
163 &cpu1 {
164 cpu-supply = <&vdd_cpu>;
165 };
166
167 &cpu2 {
168 cpu-supply = <&vdd_cpu>;
169 };
170
171 &cpu3 {
172 cpu-supply = <&vdd_cpu>;
173 };
174
175 &gmac1 {
176 assigned-clocks = <&cru SCLK_GMAC1_RX_
177 assigned-clock-parents = <&cru SCLK_GM
178 clock_in_out = "input";
179 phy-mode = "rgmii";
180 phy-supply = <&vcc_3v3>;
181 pinctrl-names = "default";
182 pinctrl-0 = <&gmac1m1_miim
183 &gmac1m1_tx_bus2
184 &gmac1m1_rx_bus2
185 &gmac1m1_rgmii_clk
186 &gmac1m1_clkinout
187 &gmac1m1_rgmii_bus>;
188 snps,reset-gpio = <&gpio3 RK_PC0 GPIO_
189 snps,reset-active-low;
190 /* Reset time is 20ms, 100ms for rtl82
191 snps,reset-delays-us = <0 20000 100000
192 tx_delay = <0x4f>;
193 rx_delay = <0x24>;
194 phy-handle = <&rgmii_phy1>;
195 status = "okay";
196 };
197
198 &gpu {
199 mali-supply = <&vdd_gpu>;
200 status = "okay";
201 };
202
203 &hdmi {
204 avdd-0v9-supply = <&vdda0v9_image>;
205 avdd-1v8-supply = <&vcca1v8_image>;
206 status = "okay";
207 };
208
209 &hdmi_in {
210 hdmi_in_vp0: endpoint {
211 remote-endpoint = <&vp0_out_hd
212 };
213 };
214
215 &hdmi_out {
216 hdmi_out_con: endpoint {
217 remote-endpoint = <&hdmi_con_i
218 };
219 };
220
221 &hdmi_sound {
222 status = "okay";
223 };
224
225 &i2c0 {
226 status = "okay";
227
228 vdd_cpu: regulator@1c {
229 compatible = "tcs,tcs4525";
230 reg = <0x1c>;
231 fcs,suspend-voltage-selector =
232 regulator-name = "vdd_cpu";
233 regulator-min-microvolt = <800
234 regulator-max-microvolt = <115
235 regulator-ramp-delay = <2300>;
236 regulator-always-on;
237 regulator-boot-on;
238 vin-supply = <&vcc5v0_sys>;
239
240 regulator-state-mem {
241 regulator-off-in-suspe
242 };
243 };
244
245 rk809: pmic@20 {
246 compatible = "rockchip,rk809";
247 reg = <0x20>;
248 interrupt-parent = <&gpio0>;
249 interrupts = <RK_PA3 IRQ_TYPE_
250 assigned-clocks = <&cru I2S1_M
251 assigned-clock-parents = <&cru
252 clock-names = "mclk";
253 clocks = <&cru I2S1_MCLKOUT_TX
254 clock-output-names = "rk808-cl
255
256 pinctrl-names = "default";
257 pinctrl-0 = <&pmic_int>, <&i2s
258 rockchip,system-power-controll
259 #sound-dai-cells = <0>;
260 wakeup-source;
261 #clock-cells = <1>;
262
263 vcc1-supply = <&vcc3v3_sys>;
264 vcc2-supply = <&vcc3v3_sys>;
265 vcc3-supply = <&vcc3v3_sys>;
266 vcc4-supply = <&vcc3v3_sys>;
267 vcc5-supply = <&vcc3v3_sys>;
268 vcc6-supply = <&vcc3v3_sys>;
269 vcc7-supply = <&vcc3v3_sys>;
270 vcc8-supply = <&vcc3v3_sys>;
271 vcc9-supply = <&vcc3v3_sys>;
272
273 regulators {
274 vdd_log: DCDC_REG1 {
275 regulator-name
276 regulator-alwa
277 regulator-boot
278 regulator-min-
279 regulator-max-
280 regulator-ramp
281
282 regulator-stat
283 regula
284 regula
285 };
286 };
287
288 vdd_gpu: DCDC_REG2 {
289 regulator-name
290 regulator-alwa
291 regulator-boot
292 regulator-min-
293 regulator-max-
294 regulator-ramp
295
296 regulator-stat
297 regula
298 regula
299 };
300 };
301
302 vcc_ddr: DCDC_REG3 {
303 regulator-name
304 regulator-alwa
305 regulator-boot
306 regulator-init
307 regulator-stat
308 regula
309 };
310 };
311
312 vdd_npu: DCDC_REG4 {
313 regulator-name
314 regulator-min-
315 regulator-max-
316 regulator-init
317 regulator-stat
318 regula
319 };
320 };
321
322 vcc_1v8: DCDC_REG5 {
323 regulator-name
324 regulator-alwa
325 regulator-boot
326 regulator-min-
327 regulator-max-
328
329 regulator-stat
330 regula
331 regula
332 };
333 };
334
335 vdda0v9_image: LDO_REG
336 regulator-name
337 regulator-alwa
338 regulator-boot
339 regulator-min-
340 regulator-max-
341
342 regulator-stat
343 regula
344 regula
345 };
346 };
347
348 vdda_0v9: LDO_REG2 {
349 regulator-name
350 regulator-alwa
351 regulator-boot
352 regulator-min-
353 regulator-max-
354
355 regulator-stat
356 regula
357 regula
358 };
359 };
360
361 vdda0v9_pmu: LDO_REG3
362 regulator-name
363 regulator-alwa
364 regulator-boot
365 regulator-min-
366 regulator-max-
367 regulator-stat
368 regula
369 regula
370 };
371 };
372
373 vccio_acodec: LDO_REG4
374 regulator-name
375 regulator-alwa
376 regulator-boot
377 regulator-min-
378 regulator-max-
379
380 regulator-stat
381 regula
382 regula
383
384 };
385 };
386
387 vccio_sd: LDO_REG5 {
388 regulator-name
389 regulator-alwa
390 regulator-boot
391 regulator-min-
392 regulator-max-
393
394 regulator-stat
395 regula
396 regula
397 };
398 };
399
400 vcc3v3_pmu: LDO_REG6 {
401 regulator-name
402 regulator-alwa
403 regulator-boot
404 regulator-min-
405 regulator-max-
406
407 regulator-stat
408 regula
409 regula
410 };
411 };
412
413 vcca_1v8: LDO_REG7 {
414 regulator-name
415 regulator-alwa
416 regulator-boot
417 regulator-min-
418 regulator-max-
419
420 regulator-stat
421 regula
422 regula
423 };
424 };
425
426 vcca1v8_pmu: LDO_REG8
427 regulator-name
428 regulator-alwa
429 regulator-boot
430 regulator-min-
431 regulator-max-
432
433 regulator-stat
434 regula
435 regula
436 };
437 };
438
439 vcca1v8_image: LDO_REG
440 regulator-name
441 regulator-alwa
442 regulator-boot
443 regulator-min-
444 regulator-max-
445
446 regulator-stat
447 regula
448 regula
449 };
450 };
451
452 vcc_3v3: SWITCH_REG1 {
453 regulator-boot
454 regulator-name
455 };
456
457 vcc3v3_sd: SWITCH_REG2
458 regulator-name
459 };
460 };
461 };
462 };
463
464 /* i2c2_m1 exposed on csi port, pulled up to v
465 &i2c2 {
466 pinctrl-names = "default";
467 pinctrl-0 = <&i2c2m1_xfer>;
468 status = "okay";
469 };
470
471 /* i2c3_m1 exposed on dsi port, pulled up to v
472 &i2c3 {
473 pinctrl-names = "default";
474 pinctrl-0 = <&i2c3m1_xfer>;
475 status = "okay";
476 };
477
478 /*
479 * i2c4_m0 is exposed on PI40, pulled up to vc
480 * pin 27 - i2c4_sda_m0
481 * pin 28 - i2c4_scl_m0
482 */
483 &i2c4 {
484 status = "okay";
485 };
486
487 /*
488 * i2c5_m0 is exposed on PI40
489 * pin 29 - i2c5_scl_m0
490 * pin 31 - i2c5_sda_m0
491 */
492 &i2c5 {
493 status = "disabled";
494 };
495
496 &i2s0_8ch {
497 status = "okay";
498 };
499
500 &i2s1_8ch {
501 pinctrl-names = "default";
502 pinctrl-0 = <&i2s1m0_sclktx
503 &i2s1m0_lrcktx
504 &i2s1m0_sdi0
505 &i2s1m0_sdo0>;
506 rockchip,trcm-sync-tx-only;
507 status = "okay";
508 };
509
510 &mdio1 {
511 rgmii_phy1: ethernet-phy@1 {
512 compatible = "ethernet-phy-iee
513 reg = <0x1>;
514 };
515 };
516
517 &pcie2x1 {
518 pinctrl-names = "default";
519 pinctrl-0 = <&pcie_reset_h>;
520 reset-gpios = <&gpio1 RK_PB2 GPIO_ACTI
521 vpcie3v3-supply = <&vcc3v3_pcie_p>;
522 status = "okay";
523 };
524
525 &pinctrl {
526 bt {
527 bt_enable_h: bt-enable-h {
528 rockchip,pins = <0 RK_
529 };
530
531 bt_host_wake_l: bt-host-wake-l
532 rockchip,pins = <0 RK_
533 };
534
535 bt_wake_l: bt-wake-l {
536 rockchip,pins = <0 RK_
537 };
538 };
539
540 leds {
541 user_led_enable_h: user-led-en
542 rockchip,pins = <0 RK_
543 };
544 };
545
546 pcie {
547 pcie_enable_h: pcie-enable-h {
548 rockchip,pins = <0 RK_
549 };
550
551 pcie_reset_h: pcie-reset-h {
552 rockchip,pins = <1 RK_
553 };
554 };
555
556 pmic {
557 pmic_int: pmic_int {
558 rockchip,pins =
559 <0 RK_PA3 RK_F
560 };
561 };
562
563 sdio-pwrseq {
564 wifi_enable_h: wifi-enable-h {
565 rockchip,pins = <0 RK_
566 };
567 };
568
569 usb {
570 vcc5v0_usb30_host_en_h: vcc5v0
571 rockchip,pins = <0 RK_
572 };
573
574 vcc5v0_usb_otg_en_h: vcc5v0-us
575 rockchip,pins = <0 RK_
576 };
577 };
578 };
579
580 &pmu_io_domains {
581 status = "okay";
582 pmuio1-supply = <&vcc3v3_pmu>;
583 pmuio2-supply = <&vcca1v8_pmu>;
584 vccio1-supply = <&vccio_acodec>;
585 vccio2-supply = <&vcc_1v8>;
586 vccio3-supply = <&vccio_sd>;
587 vccio4-supply = <&vcca1v8_pmu>;
588 vccio5-supply = <&vcc_3v3>;
589 vccio6-supply = <&vcc_3v3>;
590 vccio7-supply = <&vcc_3v3>;
591 };
592
593 &saradc {
594 vref-supply = <&vcca_1v8>;
595 status = "okay";
596 };
597
598 &sdhci {
599 bus-width = <8>;
600 mmc-hs200-1_8v;
601 non-removable;
602 vmmc-supply = <&vcc_3v3>;
603 vqmmc-supply = <&vcc_1v8>;
604 status = "okay";
605 };
606
607 &sdmmc0 {
608 bus-width = <4>;
609 cap-sd-highspeed;
610 cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_
611 disable-wp;
612 pinctrl-names = "default";
613 pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk
614 sd-uhs-sdr50;
615 vmmc-supply = <&vcc3v3_sd>;
616 vqmmc-supply = <&vccio_sd>;
617 status = "okay";
618 };
619
620 &sdmmc1 {
621 bus-width = <4>;
622 cap-sd-highspeed;
623 cap-sdio-irq;
624 keep-power-in-suspend;
625 mmc-pwrseq = <&sdio_pwrseq>;
626 non-removable;
627 pinctrl-names = "default";
628 pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_cmd
629 vmmc-supply = <&vcc3v3_sys>;
630 vqmmc-supply = <&vcca1v8_pmu>;
631 status = "okay";
632 };
633
634 &sfc {
635 pinctrl-0 = <&fspi_pins>;
636 pinctrl-names = "default";
637 #address-cells = <1>;
638 #size-cells = <0>;
639 status = "okay";
640
641 flash@0 {
642 compatible = "jedec,spi-nor";
643 reg = <0>;
644 spi-max-frequency = <24000000>
645 spi-rx-bus-width = <4>;
646 spi-tx-bus-width = <1>;
647 };
648 };
649
650 &tsadc {
651 rockchip,hw-tshut-mode = <1>;
652 rockchip,hw-tshut-polarity = <0>;
653 status = "okay";
654 };
655
656 &uart1 {
657 dma-names = "tx", "rx";
658 pinctrl-names = "default";
659 pinctrl-0 = <&uart1m0_xfer &uart1m0_ct
660 status = "okay";
661 uart-has-rtscts;
662
663 bluetooth {
664 compatible = "brcm,bcm4345c5";
665 clocks = <&rk809 1>;
666 clock-names = "lpo";
667 device-wakeup-gpios = <&gpio0
668 host-wakeup-gpios = <&gpio0 RK
669 shutdown-gpios = <&gpio0 RK_PC
670 pinctrl-names = "default";
671 pinctrl-0 = <&bt_host_wake_l &
672 vbat-supply = <&vcc3v3_sys>;
673 vddio-supply = <&vcca1v8_pmu>;
674 };
675 };
676
677 /*
678 * uart2_m0 is exposed on PI40
679 * pin 8 - uart2_tx_m0
680 * pin 10 - uart2_rx_m0
681 */
682 &uart2 {
683 status = "okay";
684 };
685
686 &usb2phy0_host {
687 phy-supply = <&vcc5v0_usb30_host>;
688 status = "okay";
689 };
690
691 &usb2phy0_otg {
692 phy-supply = <&vcc5v0_usb_otg>;
693 status = "okay";
694 };
695
696 &usb2phy1_otg {
697 phy-supply = <&vcc5v0_usb30_host>;
698 status = "okay";
699 };
700
701 &usb2phy0 {
702 status = "okay";
703 };
704
705 &usb2phy1 {
706 status = "okay";
707 };
708
709 &usb_host0_xhci {
710 status = "okay";
711 };
712
713 &usb_host1_xhci {
714 status = "okay";
715 };
716
717 &usb_host0_ehci {
718 status = "okay";
719 };
720
721 &usb_host0_ohci {
722 status = "okay";
723 };
724
725 &vop {
726 assigned-clocks = <&cru DCLK_VOP0>, <&
727 assigned-clock-parents = <&pmucru PLL_
728 status = "okay";
729 };
730
731 &vop_mmu {
732 status = "okay";
733 };
734
735 &vp0 {
736 vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_E
737 reg = <ROCKCHIP_VOP2_EP_HDMI0>
738 remote-endpoint = <&hdmi_in_vp
739 };
740 };
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