1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 2
3 /dts-v1/; 3 /dts-v1/;
4 4
5 #include "rk3566-radxa-zero-3.dtsi" 5 #include "rk3566-radxa-zero-3.dtsi"
6 6
7 / { 7 / {
8 model = "Radxa ZERO 3E"; 8 model = "Radxa ZERO 3E";
9 compatible = "radxa,zero-3e", "rockchi 9 compatible = "radxa,zero-3e", "rockchip,rk3566";
10 10
11 aliases { 11 aliases {
12 ethernet0 = &gmac1; 12 ethernet0 = &gmac1;
13 mmc0 = &sdmmc0; 13 mmc0 = &sdmmc0;
14 }; 14 };
15 }; 15 };
16 16
17 &gmac1 { 17 &gmac1 {
18 assigned-clocks = <&cru SCLK_GMAC1_RX_ 18 assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
19 assigned-clock-parents = <&cru SCLK_GM 19 assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru CLK_MAC1_2TOP>;
20 clock_in_out = "input"; 20 clock_in_out = "input";
21 phy-handle = <&rgmii_phy1>; 21 phy-handle = <&rgmii_phy1>;
22 phy-mode = "rgmii-id"; 22 phy-mode = "rgmii-id";
23 phy-supply = <&vcc_3v3>; 23 phy-supply = <&vcc_3v3>;
24 pinctrl-names = "default"; 24 pinctrl-names = "default";
25 pinctrl-0 = <&gmac1m1_miim 25 pinctrl-0 = <&gmac1m1_miim
26 &gmac1m1_tx_bus2 26 &gmac1m1_tx_bus2
27 &gmac1m1_rx_bus2 27 &gmac1m1_rx_bus2
28 &gmac1m1_rgmii_clk 28 &gmac1m1_rgmii_clk
29 &gmac1m1_rgmii_bus 29 &gmac1m1_rgmii_bus
30 &gmac1m1_clkinout>; 30 &gmac1m1_clkinout>;
31 status = "okay"; 31 status = "okay";
32 }; 32 };
33 33
34 &mdio1 { 34 &mdio1 {
35 rgmii_phy1: ethernet-phy@1 { 35 rgmii_phy1: ethernet-phy@1 {
36 compatible = "ethernet-phy-iee 36 compatible = "ethernet-phy-ieee802.3-c22";
37 reg = <1>; 37 reg = <1>;
38 pinctrl-names = "default"; 38 pinctrl-names = "default";
39 pinctrl-0 = <&gmac1_rstn>; 39 pinctrl-0 = <&gmac1_rstn>;
40 reset-assert-us = <20000>; 40 reset-assert-us = <20000>;
41 reset-deassert-us = <50000>; 41 reset-deassert-us = <50000>;
42 reset-gpios = <&gpio3 RK_PC0 G 42 reset-gpios = <&gpio3 RK_PC0 GPIO_ACTIVE_LOW>;
43 }; 43 };
44 }; 44 };
45 45
46 &pinctrl { 46 &pinctrl {
47 gmac1 { 47 gmac1 {
48 gmac1_rstn: gmac1-rstn { 48 gmac1_rstn: gmac1-rstn {
49 rockchip,pins = <3 RK_ 49 rockchip,pins = <3 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>;
50 }; 50 };
51 }; 51 };
52 }; 52 };
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