1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2
3 /dts-v1/;
4
5 #include <dt-bindings/gpio/gpio.h>
6 #include <dt-bindings/pinctrl/rockchip.h>
7 #include <dt-bindings/soc/rockchip,vop2.h>
8 #include "rk3566.dtsi"
9
10 / {
11 model = "Firefly Station M2";
12 compatible = "firefly,rk3566-roc-pc",
13
14 aliases {
15 ethernet0 = &gmac1;
16 mmc0 = &sdmmc0;
17 mmc1 = &sdhci;
18 mmc2 = &sdmmc1;
19 };
20
21 chosen: chosen {
22 stdout-path = "serial2:1500000
23 };
24
25 gmac1_clkin: external-gmac1-clock {
26 compatible = "fixed-clock";
27 clock-frequency = <125000000>;
28 clock-output-names = "gmac1_cl
29 #clock-cells = <0>;
30 };
31
32 hdmi-con {
33 compatible = "hdmi-connector";
34 type = "a";
35
36 port {
37 hdmi_con_in: endpoint
38 remote-endpoin
39 };
40 };
41 };
42
43 leds {
44 compatible = "gpio-leds";
45
46 led-user {
47 label = "user-led";
48 default-state = "on";
49 gpios = <&gpio0 RK_PD3
50 linux,default-trigger
51 pinctrl-names = "defau
52 pinctrl-0 = <&user_led
53 retain-state-suspended
54 };
55 };
56
57 rk809-sound {
58 compatible = "simple-audio-car
59 simple-audio-card,format = "i2
60 simple-audio-card,name = "STAT
61 simple-audio-card,mclk-fs = <2
62 status = "okay";
63
64 simple-audio-card,cpu {
65 sound-dai = <&i2s1_8ch
66 };
67
68 simple-audio-card,codec {
69 sound-dai = <&rk809>;
70 };
71 };
72
73 sdio_pwrseq: sdio-pwrseq {
74 status = "okay";
75 compatible = "mmc-pwrseq-simpl
76 clocks = <&rk809 1>;
77 clock-names = "ext_clock";
78 pinctrl-names = "default";
79 pinctrl-0 = <&wifi_enable_h>;
80 reset-gpios = <&gpio2 RK_PB1 G
81 };
82
83 usb_5v: usb-5v-regulator {
84 compatible = "regulator-fixed"
85 regulator-name = "usb_5v";
86 regulator-always-on;
87 regulator-boot-on;
88 regulator-min-microvolt = <500
89 regulator-max-microvolt = <500
90 };
91
92 vcc5v0_sys: vcc5v0-sys-regulator {
93 compatible = "regulator-fixed"
94 regulator-name = "vcc5v0_sys";
95 regulator-always-on;
96 regulator-boot-on;
97 regulator-min-microvolt = <500
98 regulator-max-microvolt = <500
99 vin-supply = <&usb_5v>;
100 };
101
102 vcc3v3_pcie: vcc3v3-pcie-regulator {
103 compatible = "regulator-fixed"
104 enable-active-high;
105 gpio = <&gpio0 RK_PC4 GPIO_ACT
106 pinctrl-names = "default";
107 pinctrl-0 = <&pcie_enable_h>;
108 regulator-name = "vcc3v3_pcie"
109 regulator-min-microvolt = <330
110 regulator-max-microvolt = <330
111 vin-supply = <&vcc5v0_sys>;
112 };
113
114 vcc3v3_sys: vcc3v3-sys-regulator {
115 compatible = "regulator-fixed"
116 regulator-name = "vcc3v3_sys";
117 regulator-min-microvolt = <330
118 regulator-max-microvolt = <330
119 regulator-always-on;
120 vin-supply = <&vcc5v0_sys>;
121 };
122
123 vcc5v0_usb30_host: vcc5v0-usb30-host-r
124 compatible = "regulator-fixed"
125 regulator-name = "vcc5v0_usb30
126 enable-active-high;
127 gpio = <&gpio0 RK_PC5 GPIO_ACT
128 pinctrl-names = "default";
129 pinctrl-0 = <&vcc5v0_usb30_hos
130 regulator-always-on;
131 regulator-min-microvolt = <500
132 regulator-max-microvolt = <500
133 vin-supply = <&vcc5v0_sys>;
134 };
135
136 vcc5v0_usb_otg: vcc5v0-usb-otg-regulat
137 compatible = "regulator-fixed"
138 regulator-name = "vcc5v0_usb_o
139 enable-active-high;
140 gpio = <&gpio0 RK_PC6 GPIO_ACT
141 pinctrl-names = "default";
142 pinctrl-0 = <&vcc5v0_usb_otg_e
143 regulator-always-on;
144 regulator-min-microvolt = <500
145 regulator-max-microvolt = <500
146 vin-supply = <&vcc5v0_sys>;
147 };
148 };
149
150 &combphy1 {
151 status = "okay";
152 };
153
154 &combphy2 {
155 status = "okay";
156 };
157
158 &cpu0 {
159 cpu-supply = <&vdd_cpu>;
160 };
161
162 &cpu1 {
163 cpu-supply = <&vdd_cpu>;
164 };
165
166 &cpu2 {
167 cpu-supply = <&vdd_cpu>;
168 };
169
170 &cpu3 {
171 cpu-supply = <&vdd_cpu>;
172 };
173
174 &gmac1 {
175 assigned-clocks = <&cru SCLK_GMAC1_RX_
176 assigned-clock-parents = <&cru SCLK_GM
177 clock_in_out = "input";
178 phy-mode = "rgmii";
179 phy-supply = <&vcc_3v3>;
180 pinctrl-names = "default";
181 pinctrl-0 = <&gmac1m0_miim
182 &gmac1m0_tx_bus2
183 &gmac1m0_rx_bus2
184 &gmac1m0_rgmii_clk
185 &gmac1m0_clkinout
186 &gmac1m0_rgmii_bus>;
187 snps,reset-gpio = <&gpio0 RK_PB7 GPIO_
188 snps,reset-active-low;
189 /* Reset time is 20ms, 100ms for rtl82
190 snps,reset-delays-us = <0 20000 100000
191 tx_delay = <0x4f>;
192 rx_delay = <0x24>;
193 phy-handle = <&rgmii_phy1>;
194 status = "okay";
195 };
196
197 &gpu {
198 mali-supply = <&vdd_gpu>;
199 status = "okay";
200 };
201
202 &hdmi {
203 avdd-0v9-supply = <&vdda0v9_image>;
204 avdd-1v8-supply = <&vcca1v8_image>;
205 status = "okay";
206 };
207
208 &hdmi_in {
209 hdmi_in_vp0: endpoint {
210 remote-endpoint = <&vp0_out_hd
211 };
212 };
213
214 &hdmi_out {
215 hdmi_out_con: endpoint {
216 remote-endpoint = <&hdmi_con_i
217 };
218 };
219
220 &hdmi_sound {
221 status = "okay";
222 };
223
224 &i2c0 {
225 status = "okay";
226
227 vdd_cpu: regulator@1c {
228 compatible = "tcs,tcs4525";
229 reg = <0x1c>;
230 fcs,suspend-voltage-selector =
231 regulator-name = "vdd_cpu";
232 regulator-min-microvolt = <800
233 regulator-max-microvolt = <115
234 regulator-ramp-delay = <2300>;
235 regulator-always-on;
236 regulator-boot-on;
237 vin-supply = <&vcc5v0_sys>;
238
239 regulator-state-mem {
240 regulator-off-in-suspe
241 };
242 };
243
244 rk809: pmic@20 {
245 compatible = "rockchip,rk809";
246 reg = <0x20>;
247 interrupt-parent = <&gpio0>;
248 interrupts = <RK_PA7 IRQ_TYPE_
249 clock-output-names = "rk808-cl
250 assigned-clocks = <&cru I2S1_M
251 assigned-clock-parents = <&cru
252 clock-names = "mclk";
253 clocks = <&cru I2S1_MCLKOUT_TX
254 pinctrl-names = "default";
255 pinctrl-0 = <&pmic_int>, <&i2s
256 rockchip,system-power-controll
257 wakeup-source;
258 #clock-cells = <1>;
259 #sound-dai-cells = <0>;
260
261 vcc1-supply = <&vcc3v3_sys>;
262 vcc2-supply = <&vcc3v3_sys>;
263 vcc3-supply = <&vcc3v3_sys>;
264 vcc4-supply = <&vcc3v3_sys>;
265 vcc5-supply = <&vcc3v3_sys>;
266 vcc6-supply = <&vcc3v3_sys>;
267 vcc7-supply = <&vcc3v3_sys>;
268 vcc8-supply = <&vcc3v3_sys>;
269 vcc9-supply = <&vcc3v3_sys>;
270
271 codec {
272 rockchip,mic-in-differ
273 };
274
275 regulators {
276 vdd_log: DCDC_REG1 {
277 regulator-name
278 regulator-alwa
279 regulator-boot
280 regulator-min-
281 regulator-max-
282 regulator-ramp
283
284 regulator-stat
285 regula
286 regula
287 };
288 };
289
290 vdd_gpu: DCDC_REG2 {
291 regulator-name
292 regulator-min-
293 regulator-max-
294 regulator-ramp
295
296 regulator-stat
297 regula
298 regula
299 };
300 };
301
302 vcc_ddr: DCDC_REG3 {
303 regulator-name
304 regulator-alwa
305 regulator-boot
306 regulator-min-
307 regulator-max-
308 regulator-init
309 regulator-stat
310 regula
311 };
312 };
313
314 vdd_npu: DCDC_REG4 {
315 regulator-name
316 regulator-min-
317 regulator-max-
318 regulator-init
319 regulator-stat
320 regula
321 };
322 };
323
324 vcc_1v8: DCDC_REG5 {
325 regulator-name
326 regulator-alwa
327 regulator-boot
328 regulator-min-
329 regulator-max-
330
331 regulator-stat
332 regula
333 regula
334 };
335 };
336
337 vdda0v9_image: LDO_REG
338 regulator-name
339 regulator-alwa
340 regulator-boot
341 regulator-min-
342 regulator-max-
343
344 regulator-stat
345 regula
346 regula
347 };
348 };
349
350 vdda_0v9: LDO_REG2 {
351 regulator-name
352 regulator-alwa
353 regulator-boot
354 regulator-min-
355 regulator-max-
356
357 regulator-stat
358 regula
359 regula
360 };
361 };
362
363 vdda0v9_pmu: LDO_REG3
364 regulator-name
365 regulator-alwa
366 regulator-boot
367 regulator-min-
368 regulator-max-
369 regulator-stat
370 regula
371 regula
372 };
373 };
374
375 vccio_acodec: LDO_REG4
376 regulator-name
377 regulator-alwa
378 regulator-boot
379 regulator-min-
380 regulator-max-
381
382 regulator-stat
383 regula
384 regula
385
386 };
387 };
388
389 vccio_sd: LDO_REG5 {
390 regulator-name
391 regulator-alwa
392 regulator-boot
393 regulator-min-
394 regulator-max-
395
396 regulator-stat
397 regula
398 regula
399 };
400 };
401
402 vcc3v3_pmu: LDO_REG6 {
403 regulator-name
404 regulator-alwa
405 regulator-boot
406 regulator-min-
407 regulator-max-
408
409 regulator-stat
410 regula
411 regula
412 };
413 };
414
415 vcca_1v8: LDO_REG7 {
416 regulator-name
417 regulator-alwa
418 regulator-boot
419 regulator-min-
420 regulator-max-
421
422 regulator-stat
423 regula
424 regula
425 };
426 };
427
428 vcca1v8_pmu: LDO_REG8
429 regulator-name
430 regulator-alwa
431 regulator-boot
432 regulator-min-
433 regulator-max-
434
435 regulator-stat
436 regula
437 regula
438 };
439 };
440
441 vcca1v8_image: LDO_REG
442 regulator-name
443 regulator-alwa
444 regulator-boot
445 regulator-min-
446 regulator-max-
447
448 regulator-stat
449 regula
450 regula
451 };
452 };
453
454 vcc_3v3: SWITCH_REG1 {
455 regulator-boot
456 regulator-name
457 };
458
459 vcc3v3_sd: SWITCH_REG2
460 regulator-name
461 regulator-alwa
462 regulator-boot
463 };
464 };
465 };
466 };
467
468 &i2c1 {
469 status = "okay";
470 };
471
472 &i2c2 {
473 status = "okay";
474 };
475
476 &i2c3 {
477 pinctrl-names = "default";
478 pinctrl-0 = <&i2c3m0_xfer>;
479 status = "okay";
480 };
481
482 &i2s0_8ch {
483 status = "okay";
484 };
485
486 &i2s1_8ch {
487 pinctrl-0 = <&i2s1m0_sclktx &i2s1m0_sc
488 &i2s1m0_lrcktx &i2s1m0
489 &i2s1m0_sdi0 &i2s1m0
490 rockchip,trcm-sync-tx-only;
491 status = "okay";
492 };
493
494 &mdio1 {
495 rgmii_phy1: ethernet-phy@0 {
496 compatible = "ethernet-phy-iee
497 reg = <0x0>;
498 };
499 };
500
501 &pcie2x1 {
502 pinctrl-names = "default";
503 pinctrl-0 = <&pcie_reset_h>;
504 reset-gpios = <&gpio1 RK_PB2 GPIO_ACTI
505 vpcie3v3-supply = <&vcc3v3_pcie>;
506 status = "okay";
507 };
508
509 &pinctrl {
510 bt {
511 bt_enable_h: bt-enable-h {
512 rockchip,pins = <0 RK_
513 };
514
515 bt_host_wake_l: bt-host-wake-l
516 rockchip,pins = <0 RK_
517 };
518
519 bt_wake_l: bt-wake-l {
520 rockchip,pins = <0 RK_
521 };
522 };
523
524 leds {
525 user_led_enable_h: user-led-en
526 rockchip,pins = <0 RK_
527 };
528 };
529
530 pcie {
531 pcie_enable_h: pcie-enable-h {
532 rockchip,pins = <0 RK_
533 };
534
535 pcie_reset_h: pcie-reset-h {
536 rockchip,pins = <1 RK_
537 };
538 };
539
540 pmic {
541 pmic_int: pmic_int {
542 rockchip,pins =
543 <0 RK_PA3 RK_F
544 };
545 };
546
547 sdio-pwrseq {
548 wifi_enable_h: wifi-enable-h {
549 rockchip,pins = <2 RK_
550 };
551 };
552
553 usb {
554 vcc5v0_usb30_host_en_h: vcc5v0
555 rockchip,pins = <0 RK_
556 };
557
558 vcc5v0_usb_otg_en_h: vcc5v0-us
559 rockchip,pins = <0 RK_
560 };
561 };
562 };
563
564 &pmu_io_domains {
565 status = "okay";
566 pmuio1-supply = <&vcc3v3_pmu>;
567 pmuio2-supply = <&vcc3v3_pmu>;
568 vccio1-supply = <&vccio_acodec>;
569 vccio2-supply = <&vcc_1v8>;
570 vccio3-supply = <&vccio_sd>;
571 vccio4-supply = <&vcc_1v8>;
572 vccio5-supply = <&vcc_3v3>;
573 vccio6-supply = <&vcc_1v8>;
574 vccio7-supply = <&vcc_3v3>;
575 };
576
577 &sdhci {
578 bus-width = <8>;
579 mmc-hs200-1_8v;
580 non-removable;
581 vmmc-supply = <&vcc_3v3>;
582 vqmmc-supply = <&vcc_1v8>;
583 status = "okay";
584 };
585
586 &sdmmc0 {
587 bus-width = <4>;
588 cap-sd-highspeed;
589 cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_
590 disable-wp;
591 pinctrl-names = "default";
592 pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk
593 sd-uhs-sdr104;
594 vmmc-supply = <&vcc3v3_sd>;
595 vqmmc-supply = <&vccio_sd>;
596 status = "okay";
597 };
598
599 &sdmmc1 {
600 bus-width = <4>;
601 cap-sd-highspeed;
602 cap-sdio-irq;
603 keep-power-in-suspend;
604 mmc-pwrseq = <&sdio_pwrseq>;
605 vmmc-supply = <&vcc3v3_sys>;
606 vqmmc-supply = <&vcca1v8_pmu>;
607 pinctrl-names = "default";
608 pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_cmd
609 status = "okay";
610 };
611
612 &tsadc {
613 status = "okay";
614 };
615
616 &uart0 {
617 pinctrl-names = "default";
618 pinctrl-0 = <&uart0_xfer>;
619 status = "okay";
620 };
621
622 &uart1 {
623 pinctrl-names = "default";
624 pinctrl-0 = <&uart1m0_xfer &uart1m0_ct
625 status = "okay";
626 uart-has-rtscts;
627
628 bluetooth {
629 compatible = "brcm,bcm43438-bt
630 clocks = <&rk809 1>;
631 clock-names = "lpo";
632 device-wakeup-gpios = <&gpio2
633 host-wakeup-gpios = <&gpio2 RK
634 shutdown-gpios = <&gpio2 RK_PB
635 pinctrl-names = "default";
636 pinctrl-0 = <&bt_host_wake_l &
637 vbat-supply = <&vcc3v3_sys>;
638 vddio-supply = <&vcca1v8_pmu>;
639 };
640 };
641
642 &uart2 {
643 status = "okay";
644 };
645
646 &usb2phy0_host {
647 phy-supply = <&vcc5v0_usb30_host>;
648 status = "okay";
649 };
650
651 &usb2phy0_otg {
652 phy-supply = <&vcc5v0_usb_otg>;
653 status = "okay";
654 };
655
656 &usb2phy1_otg {
657 phy-supply = <&vcc5v0_usb30_host>;
658 status = "okay";
659 };
660
661 &usb2phy0 {
662 status = "okay";
663 };
664
665 &usb2phy1 {
666 status = "okay";
667 };
668
669 &usb_host0_xhci {
670 status = "okay";
671 };
672
673 &usb_host1_xhci {
674 status = "okay";
675 };
676
677 &usb_host0_ehci {
678 status = "okay";
679 };
680
681 &usb_host0_ohci {
682 status = "okay";
683 };
684
685 &vop {
686 assigned-clocks = <&cru DCLK_VOP0>, <&
687 assigned-clock-parents = <&pmucru PLL_
688 status = "okay";
689 };
690
691 &vop_mmu {
692 status = "okay";
693 };
694
695 &vp0 {
696 vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_E
697 reg = <ROCKCHIP_VOP2_EP_HDMI0>
698 remote-endpoint = <&hdmi_in_vp
699 };
700 };
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