1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2
3 /*
4 * Copyright (c) 2021 Rockchip Electronics Co.
5 * Copyright (c) 2022 EmbedFire <embedfire@embe
6 */
7
8 /dts-v1/;
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/leds/common.h>
11 #include <dt-bindings/pinctrl/rockchip.h>
12 #include <dt-bindings/soc/rockchip,vop2.h>
13 #include "rk3568.dtsi"
14
15 / {
16 model = "EmbedFire LubanCat 2";
17 compatible = "embedfire,lubancat-2", "
18
19 aliases {
20 ethernet0 = &gmac0;
21 ethernet1 = &gmac1;
22 mmc0 = &sdmmc0;
23 mmc1 = &sdhci;
24 };
25
26 chosen: chosen {
27 stdout-path = "serial2:1500000
28 };
29
30 leds {
31 compatible = "gpio-leds";
32
33 user_led: user-led {
34 label = "user_led";
35 linux,default-trigger
36 default-state = "on";
37 gpios = <&gpio0 RK_PC7
38 pinctrl-names = "defau
39 pinctrl-0 = <&user_led
40 };
41 };
42
43 hdmi-con {
44 compatible = "hdmi-connector";
45 type = "a";
46
47 port {
48 hdmi_con_in: endpoint
49 remote-endpoin
50 };
51 };
52 };
53
54 dc_5v: dc-5v-regulator {
55 compatible = "regulator-fixed"
56 regulator-name = "dc_5v";
57 regulator-always-on;
58 regulator-boot-on;
59 regulator-min-microvolt = <500
60 regulator-max-microvolt = <500
61 };
62
63 vcc3v3_sys: vcc3v3-sys-regulator {
64 compatible = "regulator-fixed"
65 regulator-name = "vcc3v3_sys";
66 regulator-always-on;
67 regulator-boot-on;
68 regulator-min-microvolt = <330
69 regulator-max-microvolt = <330
70 vin-supply = <&vcc5v0_sys>;
71 };
72
73 vcc5v0_sys: vcc5v0-sys-regulator {
74 compatible = "regulator-fixed"
75 regulator-name = "vcc5v0_sys";
76 regulator-always-on;
77 regulator-boot-on;
78 regulator-min-microvolt = <500
79 regulator-max-microvolt = <500
80 vin-supply = <&dc_5v>;
81 };
82
83 vcc3v3_m2_pcie: vcc3v3-m2-pcie-regulat
84 compatible = "regulator-fixed"
85 regulator-name = "m2_pcie_3v3"
86 enable-active-high;
87 regulator-min-microvolt = <330
88 regulator-max-microvolt = <330
89 gpios = <&gpio0 RK_PD4 GPIO_AC
90 pinctrl-0 = <&vcc3v3_m2_pcie_e
91 pinctrl-names = "default";
92 startup-delay-us = <200000>;
93 vin-supply = <&vcc5v0_sys>;
94 };
95
96 vcc3v3_mini_pcie: vcc3v3-mini-pcie-reg
97 compatible = "regulator-fixed"
98 regulator-name = "minipcie_3v3
99 enable-active-high;
100 regulator-min-microvolt = <330
101 regulator-max-microvolt = <330
102 gpio = <&gpio3 RK_PC3 GPIO_ACT
103 pinctrl-0 = <&vcc3v3_mini_pcie
104 pinctrl-names = "default";
105 startup-delay-us = <5000>;
106 vin-supply = <&vcc5v0_sys>;
107 };
108
109 vcc5v0_usb20_host: vcc5v0-usb20-host-r
110 compatible = "regulator-fixed"
111 regulator-name = "vcc5v0_usb20
112 enable-active-high;
113 gpio = <&gpio0 RK_PD5 GPIO_ACT
114 pinctrl-0 = <&vcc5v0_usb20_hos
115 pinctrl-names = "default";
116 };
117
118 vcc5v0_usb30_host: vcc5v0-usb30-host-r
119 compatible = "regulator-fixed"
120 regulator-name = "vcc5v0_usb30
121 enable-active-high;
122 gpio = <&gpio0 RK_PD6 GPIO_ACT
123 pinctrl-0 = <&vcc5v0_usb30_hos
124 pinctrl-names = "default";
125 };
126
127 vcc5v0_otg_vbus: vcc5v0-otg-vbus-regul
128 compatible = "regulator-fixed"
129 regulator-name = "vcc5v0_otg_v
130 enable-active-high;
131 regulator-min-microvolt = <500
132 regulator-max-microvolt = <500
133 gpio = <&gpio0 RK_PD3 GPIO_ACT
134 pinctrl-0 = <&vcc5v0_otg_vbus_
135 pinctrl-names = "default";
136 };
137 };
138
139 &combphy0 {
140 status = "okay";
141 };
142
143 &combphy1 {
144 status = "okay";
145 };
146
147 &combphy2 {
148 status = "okay";
149 };
150
151 &cpu0 {
152 cpu-supply = <&vdd_cpu>;
153 };
154
155 &cpu1 {
156 cpu-supply = <&vdd_cpu>;
157 };
158
159 &cpu2 {
160 cpu-supply = <&vdd_cpu>;
161 };
162
163 &cpu3 {
164 cpu-supply = <&vdd_cpu>;
165 };
166
167 &gpu {
168 mali-supply = <&vdd_gpu>;
169 status = "okay";
170 };
171
172 &hdmi {
173 avdd-0v9-supply = <&vdda0v9_image>;
174 avdd-1v8-supply = <&vcca1v8_image>;
175 status = "okay";
176 };
177
178 &hdmi_in {
179 hdmi_in_vp0: endpoint {
180 remote-endpoint = <&vp0_out_hd
181 };
182 };
183
184 &hdmi_out {
185 hdmi_out_con: endpoint {
186 remote-endpoint = <&hdmi_con_i
187 };
188 };
189
190 &hdmi_sound {
191 status = "okay";
192 };
193
194 &i2c0 {
195 status = "okay";
196
197 vdd_cpu: regulator@1c {
198 compatible = "tcs,tcs4525";
199 reg = <0x1c>;
200 fcs,suspend-voltage-selector =
201 regulator-name = "vdd_cpu";
202 regulator-always-on;
203 regulator-boot-on;
204 regulator-min-microvolt = <800
205 regulator-max-microvolt = <115
206 regulator-ramp-delay = <2300>;
207 vin-supply = <&vcc5v0_sys>;
208
209 regulator-state-mem {
210 regulator-off-in-suspe
211 };
212 };
213
214 rk809: pmic@20 {
215 compatible = "rockchip,rk809";
216 reg = <0x20>;
217 interrupt-parent = <&gpio0>;
218 interrupts = <RK_PA3 IRQ_TYPE_
219 assigned-clocks = <&cru I2S1_M
220 assigned-clock-parents = <&cru
221 #clock-cells = <1>;
222 clock-names = "mclk";
223 clocks = <&cru I2S1_MCLKOUT_TX
224 pinctrl-names = "default";
225 pinctrl-0 = <&pmic_int>;
226 rockchip,system-power-controll
227 #sound-dai-cells = <0>;
228 vcc1-supply = <&vcc3v3_sys>;
229 vcc2-supply = <&vcc3v3_sys>;
230 vcc3-supply = <&vcc3v3_sys>;
231 vcc4-supply = <&vcc3v3_sys>;
232 vcc5-supply = <&vcc3v3_sys>;
233 vcc6-supply = <&vcc3v3_sys>;
234 vcc7-supply = <&vcc3v3_sys>;
235 vcc8-supply = <&vcc3v3_sys>;
236 vcc9-supply = <&vcc3v3_sys>;
237 wakeup-source;
238
239 regulators {
240 vdd_logic: DCDC_REG1 {
241 regulator-name
242 regulator-alwa
243 regulator-boot
244 regulator-min-
245 regulator-max-
246 regulator-ramp
247 regulator-init
248
249 regulator-stat
250 regula
251 };
252 };
253
254 vdd_gpu: DCDC_REG2 {
255 regulator-name
256 regulator-alwa
257 regulator-boot
258 regulator-min-
259 regulator-max-
260 regulator-ramp
261 regulator-init
262
263 regulator-stat
264 regula
265 };
266 };
267
268 vcc_ddr: DCDC_REG3 {
269 regulator-name
270 regulator-alwa
271 regulator-boot
272 regulator-init
273
274 regulator-stat
275 regula
276 };
277 };
278
279 vdd_npu: DCDC_REG4 {
280 regulator-name
281 regulator-alwa
282 regulator-boot
283 regulator-min-
284 regulator-max-
285 regulator-ramp
286 regulator-init
287
288 regulator-stat
289 regula
290 };
291 };
292
293 vcc_1v8: DCDC_REG5 {
294 regulator-name
295 regulator-alwa
296 regulator-boot
297 regulator-min-
298 regulator-max-
299
300 regulator-stat
301 regula
302 };
303 };
304
305 vdda0v9_image: LDO_REG
306 regulator-name
307 regulator-boot
308 regulator-alwa
309 regulator-min-
310 regulator-max-
311
312 regulator-stat
313 regula
314 };
315 };
316
317 vdda_0v9: LDO_REG2 {
318 regulator-name
319 regulator-alwa
320 regulator-boot
321 regulator-min-
322 regulator-max-
323
324 regulator-stat
325 regula
326 };
327 };
328
329 vdda0v9_pmu: LDO_REG3
330 regulator-name
331 regulator-alwa
332 regulator-boot
333 regulator-min-
334 regulator-max-
335
336 regulator-stat
337 regula
338 regula
339 };
340 };
341
342 vccio_acodec: LDO_REG4
343 regulator-name
344 regulator-alwa
345 regulator-boot
346 regulator-min-
347 regulator-max-
348
349 regulator-stat
350 regula
351 };
352 };
353
354 vccio_sd: LDO_REG5 {
355 regulator-name
356 regulator-alwa
357 regulator-boot
358 regulator-min-
359 regulator-max-
360
361 regulator-stat
362 regula
363 };
364 };
365
366 vcc3v3_pmu: LDO_REG6 {
367 regulator-name
368 regulator-alwa
369 regulator-boot
370 regulator-min-
371 regulator-max-
372
373 regulator-stat
374 regula
375 regula
376 };
377 };
378
379 vcca_1v8: LDO_REG7 {
380 regulator-name
381 regulator-alwa
382 regulator-boot
383 regulator-min-
384 regulator-max-
385
386 regulator-stat
387 regula
388 };
389 };
390
391 vcca1v8_pmu: LDO_REG8
392 regulator-name
393 regulator-alwa
394 regulator-boot
395 regulator-min-
396 regulator-max-
397
398 regulator-stat
399 regula
400 regula
401 };
402 };
403
404 vcca1v8_image: LDO_REG
405 regulator-name
406 regulator-alwa
407 regulator-boot
408 regulator-min-
409 regulator-max-
410
411 regulator-stat
412 regula
413 };
414 };
415
416 vcc_3v3: SWITCH_REG1 {
417 regulator-name
418 regulator-alwa
419 regulator-boot
420
421 regulator-stat
422 regula
423 };
424 };
425
426 vcc3v3_sd: SWITCH_REG2
427 regulator-name
428 regulator-alwa
429 regulator-boot
430
431 regulator-stat
432 regula
433 };
434 };
435 };
436 };
437 };
438
439 &i2s1_8ch {
440 rockchip,trcm-sync-tx-only;
441 status = "okay";
442 };
443
444 &gmac0 {
445 phy-mode = "rgmii";
446 clock_in_out = "output";
447
448 snps,reset-gpio = <&gpio2 RK_PD3 GPIO_
449 snps,reset-active-low;
450 /* Reset time is 20ms, 100ms for rtl82
451 snps,reset-delays-us = <0 20000 100000
452
453 assigned-clocks = <&cru SCLK_GMAC0_RX_
454 assigned-clock-parents = <&cru SCLK_GM
455
456 pinctrl-names = "default";
457 pinctrl-0 = <&gmac0_miim
458 &gmac0_tx_bus2
459 &gmac0_rx_bus2
460 &gmac0_rgmii_clk
461 &gmac0_rgmii_bus>;
462
463 tx_delay = <0x22>;
464 rx_delay = <0x0e>;
465
466 phy-handle = <&rgmii_phy0>;
467 status = "okay";
468 };
469
470 &mdio0 {
471 rgmii_phy0: phy@0 {
472 compatible = "ethernet-phy-iee
473 reg = <0x0>;
474 };
475 };
476
477 &gmac1 {
478 phy-mode = "rgmii";
479 clock_in_out = "output";
480
481 snps,reset-gpio = <&gpio3 RK_PA2 GPIO_
482 snps,reset-active-low;
483 /* Reset time is 20ms, 100ms for rtl82
484 snps,reset-delays-us = <0 20000 100000
485
486 assigned-clocks = <&cru SCLK_GMAC1_RX_
487 assigned-clock-parents = <&cru SCLK_GM
488
489 pinctrl-names = "default";
490 pinctrl-0 = <&gmac1m1_miim
491 &gmac1m1_tx_bus2
492 &gmac1m1_rx_bus2
493 &gmac1m1_rgmii_clk
494 &gmac1m1_rgmii_bus>;
495
496 tx_delay = <0x21>;
497 rx_delay = <0x0e>;
498
499 phy-handle = <&rgmii_phy1>;
500 status = "okay";
501 };
502
503 &mdio1 {
504 rgmii_phy1: phy@0 {
505 compatible = "ethernet-phy-iee
506 reg = <0x0>;
507 };
508 };
509
510 &gic {
511 mbi-ranges = <94 31>, <229 31>, <289 3
512 };
513
514 &pcie30phy {
515 status = "okay";
516 };
517
518 &pcie3x2 {
519 reset-gpios = <&gpio2 RK_PD6 GPIO_ACTI
520 vpcie3v3-supply = <&vcc3v3_m2_pcie>;
521 status = "okay";
522 };
523
524 &pcie2x1 {
525 reset-gpios = <&gpio3 RK_PC1 GPIO_ACTI
526 vpcie3v3-supply = <&vcc3v3_mini_pcie>;
527 status = "okay";
528 };
529
530 &pmu_io_domains {
531 pmuio2-supply = <&vcc3v3_pmu>;
532 vccio1-supply = <&vccio_acodec>;
533 vccio3-supply = <&vccio_sd>;
534 vccio4-supply = <&vcc_1v8>;
535 vccio5-supply = <&vcc_3v3>;
536 vccio6-supply = <&vcc_1v8>;
537 vccio7-supply = <&vcc_3v3>;
538 status = "okay";
539 };
540
541 &pwm8 {
542 status = "okay";
543 };
544
545 &pwm9 {
546 status = "disabled";
547 };
548
549 &pwm10 {
550 status = "disabled";
551 };
552
553 &pwm14 {
554 status = "disabled";
555 };
556
557 &spi3 {
558 pinctrl-0 = <&spi3m1_pins>;
559 status = "disabled";
560 };
561
562 &uart2 {
563 status = "okay";
564 };
565
566 &uart3 {
567 pinctrl-names = "default";
568 pinctrl-0 = <&uart3m1_xfer>;
569 status = "disabled";
570 };
571
572 &saradc {
573 vref-supply = <&vcca_1v8>;
574 status = "okay";
575 };
576
577 &tsadc {
578 rockchip,hw-tshut-mode = <1>;
579 rockchip,hw-tshut-polarity = <0>;
580 status = "okay";
581 };
582
583 &sdhci {
584 assigned-clocks = <&cru BCLK_EMMC>, <&
585 assigned-clock-rates = <200000000>, <2
586 bus-width = <8>;
587 max-frequency = <200000000>;
588 mmc-hs200-1_8v;
589 non-removable;
590 pinctrl-names = "default";
591 pinctrl-0 = <&emmc_bus8 &emmc_clk &emm
592 status = "okay";
593 };
594
595 &sdmmc0 {
596 max-frequency = <150000000>;
597 no-sdio;
598 no-mmc;
599 bus-width = <4>;
600 cap-mmc-highspeed;
601 cap-sd-highspeed;
602 disable-wp;
603 sd-uhs-sdr104;
604 vmmc-supply = <&vcc3v3_sd>;
605 vqmmc-supply = <&vccio_sd>;
606 pinctrl-names = "default";
607 pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk
608 status = "okay";
609 };
610
611 /* USB OTG/USB Host_1 USB 2.0 Comb */
612 &usb2phy0 {
613 status = "okay";
614 };
615
616 &usb2phy0_host {
617 phy-supply = <&vcc5v0_usb30_host>;
618 status = "okay";
619 };
620
621 &usb2phy0_otg {
622 phy-supply = <&vcc5v0_otg_vbus>;
623 status = "okay";
624 };
625
626 &usb_host0_ehci {
627 status = "okay";
628 };
629
630 &usb_host0_ohci {
631 status = "okay";
632 };
633
634 /* USB Host_2/USB Host_3 USB 2.0 Comb */
635 &usb2phy1 {
636 status = "okay";
637 };
638
639 &usb2phy1_host {
640 status = "okay";
641 };
642
643 &usb2phy1_otg {
644 phy-supply = <&vcc5v0_usb20_host>;
645 status = "okay";
646 };
647
648 &usb_host1_ehci {
649 status = "okay";
650 };
651
652 &usb_host1_ohci {
653 status = "okay";
654 };
655
656 /* MULTI_PHY0 For SATA0, USB3.0 OTG Only USB2.
657 &usb_host0_xhci {
658 phys = <&usb2phy0_otg>;
659 phy-names = "usb2-phy";
660 extcon = <&usb2phy0>;
661 maximum-speed = "high-speed";
662 dr_mode = "host";
663 status = "okay";
664 };
665
666 &sata0 {
667 status = "okay";
668 };
669
670 /* USB3.0 Host */
671 &usb_host1_xhci {
672 status = "okay";
673 };
674
675 &vop {
676 assigned-clocks = <&cru DCLK_VOP0>, <&
677 assigned-clock-parents = <&pmucru PLL_
678 status = "okay";
679 };
680
681 &vop_mmu {
682 status = "okay";
683 };
684
685 &vp0 {
686 vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_E
687 reg = <ROCKCHIP_VOP2_EP_HDMI0>
688 remote-endpoint = <&hdmi_in_vp
689 };
690 };
691
692 &pinctrl {
693 leds {
694 user_led_pin: user-status-led-
695 rockchip,pins = <0 RK_
696 };
697 };
698
699 usb {
700 vcc5v0_usb20_host_en: vcc5v0-u
701 rockchip,pins = <0 RK_
702 };
703
704 vcc5v0_usb30_host_en: vcc5v0-u
705 rockchip,pins = <0 RK_
706 };
707
708 vcc5v0_otg_vbus_en: vcc5v0-otg
709 rockchip,pins = <0 RK_
710 };
711 };
712
713 pcie {
714 vcc3v3_m2_pcie_en: vcc3v3-m2-p
715 rockchip,pins = <0 RK_
716 };
717
718 vcc3v3_mini_pcie_en: vcc3v3-mi
719 rockchip,pins = <3 RK_
720 };
721 };
722
723 pmic {
724 pmic_int: pmic-int {
725 rockchip,pins = <0 RK_
726 };
727 };
728 };
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