1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /*
3 * Copyright (c) 2021 Rockchip Electronics Co.
4 */
5
6 #include "rk356x.dtsi"
7
8 / {
9 compatible = "rockchip,rk3568";
10
11 sata0: sata@fc000000 {
12 compatible = "rockchip,rk3568-
13 reg = <0 0xfc000000 0 0x1000>;
14 clocks = <&cru ACLK_SATA0>, <&
15 <&cru CLK_SATA0_RXOOB
16 clock-names = "sata", "pmalive
17 interrupts = <GIC_SPI 94 IRQ_T
18 phys = <&combphy0 PHY_TYPE_SAT
19 phy-names = "sata-phy";
20 ports-implemented = <0x1>;
21 power-domains = <&power RK3568
22 status = "disabled";
23 };
24
25 pipe_phy_grf0: syscon@fdc70000 {
26 compatible = "rockchip,rk3568-
27 reg = <0x0 0xfdc70000 0x0 0x10
28 };
29
30 qos_pcie3x1: qos@fe190080 {
31 compatible = "rockchip,rk3568-
32 reg = <0x0 0xfe190080 0x0 0x20
33 };
34
35 qos_pcie3x2: qos@fe190100 {
36 compatible = "rockchip,rk3568-
37 reg = <0x0 0xfe190100 0x0 0x20
38 };
39
40 qos_sata0: qos@fe190200 {
41 compatible = "rockchip,rk3568-
42 reg = <0x0 0xfe190200 0x0 0x20
43 };
44
45 pcie30_phy_grf: syscon@fdcb8000 {
46 compatible = "rockchip,rk3568-
47 reg = <0x0 0xfdcb8000 0x0 0x10
48 };
49
50 pcie30phy: phy@fe8c0000 {
51 compatible = "rockchip,rk3568-
52 reg = <0x0 0xfe8c0000 0x0 0x20
53 #phy-cells = <0>;
54 clocks = <&pmucru CLK_PCIE30PH
55 <&cru PCLK_PCIE30PHY>
56 clock-names = "refclk_m", "ref
57 resets = <&cru SRST_PCIE30PHY>
58 reset-names = "phy";
59 rockchip,phy-grf = <&pcie30_ph
60 status = "disabled";
61 };
62
63 pcie3x1: pcie@fe270000 {
64 compatible = "rockchip,rk3568-
65 #address-cells = <3>;
66 #size-cells = <2>;
67 bus-range = <0x0 0xf>;
68 clocks = <&cru ACLK_PCIE30X1_M
69 <&cru ACLK_PCIE30X1_D
70 <&cru CLK_PCIE30X1_AU
71 clock-names = "aclk_mst", "acl
72 "aclk_dbi", "pcl
73 device_type = "pci";
74 interrupts = <GIC_SPI 160 IRQ_
75 <GIC_SPI 159 IRQ_
76 <GIC_SPI 158 IRQ_
77 <GIC_SPI 157 IRQ_
78 <GIC_SPI 156 IRQ_
79 interrupt-names = "sys", "pmc"
80 #interrupt-cells = <1>;
81 interrupt-map-mask = <0 0 0 7>
82 interrupt-map = <0 0 0 1 &pcie
83 <0 0 0 2 &pcie
84 <0 0 0 3 &pcie
85 <0 0 0 4 &pcie
86 linux,pci-domain = <1>;
87 num-ib-windows = <6>;
88 num-ob-windows = <2>;
89 max-link-speed = <3>;
90 msi-map = <0x0 &gic 0x1000 0x1
91 num-lanes = <1>;
92 phys = <&pcie30phy>;
93 phy-names = "pcie-phy";
94 power-domains = <&power RK3568
95 reg = <0x3 0xc0400000 0x0 0x00
96 <0x0 0xfe270000 0x0 0x00
97 <0x0 0xf2000000 0x0 0x00
98 ranges = <0x01000000 0x0 0xf21
99 <0x02000000 0x0 0xf22
100 <0x03000000 0x0 0x400
101 reg-names = "dbi", "apb", "con
102 resets = <&cru SRST_PCIE30X1_P
103 reset-names = "pipe";
104 /* bifurcation; lane1 when usi
105 status = "disabled";
106
107 pcie3x1_intc: legacy-interrupt
108 interrupt-controller;
109 #address-cells = <0>;
110 #interrupt-cells = <1>
111 interrupt-parent = <&g
112 interrupts = <GIC_SPI
113 };
114 };
115
116 pcie3x2: pcie@fe280000 {
117 compatible = "rockchip,rk3568-
118 #address-cells = <3>;
119 #size-cells = <2>;
120 bus-range = <0x0 0xf>;
121 clocks = <&cru ACLK_PCIE30X2_M
122 <&cru ACLK_PCIE30X2_D
123 <&cru CLK_PCIE30X2_AU
124 clock-names = "aclk_mst", "acl
125 "aclk_dbi", "pcl
126 device_type = "pci";
127 interrupts = <GIC_SPI 165 IRQ_
128 <GIC_SPI 164 IRQ_
129 <GIC_SPI 163 IRQ_
130 <GIC_SPI 162 IRQ_
131 <GIC_SPI 161 IRQ_
132 interrupt-names = "sys", "pmc"
133 #interrupt-cells = <1>;
134 interrupt-map-mask = <0 0 0 7>
135 interrupt-map = <0 0 0 1 &pcie
136 <0 0 0 2 &pcie
137 <0 0 0 3 &pcie
138 <0 0 0 4 &pcie
139 linux,pci-domain = <2>;
140 num-ib-windows = <6>;
141 num-ob-windows = <2>;
142 max-link-speed = <3>;
143 msi-map = <0x0 &gic 0x2000 0x1
144 num-lanes = <2>;
145 phys = <&pcie30phy>;
146 phy-names = "pcie-phy";
147 power-domains = <&power RK3568
148 reg = <0x3 0xc0800000 0x0 0x00
149 <0x0 0xfe280000 0x0 0x00
150 <0x0 0xf0000000 0x0 0x00
151 ranges = <0x01000000 0x0 0xf01
152 <0x02000000 0x0 0xf02
153 <0x03000000 0x0 0x400
154 reg-names = "dbi", "apb", "con
155 resets = <&cru SRST_PCIE30X2_P
156 reset-names = "pipe";
157 /* bifurcation; lane0 when usi
158 status = "disabled";
159
160 pcie3x2_intc: legacy-interrupt
161 interrupt-controller;
162 #address-cells = <0>;
163 #interrupt-cells = <1>
164 interrupt-parent = <&g
165 interrupts = <GIC_SPI
166 };
167 };
168
169 gmac0: ethernet@fe2a0000 {
170 compatible = "rockchip,rk3568-
171 reg = <0x0 0xfe2a0000 0x0 0x10
172 interrupts = <GIC_SPI 27 IRQ_T
173 <GIC_SPI 24 IRQ_T
174 interrupt-names = "macirq", "e
175 clocks = <&cru SCLK_GMAC0>, <&
176 <&cru SCLK_GMAC0_RX_T
177 <&cru ACLK_GMAC0>, <&
178 <&cru SCLK_GMAC0_RX_T
179 clock-names = "stmmaceth", "ma
180 "mac_clk_tx", "c
181 "aclk_mac", "pcl
182 "clk_mac_speed",
183 resets = <&cru SRST_A_GMAC0>;
184 reset-names = "stmmaceth";
185 rockchip,grf = <&grf>;
186 snps,axi-config = <&gmac0_stmm
187 snps,mixed-burst;
188 snps,mtl-rx-config = <&gmac0_m
189 snps,mtl-tx-config = <&gmac0_m
190 snps,tso;
191 status = "disabled";
192
193 mdio0: mdio {
194 compatible = "snps,dwm
195 #address-cells = <0x1>
196 #size-cells = <0x0>;
197 };
198
199 gmac0_stmmac_axi_setup: stmmac
200 snps,blen = <0 0 0 0 1
201 snps,rd_osr_lmt = <8>;
202 snps,wr_osr_lmt = <4>;
203 };
204
205 gmac0_mtl_rx_setup: rx-queues-
206 snps,rx-queues-to-use
207 queue0 {};
208 };
209
210 gmac0_mtl_tx_setup: tx-queues-
211 snps,tx-queues-to-use
212 queue0 {};
213 };
214 };
215
216 can0: can@fe570000 {
217 compatible = "rockchip,rk3568v
218 reg = <0x0 0xfe570000 0x0 0x10
219 interrupts = <GIC_SPI 1 IRQ_TY
220 clocks = <&cru CLK_CAN0>, <&cr
221 clock-names = "baud", "pclk";
222 resets = <&cru SRST_CAN0>, <&c
223 reset-names = "core", "apb";
224 pinctrl-names = "default";
225 pinctrl-0 = <&can0m0_pins>;
226 status = "disabled";
227 };
228
229 can1: can@fe580000 {
230 compatible = "rockchip,rk3568v
231 reg = <0x0 0xfe580000 0x0 0x10
232 interrupts = <GIC_SPI 2 IRQ_TY
233 clocks = <&cru CLK_CAN1>, <&cr
234 clock-names = "baud", "pclk";
235 resets = <&cru SRST_CAN1>, <&c
236 reset-names = "core", "apb";
237 pinctrl-names = "default";
238 pinctrl-0 = <&can1m0_pins>;
239 status = "disabled";
240 };
241
242 can2: can@fe590000 {
243 compatible = "rockchip,rk3568v
244 reg = <0x0 0xfe590000 0x0 0x10
245 interrupts = <GIC_SPI 3 IRQ_TY
246 clocks = <&cru CLK_CAN2>, <&cr
247 clock-names = "baud", "pclk";
248 resets = <&cru SRST_CAN2>, <&c
249 reset-names = "core", "apb";
250 pinctrl-names = "default";
251 pinctrl-0 = <&can2m0_pins>;
252 status = "disabled";
253 };
254
255 combphy0: phy@fe820000 {
256 compatible = "rockchip,rk3568-
257 reg = <0x0 0xfe820000 0x0 0x10
258 clocks = <&pmucru CLK_PCIEPHY0
259 <&cru PCLK_PIPEPHY0>,
260 <&cru PCLK_PIPE>;
261 clock-names = "ref", "apb", "p
262 assigned-clocks = <&pmucru CLK
263 assigned-clock-rates = <100000
264 resets = <&cru SRST_PIPEPHY0>;
265 rockchip,pipe-grf = <&pipegrf>
266 rockchip,pipe-phy-grf = <&pipe
267 #phy-cells = <1>;
268 status = "disabled";
269 };
270 };
271
272 &cpu0_opp_table {
273 opp-1992000000 {
274 opp-hz = /bits/ 64 <1992000000
275 opp-microvolt = <1150000 11500
276 };
277 };
278
279 &pipegrf {
280 compatible = "rockchip,rk3568-pipe-grf
281 };
282
283 &power {
284 power-domain@RK3568_PD_PIPE {
285 reg = <RK3568_PD_PIPE>;
286 clocks = <&cru PCLK_PIPE>;
287 pm_qos = <&qos_pcie2x1>,
288 <&qos_pcie3x1>,
289 <&qos_pcie3x2>,
290 <&qos_sata0>,
291 <&qos_sata1>,
292 <&qos_sata2>,
293 <&qos_usb3_0>,
294 <&qos_usb3_1>;
295 #power-domain-cells = <0>;
296 };
297 };
298
299 &rng {
300 status = "okay";
301 };
302
303 &usb_host0_xhci {
304 phys = <&usb2phy0_otg>, <&combphy0 PHY
305 phy-names = "usb2-phy", "usb3-phy";
306 };
307
308 &vop {
309 compatible = "rockchip,rk3568-vop";
310 };
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