1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /* 2 /*
3 * Copyright (c) 2021 Rockchip Electronics Co. 3 * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
4 */ 4 */
5 5
6 #include "rk356x.dtsi" !! 6 #include <dt-bindings/clock/rk3568-cru.h>
>> 7 #include <dt-bindings/interrupt-controller/arm-gic.h>
>> 8 #include <dt-bindings/interrupt-controller/irq.h>
>> 9 #include <dt-bindings/phy/phy.h>
>> 10 #include <dt-bindings/pinctrl/rockchip.h>
>> 11 #include <dt-bindings/soc/rockchip,boot-mode.h>
>> 12 #include <dt-bindings/thermal/thermal.h>
7 13
8 / { 14 / {
9 compatible = "rockchip,rk3568"; 15 compatible = "rockchip,rk3568";
10 16
11 sata0: sata@fc000000 { !! 17 interrupt-parent = <&gic>;
12 compatible = "rockchip,rk3568- !! 18 #address-cells = <2>;
13 reg = <0 0xfc000000 0 0x1000>; !! 19 #size-cells = <2>;
14 clocks = <&cru ACLK_SATA0>, <& !! 20
15 <&cru CLK_SATA0_RXOOB !! 21 aliases {
16 clock-names = "sata", "pmalive !! 22 gpio0 = &gpio0;
17 interrupts = <GIC_SPI 94 IRQ_T !! 23 gpio1 = &gpio1;
18 phys = <&combphy0 PHY_TYPE_SAT !! 24 gpio2 = &gpio2;
19 phy-names = "sata-phy"; !! 25 gpio3 = &gpio3;
20 ports-implemented = <0x1>; !! 26 gpio4 = &gpio4;
21 power-domains = <&power RK3568 !! 27 i2c0 = &i2c0;
22 status = "disabled"; !! 28 i2c1 = &i2c1;
>> 29 i2c2 = &i2c2;
>> 30 i2c3 = &i2c3;
>> 31 i2c4 = &i2c4;
>> 32 i2c5 = &i2c5;
>> 33 serial0 = &uart0;
>> 34 serial1 = &uart1;
>> 35 serial2 = &uart2;
>> 36 serial3 = &uart3;
>> 37 serial4 = &uart4;
>> 38 serial5 = &uart5;
>> 39 serial6 = &uart6;
>> 40 serial7 = &uart7;
>> 41 serial8 = &uart8;
>> 42 serial9 = &uart9;
>> 43 };
>> 44
>> 45 cpus {
>> 46 #address-cells = <2>;
>> 47 #size-cells = <0>;
>> 48
>> 49 cpu0: cpu@0 {
>> 50 device_type = "cpu";
>> 51 compatible = "arm,cortex-a55";
>> 52 reg = <0x0 0x0>;
>> 53 clocks = <&scmi_clk 0>;
>> 54 enable-method = "psci";
>> 55 operating-points-v2 = <&cpu0_opp_table>;
>> 56 };
>> 57
>> 58 cpu1: cpu@100 {
>> 59 device_type = "cpu";
>> 60 compatible = "arm,cortex-a55";
>> 61 reg = <0x0 0x100>;
>> 62 enable-method = "psci";
>> 63 operating-points-v2 = <&cpu0_opp_table>;
>> 64 };
>> 65
>> 66 cpu2: cpu@200 {
>> 67 device_type = "cpu";
>> 68 compatible = "arm,cortex-a55";
>> 69 reg = <0x0 0x200>;
>> 70 enable-method = "psci";
>> 71 operating-points-v2 = <&cpu0_opp_table>;
>> 72 };
>> 73
>> 74 cpu3: cpu@300 {
>> 75 device_type = "cpu";
>> 76 compatible = "arm,cortex-a55";
>> 77 reg = <0x0 0x300>;
>> 78 enable-method = "psci";
>> 79 operating-points-v2 = <&cpu0_opp_table>;
>> 80 };
23 }; 81 };
24 82
25 pipe_phy_grf0: syscon@fdc70000 { !! 83 cpu0_opp_table: cpu0-opp-table {
26 compatible = "rockchip,rk3568- !! 84 compatible = "operating-points-v2";
27 reg = <0x0 0xfdc70000 0x0 0x10 !! 85 opp-shared;
>> 86
>> 87 opp-408000000 {
>> 88 opp-hz = /bits/ 64 <408000000>;
>> 89 opp-microvolt = <900000 900000 1150000>;
>> 90 clock-latency-ns = <40000>;
>> 91 };
>> 92
>> 93 opp-600000000 {
>> 94 opp-hz = /bits/ 64 <600000000>;
>> 95 opp-microvolt = <900000 900000 1150000>;
>> 96 };
>> 97
>> 98 opp-816000000 {
>> 99 opp-hz = /bits/ 64 <816000000>;
>> 100 opp-microvolt = <900000 900000 1150000>;
>> 101 opp-suspend;
>> 102 };
>> 103
>> 104 opp-1104000000 {
>> 105 opp-hz = /bits/ 64 <1104000000>;
>> 106 opp-microvolt = <900000 900000 1150000>;
>> 107 };
>> 108
>> 109 opp-1416000000 {
>> 110 opp-hz = /bits/ 64 <1416000000>;
>> 111 opp-microvolt = <900000 900000 1150000>;
>> 112 };
>> 113
>> 114 opp-1608000000 {
>> 115 opp-hz = /bits/ 64 <1608000000>;
>> 116 opp-microvolt = <975000 975000 1150000>;
>> 117 };
>> 118
>> 119 opp-1800000000 {
>> 120 opp-hz = /bits/ 64 <1800000000>;
>> 121 opp-microvolt = <1050000 1050000 1150000>;
>> 122 };
>> 123
>> 124 opp-1992000000 {
>> 125 opp-hz = /bits/ 64 <1992000000>;
>> 126 opp-microvolt = <1150000 1150000 1150000>;
>> 127 };
28 }; 128 };
29 129
30 qos_pcie3x1: qos@fe190080 { !! 130 firmware {
31 compatible = "rockchip,rk3568- !! 131 scmi: scmi {
32 reg = <0x0 0xfe190080 0x0 0x20 !! 132 compatible = "arm,scmi-smc";
>> 133 arm,smc-id = <0x82000010>;
>> 134 shmem = <&scmi_shmem>;
>> 135 #address-cells = <1>;
>> 136 #size-cells = <0>;
>> 137
>> 138 scmi_clk: protocol@14 {
>> 139 reg = <0x14>;
>> 140 #clock-cells = <1>;
>> 141 };
>> 142 };
33 }; 143 };
34 144
35 qos_pcie3x2: qos@fe190100 { !! 145 pmu {
36 compatible = "rockchip,rk3568- !! 146 compatible = "arm,cortex-a55-pmu";
37 reg = <0x0 0xfe190100 0x0 0x20 !! 147 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>,
>> 148 <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
>> 149 <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>,
>> 150 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>;
>> 151 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
>> 152 };
>> 153
>> 154 psci {
>> 155 compatible = "arm,psci-1.0";
>> 156 method = "smc";
>> 157 };
>> 158
>> 159 timer {
>> 160 compatible = "arm,armv8-timer";
>> 161 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>,
>> 162 <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>,
>> 163 <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>,
>> 164 <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>;
>> 165 arm,no-tick-in-suspend;
>> 166 };
>> 167
>> 168 xin24m: xin24m {
>> 169 compatible = "fixed-clock";
>> 170 clock-frequency = <24000000>;
>> 171 clock-output-names = "xin24m";
>> 172 #clock-cells = <0>;
>> 173 };
>> 174
>> 175 xin32k: xin32k {
>> 176 compatible = "fixed-clock";
>> 177 clock-frequency = <32768>;
>> 178 clock-output-names = "xin32k";
>> 179 pinctrl-0 = <&clk32k_out0>;
>> 180 pinctrl-names = "default";
>> 181 #clock-cells = <0>;
38 }; 182 };
39 183
40 qos_sata0: qos@fe190200 { !! 184 sram@10f000 {
41 compatible = "rockchip,rk3568- !! 185 compatible = "mmio-sram";
42 reg = <0x0 0xfe190200 0x0 0x20 !! 186 reg = <0x0 0x0010f000 0x0 0x100>;
>> 187 #address-cells = <1>;
>> 188 #size-cells = <1>;
>> 189 ranges = <0 0x0 0x0010f000 0x100>;
>> 190
>> 191 scmi_shmem: sram@0 {
>> 192 compatible = "arm,scmi-shmem";
>> 193 reg = <0x0 0x100>;
>> 194 };
43 }; 195 };
44 196
45 pcie30_phy_grf: syscon@fdcb8000 { !! 197 gic: interrupt-controller@fd400000 {
46 compatible = "rockchip,rk3568- !! 198 compatible = "arm,gic-v3";
47 reg = <0x0 0xfdcb8000 0x0 0x10 !! 199 reg = <0x0 0xfd400000 0 0x10000>, /* GICD */
>> 200 <0x0 0xfd460000 0 0x80000>; /* GICR */
>> 201 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
>> 202 interrupt-controller;
>> 203 #interrupt-cells = <3>;
>> 204 mbi-alias = <0x0 0xfd100000>;
>> 205 mbi-ranges = <296 24>;
>> 206 msi-controller;
>> 207 };
>> 208
>> 209 pmugrf: syscon@fdc20000 {
>> 210 compatible = "rockchip,rk3568-pmugrf", "syscon", "simple-mfd";
>> 211 reg = <0x0 0xfdc20000 0x0 0x10000>;
>> 212 };
>> 213
>> 214 grf: syscon@fdc60000 {
>> 215 compatible = "rockchip,rk3568-grf", "syscon", "simple-mfd";
>> 216 reg = <0x0 0xfdc60000 0x0 0x10000>;
>> 217 };
>> 218
>> 219 pmucru: clock-controller@fdd00000 {
>> 220 compatible = "rockchip,rk3568-pmucru";
>> 221 reg = <0x0 0xfdd00000 0x0 0x1000>;
>> 222 #clock-cells = <1>;
>> 223 #reset-cells = <1>;
>> 224 };
>> 225
>> 226 cru: clock-controller@fdd20000 {
>> 227 compatible = "rockchip,rk3568-cru";
>> 228 reg = <0x0 0xfdd20000 0x0 0x1000>;
>> 229 #clock-cells = <1>;
>> 230 #reset-cells = <1>;
>> 231 };
>> 232
>> 233 i2c0: i2c@fdd40000 {
>> 234 compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c";
>> 235 reg = <0x0 0xfdd40000 0x0 0x1000>;
>> 236 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
>> 237 clocks = <&pmucru CLK_I2C0>, <&pmucru PCLK_I2C0>;
>> 238 clock-names = "i2c", "pclk";
>> 239 pinctrl-0 = <&i2c0_xfer>;
>> 240 pinctrl-names = "default";
>> 241 #address-cells = <1>;
>> 242 #size-cells = <0>;
>> 243 status = "disabled";
48 }; 244 };
49 245
50 pcie30phy: phy@fe8c0000 { !! 246 uart0: serial@fdd50000 {
51 compatible = "rockchip,rk3568- !! 247 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
52 reg = <0x0 0xfe8c0000 0x0 0x20 !! 248 reg = <0x0 0xfdd50000 0x0 0x100>;
53 #phy-cells = <0>; !! 249 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
54 clocks = <&pmucru CLK_PCIE30PH !! 250 clocks = <&pmucru SCLK_UART0>, <&pmucru PCLK_UART0>;
55 <&cru PCLK_PCIE30PHY> !! 251 clock-names = "baudclk", "apb_pclk";
56 clock-names = "refclk_m", "ref !! 252 dmas = <&dmac0 0>, <&dmac0 1>;
57 resets = <&cru SRST_PCIE30PHY> !! 253 pinctrl-0 = <&uart0_xfer>;
58 reset-names = "phy"; !! 254 pinctrl-names = "default";
59 rockchip,phy-grf = <&pcie30_ph !! 255 reg-io-width = <4>;
>> 256 reg-shift = <2>;
60 status = "disabled"; 257 status = "disabled";
61 }; 258 };
62 259
63 pcie3x1: pcie@fe270000 { !! 260 sdmmc2: mmc@fe000000 {
64 compatible = "rockchip,rk3568- !! 261 compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc";
65 #address-cells = <3>; !! 262 reg = <0x0 0xfe000000 0x0 0x4000>;
66 #size-cells = <2>; !! 263 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
67 bus-range = <0x0 0xf>; !! 264 clocks = <&cru HCLK_SDMMC2>, <&cru CLK_SDMMC2>,
68 clocks = <&cru ACLK_PCIE30X1_M !! 265 <&cru SCLK_SDMMC2_DRV>, <&cru SCLK_SDMMC2_SAMPLE>;
69 <&cru ACLK_PCIE30X1_D !! 266 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
70 <&cru CLK_PCIE30X1_AU !! 267 fifo-depth = <0x100>;
71 clock-names = "aclk_mst", "acl !! 268 max-frequency = <150000000>;
72 "aclk_dbi", "pcl !! 269 resets = <&cru SRST_SDMMC2>;
73 device_type = "pci"; !! 270 reset-names = "reset";
74 interrupts = <GIC_SPI 160 IRQ_ <<
75 <GIC_SPI 159 IRQ_ <<
76 <GIC_SPI 158 IRQ_ <<
77 <GIC_SPI 157 IRQ_ <<
78 <GIC_SPI 156 IRQ_ <<
79 interrupt-names = "sys", "pmc" <<
80 #interrupt-cells = <1>; <<
81 interrupt-map-mask = <0 0 0 7> <<
82 interrupt-map = <0 0 0 1 &pcie <<
83 <0 0 0 2 &pcie <<
84 <0 0 0 3 &pcie <<
85 <0 0 0 4 &pcie <<
86 linux,pci-domain = <1>; <<
87 num-ib-windows = <6>; <<
88 num-ob-windows = <2>; <<
89 max-link-speed = <3>; <<
90 msi-map = <0x0 &gic 0x1000 0x1 <<
91 num-lanes = <1>; <<
92 phys = <&pcie30phy>; <<
93 phy-names = "pcie-phy"; <<
94 power-domains = <&power RK3568 <<
95 reg = <0x3 0xc0400000 0x0 0x00 <<
96 <0x0 0xfe270000 0x0 0x00 <<
97 <0x0 0xf2000000 0x0 0x00 <<
98 ranges = <0x01000000 0x0 0xf21 <<
99 <0x02000000 0x0 0xf22 <<
100 <0x03000000 0x0 0x400 <<
101 reg-names = "dbi", "apb", "con <<
102 resets = <&cru SRST_PCIE30X1_P <<
103 reset-names = "pipe"; <<
104 /* bifurcation; lane1 when usi <<
105 status = "disabled"; 271 status = "disabled";
>> 272 };
106 273
107 pcie3x1_intc: legacy-interrupt !! 274 sdmmc0: mmc@fe2b0000 {
108 interrupt-controller; !! 275 compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc";
109 #address-cells = <0>; !! 276 reg = <0x0 0xfe2b0000 0x0 0x4000>;
110 #interrupt-cells = <1> !! 277 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
111 interrupt-parent = <&g !! 278 clocks = <&cru HCLK_SDMMC0>, <&cru CLK_SDMMC0>,
112 interrupts = <GIC_SPI !! 279 <&cru SCLK_SDMMC0_DRV>, <&cru SCLK_SDMMC0_SAMPLE>;
113 }; !! 280 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
>> 281 fifo-depth = <0x100>;
>> 282 max-frequency = <150000000>;
>> 283 resets = <&cru SRST_SDMMC0>;
>> 284 reset-names = "reset";
>> 285 status = "disabled";
114 }; 286 };
115 287
116 pcie3x2: pcie@fe280000 { !! 288 sdmmc1: mmc@fe2c0000 {
117 compatible = "rockchip,rk3568- !! 289 compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc";
118 #address-cells = <3>; !! 290 reg = <0x0 0xfe2c0000 0x0 0x4000>;
119 #size-cells = <2>; !! 291 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
120 bus-range = <0x0 0xf>; !! 292 clocks = <&cru HCLK_SDMMC1>, <&cru CLK_SDMMC1>,
121 clocks = <&cru ACLK_PCIE30X2_M !! 293 <&cru SCLK_SDMMC1_DRV>, <&cru SCLK_SDMMC1_SAMPLE>;
122 <&cru ACLK_PCIE30X2_D !! 294 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
123 <&cru CLK_PCIE30X2_AU !! 295 fifo-depth = <0x100>;
124 clock-names = "aclk_mst", "acl !! 296 max-frequency = <150000000>;
125 "aclk_dbi", "pcl !! 297 resets = <&cru SRST_SDMMC1>;
126 device_type = "pci"; !! 298 reset-names = "reset";
127 interrupts = <GIC_SPI 165 IRQ_ <<
128 <GIC_SPI 164 IRQ_ <<
129 <GIC_SPI 163 IRQ_ <<
130 <GIC_SPI 162 IRQ_ <<
131 <GIC_SPI 161 IRQ_ <<
132 interrupt-names = "sys", "pmc" <<
133 #interrupt-cells = <1>; <<
134 interrupt-map-mask = <0 0 0 7> <<
135 interrupt-map = <0 0 0 1 &pcie <<
136 <0 0 0 2 &pcie <<
137 <0 0 0 3 &pcie <<
138 <0 0 0 4 &pcie <<
139 linux,pci-domain = <2>; <<
140 num-ib-windows = <6>; <<
141 num-ob-windows = <2>; <<
142 max-link-speed = <3>; <<
143 msi-map = <0x0 &gic 0x2000 0x1 <<
144 num-lanes = <2>; <<
145 phys = <&pcie30phy>; <<
146 phy-names = "pcie-phy"; <<
147 power-domains = <&power RK3568 <<
148 reg = <0x3 0xc0800000 0x0 0x00 <<
149 <0x0 0xfe280000 0x0 0x00 <<
150 <0x0 0xf0000000 0x0 0x00 <<
151 ranges = <0x01000000 0x0 0xf01 <<
152 <0x02000000 0x0 0xf02 <<
153 <0x03000000 0x0 0x400 <<
154 reg-names = "dbi", "apb", "con <<
155 resets = <&cru SRST_PCIE30X2_P <<
156 reset-names = "pipe"; <<
157 /* bifurcation; lane0 when usi <<
158 status = "disabled"; 299 status = "disabled";
>> 300 };
159 301
160 pcie3x2_intc: legacy-interrupt !! 302 sdhci: mmc@fe310000 {
161 interrupt-controller; !! 303 compatible = "rockchip,rk3568-dwcmshc";
162 #address-cells = <0>; !! 304 reg = <0x0 0xfe310000 0x0 0x10000>;
163 #interrupt-cells = <1> !! 305 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
164 interrupt-parent = <&g !! 306 assigned-clocks = <&cru BCLK_EMMC>, <&cru TCLK_EMMC>;
165 interrupts = <GIC_SPI !! 307 assigned-clock-rates = <200000000>, <24000000>;
166 }; !! 308 clocks = <&cru CCLK_EMMC>, <&cru HCLK_EMMC>,
>> 309 <&cru ACLK_EMMC>, <&cru BCLK_EMMC>,
>> 310 <&cru TCLK_EMMC>;
>> 311 clock-names = "core", "bus", "axi", "block", "timer";
>> 312 status = "disabled";
167 }; 313 };
168 314
169 gmac0: ethernet@fe2a0000 { !! 315 dmac0: dmac@fe530000 {
170 compatible = "rockchip,rk3568- !! 316 compatible = "arm,pl330", "arm,primecell";
171 reg = <0x0 0xfe2a0000 0x0 0x10 !! 317 reg = <0x0 0xfe530000 0x0 0x4000>;
172 interrupts = <GIC_SPI 27 IRQ_T !! 318 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
173 <GIC_SPI 24 IRQ_T !! 319 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
174 interrupt-names = "macirq", "e !! 320 arm,pl330-periph-burst;
175 clocks = <&cru SCLK_GMAC0>, <& !! 321 clocks = <&cru ACLK_BUS>;
176 <&cru SCLK_GMAC0_RX_T !! 322 clock-names = "apb_pclk";
177 <&cru ACLK_GMAC0>, <& !! 323 #dma-cells = <1>;
178 <&cru SCLK_GMAC0_RX_T !! 324 };
179 clock-names = "stmmaceth", "ma !! 325
180 "mac_clk_tx", "c !! 326 dmac1: dmac@fe550000 {
181 "aclk_mac", "pcl !! 327 compatible = "arm,pl330", "arm,primecell";
182 "clk_mac_speed", !! 328 reg = <0x0 0xfe550000 0x0 0x4000>;
183 resets = <&cru SRST_A_GMAC0>; !! 329 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
184 reset-names = "stmmaceth"; !! 330 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
185 rockchip,grf = <&grf>; !! 331 arm,pl330-periph-burst;
186 snps,axi-config = <&gmac0_stmm !! 332 clocks = <&cru ACLK_BUS>;
187 snps,mixed-burst; !! 333 clock-names = "apb_pclk";
188 snps,mtl-rx-config = <&gmac0_m !! 334 #dma-cells = <1>;
189 snps,mtl-tx-config = <&gmac0_m !! 335 };
190 snps,tso; !! 336
>> 337 i2c1: i2c@fe5a0000 {
>> 338 compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c";
>> 339 reg = <0x0 0xfe5a0000 0x0 0x1000>;
>> 340 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
>> 341 clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>;
>> 342 clock-names = "i2c", "pclk";
>> 343 pinctrl-0 = <&i2c1_xfer>;
>> 344 pinctrl-names = "default";
>> 345 #address-cells = <1>;
>> 346 #size-cells = <0>;
191 status = "disabled"; 347 status = "disabled";
>> 348 };
192 349
193 mdio0: mdio { !! 350 i2c2: i2c@fe5b0000 {
194 compatible = "snps,dwm !! 351 compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c";
195 #address-cells = <0x1> !! 352 reg = <0x0 0xfe5b0000 0x0 0x1000>;
196 #size-cells = <0x0>; !! 353 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
197 }; !! 354 clocks = <&cru CLK_I2C2>, <&cru PCLK_I2C2>;
>> 355 clock-names = "i2c", "pclk";
>> 356 pinctrl-0 = <&i2c2m0_xfer>;
>> 357 pinctrl-names = "default";
>> 358 #address-cells = <1>;
>> 359 #size-cells = <0>;
>> 360 status = "disabled";
>> 361 };
198 362
199 gmac0_stmmac_axi_setup: stmmac !! 363 i2c3: i2c@fe5c0000 {
200 snps,blen = <0 0 0 0 1 !! 364 compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c";
201 snps,rd_osr_lmt = <8>; !! 365 reg = <0x0 0xfe5c0000 0x0 0x1000>;
202 snps,wr_osr_lmt = <4>; !! 366 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
203 }; !! 367 clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>;
>> 368 clock-names = "i2c", "pclk";
>> 369 pinctrl-0 = <&i2c3m0_xfer>;
>> 370 pinctrl-names = "default";
>> 371 #address-cells = <1>;
>> 372 #size-cells = <0>;
>> 373 status = "disabled";
>> 374 };
204 375
205 gmac0_mtl_rx_setup: rx-queues- !! 376 i2c4: i2c@fe5d0000 {
206 snps,rx-queues-to-use !! 377 compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c";
207 queue0 {}; !! 378 reg = <0x0 0xfe5d0000 0x0 0x1000>;
208 }; !! 379 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
>> 380 clocks = <&cru CLK_I2C4>, <&cru PCLK_I2C4>;
>> 381 clock-names = "i2c", "pclk";
>> 382 pinctrl-0 = <&i2c4m0_xfer>;
>> 383 pinctrl-names = "default";
>> 384 #address-cells = <1>;
>> 385 #size-cells = <0>;
>> 386 status = "disabled";
>> 387 };
209 388
210 gmac0_mtl_tx_setup: tx-queues- !! 389 i2c5: i2c@fe5e0000 {
211 snps,tx-queues-to-use !! 390 compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c";
212 queue0 {}; !! 391 reg = <0x0 0xfe5e0000 0x0 0x1000>;
213 }; !! 392 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
>> 393 clocks = <&cru CLK_I2C5>, <&cru PCLK_I2C5>;
>> 394 clock-names = "i2c", "pclk";
>> 395 pinctrl-0 = <&i2c5m0_xfer>;
>> 396 pinctrl-names = "default";
>> 397 #address-cells = <1>;
>> 398 #size-cells = <0>;
>> 399 status = "disabled";
214 }; 400 };
215 401
216 can0: can@fe570000 { !! 402 uart1: serial@fe650000 {
217 compatible = "rockchip,rk3568v !! 403 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
218 reg = <0x0 0xfe570000 0x0 0x10 !! 404 reg = <0x0 0xfe650000 0x0 0x100>;
219 interrupts = <GIC_SPI 1 IRQ_TY !! 405 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
220 clocks = <&cru CLK_CAN0>, <&cr !! 406 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
221 clock-names = "baud", "pclk"; !! 407 clock-names = "baudclk", "apb_pclk";
222 resets = <&cru SRST_CAN0>, <&c !! 408 dmas = <&dmac0 2>, <&dmac0 3>;
223 reset-names = "core", "apb"; !! 409 pinctrl-0 = <&uart1m0_xfer>;
224 pinctrl-names = "default"; 410 pinctrl-names = "default";
225 pinctrl-0 = <&can0m0_pins>; !! 411 reg-io-width = <4>;
>> 412 reg-shift = <2>;
226 status = "disabled"; 413 status = "disabled";
227 }; 414 };
228 415
229 can1: can@fe580000 { !! 416 uart2: serial@fe660000 {
230 compatible = "rockchip,rk3568v !! 417 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
231 reg = <0x0 0xfe580000 0x0 0x10 !! 418 reg = <0x0 0xfe660000 0x0 0x100>;
232 interrupts = <GIC_SPI 2 IRQ_TY !! 419 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
233 clocks = <&cru CLK_CAN1>, <&cr !! 420 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
234 clock-names = "baud", "pclk"; !! 421 clock-names = "baudclk", "apb_pclk";
235 resets = <&cru SRST_CAN1>, <&c !! 422 dmas = <&dmac0 4>, <&dmac0 5>;
236 reset-names = "core", "apb"; !! 423 pinctrl-0 = <&uart2m0_xfer>;
237 pinctrl-names = "default"; 424 pinctrl-names = "default";
238 pinctrl-0 = <&can1m0_pins>; !! 425 reg-io-width = <4>;
>> 426 reg-shift = <2>;
239 status = "disabled"; 427 status = "disabled";
240 }; 428 };
241 429
242 can2: can@fe590000 { !! 430 uart3: serial@fe670000 {
243 compatible = "rockchip,rk3568v !! 431 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
244 reg = <0x0 0xfe590000 0x0 0x10 !! 432 reg = <0x0 0xfe670000 0x0 0x100>;
245 interrupts = <GIC_SPI 3 IRQ_TY !! 433 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
246 clocks = <&cru CLK_CAN2>, <&cr !! 434 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
247 clock-names = "baud", "pclk"; !! 435 clock-names = "baudclk", "apb_pclk";
248 resets = <&cru SRST_CAN2>, <&c !! 436 dmas = <&dmac0 6>, <&dmac0 7>;
249 reset-names = "core", "apb"; !! 437 pinctrl-0 = <&uart3m0_xfer>;
250 pinctrl-names = "default"; 438 pinctrl-names = "default";
251 pinctrl-0 = <&can2m0_pins>; !! 439 reg-io-width = <4>;
>> 440 reg-shift = <2>;
252 status = "disabled"; 441 status = "disabled";
253 }; 442 };
254 443
255 combphy0: phy@fe820000 { !! 444 uart4: serial@fe680000 {
256 compatible = "rockchip,rk3568- !! 445 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
257 reg = <0x0 0xfe820000 0x0 0x10 !! 446 reg = <0x0 0xfe680000 0x0 0x100>;
258 clocks = <&pmucru CLK_PCIEPHY0 !! 447 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
259 <&cru PCLK_PIPEPHY0>, !! 448 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
260 <&cru PCLK_PIPE>; !! 449 clock-names = "baudclk", "apb_pclk";
261 clock-names = "ref", "apb", "p !! 450 dmas = <&dmac0 8>, <&dmac0 9>;
262 assigned-clocks = <&pmucru CLK !! 451 pinctrl-0 = <&uart4m0_xfer>;
263 assigned-clock-rates = <100000 !! 452 pinctrl-names = "default";
264 resets = <&cru SRST_PIPEPHY0>; !! 453 reg-io-width = <4>;
265 rockchip,pipe-grf = <&pipegrf> !! 454 reg-shift = <2>;
266 rockchip,pipe-phy-grf = <&pipe <<
267 #phy-cells = <1>; <<
268 status = "disabled"; 455 status = "disabled";
269 }; 456 };
270 }; <<
271 457
272 &cpu0_opp_table { !! 458 uart5: serial@fe690000 {
273 opp-1992000000 { !! 459 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
274 opp-hz = /bits/ 64 <1992000000 !! 460 reg = <0x0 0xfe690000 0x0 0x100>;
275 opp-microvolt = <1150000 11500 !! 461 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
>> 462 clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>;
>> 463 clock-names = "baudclk", "apb_pclk";
>> 464 dmas = <&dmac0 10>, <&dmac0 11>;
>> 465 pinctrl-0 = <&uart5m0_xfer>;
>> 466 pinctrl-names = "default";
>> 467 reg-io-width = <4>;
>> 468 reg-shift = <2>;
>> 469 status = "disabled";
276 }; 470 };
277 }; <<
278 471
279 &pipegrf { !! 472 uart6: serial@fe6a0000 {
280 compatible = "rockchip,rk3568-pipe-grf !! 473 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
281 }; !! 474 reg = <0x0 0xfe6a0000 0x0 0x100>;
>> 475 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
>> 476 clocks = <&cru SCLK_UART6>, <&cru PCLK_UART6>;
>> 477 clock-names = "baudclk", "apb_pclk";
>> 478 dmas = <&dmac0 12>, <&dmac0 13>;
>> 479 pinctrl-0 = <&uart6m0_xfer>;
>> 480 pinctrl-names = "default";
>> 481 reg-io-width = <4>;
>> 482 reg-shift = <2>;
>> 483 status = "disabled";
>> 484 };
282 485
283 &power { !! 486 uart7: serial@fe6b0000 {
284 power-domain@RK3568_PD_PIPE { !! 487 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
285 reg = <RK3568_PD_PIPE>; !! 488 reg = <0x0 0xfe6b0000 0x0 0x100>;
286 clocks = <&cru PCLK_PIPE>; !! 489 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
287 pm_qos = <&qos_pcie2x1>, !! 490 clocks = <&cru SCLK_UART7>, <&cru PCLK_UART7>;
288 <&qos_pcie3x1>, !! 491 clock-names = "baudclk", "apb_pclk";
289 <&qos_pcie3x2>, !! 492 dmas = <&dmac0 14>, <&dmac0 15>;
290 <&qos_sata0>, !! 493 pinctrl-0 = <&uart7m0_xfer>;
291 <&qos_sata1>, !! 494 pinctrl-names = "default";
292 <&qos_sata2>, !! 495 reg-io-width = <4>;
293 <&qos_usb3_0>, !! 496 reg-shift = <2>;
294 <&qos_usb3_1>; !! 497 status = "disabled";
295 #power-domain-cells = <0>; <<
296 }; 498 };
297 }; <<
298 499
299 &rng { !! 500 uart8: serial@fe6c0000 {
300 status = "okay"; !! 501 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
301 }; !! 502 reg = <0x0 0xfe6c0000 0x0 0x100>;
>> 503 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
>> 504 clocks = <&cru SCLK_UART8>, <&cru PCLK_UART8>;
>> 505 clock-names = "baudclk", "apb_pclk";
>> 506 dmas = <&dmac0 16>, <&dmac0 17>;
>> 507 pinctrl-0 = <&uart8m0_xfer>;
>> 508 pinctrl-names = "default";
>> 509 reg-io-width = <4>;
>> 510 reg-shift = <2>;
>> 511 status = "disabled";
>> 512 };
302 513
303 &usb_host0_xhci { !! 514 uart9: serial@fe6d0000 {
304 phys = <&usb2phy0_otg>, <&combphy0 PHY !! 515 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
305 phy-names = "usb2-phy", "usb3-phy"; !! 516 reg = <0x0 0xfe6d0000 0x0 0x100>;
306 }; !! 517 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
>> 518 clocks = <&cru SCLK_UART9>, <&cru PCLK_UART9>;
>> 519 clock-names = "baudclk", "apb_pclk";
>> 520 dmas = <&dmac0 18>, <&dmac0 19>;
>> 521 pinctrl-0 = <&uart9m0_xfer>;
>> 522 pinctrl-names = "default";
>> 523 reg-io-width = <4>;
>> 524 reg-shift = <2>;
>> 525 status = "disabled";
>> 526 };
>> 527
>> 528 pinctrl: pinctrl {
>> 529 compatible = "rockchip,rk3568-pinctrl";
>> 530 rockchip,grf = <&grf>;
>> 531 rockchip,pmu = <&pmugrf>;
>> 532 #address-cells = <2>;
>> 533 #size-cells = <2>;
>> 534 ranges;
>> 535
>> 536 gpio0: gpio@fdd60000 {
>> 537 compatible = "rockchip,gpio-bank";
>> 538 reg = <0x0 0xfdd60000 0x0 0x100>;
>> 539 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
>> 540 clocks = <&pmucru PCLK_GPIO0>;
>> 541 gpio-controller;
>> 542 #gpio-cells = <2>;
>> 543 interrupt-controller;
>> 544 #interrupt-cells = <2>;
>> 545 };
>> 546
>> 547 gpio1: gpio@fe740000 {
>> 548 compatible = "rockchip,gpio-bank";
>> 549 reg = <0x0 0xfe740000 0x0 0x100>;
>> 550 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
>> 551 clocks = <&cru PCLK_GPIO1>;
>> 552 gpio-controller;
>> 553 #gpio-cells = <2>;
>> 554 interrupt-controller;
>> 555 #interrupt-cells = <2>;
>> 556 };
>> 557
>> 558 gpio2: gpio@fe750000 {
>> 559 compatible = "rockchip,gpio-bank";
>> 560 reg = <0x0 0xfe750000 0x0 0x100>;
>> 561 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
>> 562 clocks = <&cru PCLK_GPIO2>;
>> 563 gpio-controller;
>> 564 #gpio-cells = <2>;
>> 565 interrupt-controller;
>> 566 #interrupt-cells = <2>;
>> 567 };
>> 568
>> 569 gpio3: gpio@fe760000 {
>> 570 compatible = "rockchip,gpio-bank";
>> 571 reg = <0x0 0xfe760000 0x0 0x100>;
>> 572 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
>> 573 clocks = <&cru PCLK_GPIO3>;
>> 574 gpio-controller;
>> 575 #gpio-cells = <2>;
>> 576 interrupt-controller;
>> 577 #interrupt-cells = <2>;
>> 578 };
307 579
308 &vop { !! 580 gpio4: gpio@fe770000 {
309 compatible = "rockchip,rk3568-vop"; !! 581 compatible = "rockchip,gpio-bank";
>> 582 reg = <0x0 0xfe770000 0x0 0x100>;
>> 583 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
>> 584 clocks = <&cru PCLK_GPIO4>;
>> 585 gpio-controller;
>> 586 #gpio-cells = <2>;
>> 587 interrupt-controller;
>> 588 #interrupt-cells = <2>;
>> 589 };
>> 590 };
310 }; 591 };
>> 592
>> 593 #include "rk3568-pinctrl.dtsi"
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