1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2
3 /dts-v1/;
4
5 #include <dt-bindings/gpio/gpio.h>
6 #include <dt-bindings/leds/common.h>
7 #include "rk3588.dtsi"
8
9 / {
10 model = "ArmSoM Sige7";
11 compatible = "armsom,sige7", "rockchip
12
13 aliases {
14 mmc0 = &sdhci;
15 mmc1 = &sdmmc;
16 };
17
18 chosen {
19 stdout-path = "serial2:1500000
20 };
21
22 analog-sound {
23 compatible = "audio-graph-card
24 dais = <&i2s0_8ch_p0>;
25 label = "rk3588-es8316";
26 hp-det-gpio = <&gpio1 RK_PD5 G
27 pinctrl-names = "default";
28 pinctrl-0 = <&hp_detect>;
29 routing = "MIC2", "Mic Jack",
30 "Headphones", "HPOL"
31 "Headphones", "HPOR"
32 widgets = "Microphone", "Mic J
33 "Headphone", "Headph
34 };
35
36 leds {
37 compatible = "gpio-leds";
38 pinctrl-names = "default";
39 pinctrl-0 = <&led_rgb_g>;
40
41 led_green: led-0 {
42 color = <LED_COLOR_ID_
43 function = LED_FUNCTIO
44 gpios = <&gpio0 RK_PB7
45 linux,default-trigger
46 };
47
48 led_red: led-1 {
49 color = <LED_COLOR_ID_
50 function = LED_FUNCTIO
51 gpios = <&gpio4 RK_PC5
52 linux,default-trigger
53 };
54 };
55
56 fan: pwm-fan {
57 compatible = "pwm-fan";
58 cooling-levels = <0 95 145 195
59 fan-supply = <&vcc5v0_sys>;
60 pwms = <&pwm1 0 50000 0>;
61 #cooling-cells = <2>;
62 };
63
64 vcc3v3_pcie2x1l2: vcc3v3-pcie2x1l2-reg
65 compatible = "regulator-fixed"
66 regulator-name = "vcc3v3_pcie2
67 regulator-min-microvolt = <330
68 regulator-max-microvolt = <330
69 startup-delay-us = <5000>;
70 vin-supply = <&vcc_3v3_s3>;
71 };
72
73 vcc3v3_pcie30: vcc3v3-pcie30-regulator
74 compatible = "regulator-fixed"
75 enable-active-high;
76 gpios = <&gpio1 RK_PA4 GPIO_AC
77 regulator-name = "vcc3v3_pcie3
78 regulator-min-microvolt = <330
79 regulator-max-microvolt = <330
80 startup-delay-us = <5000>;
81 vin-supply = <&vcc5v0_sys>;
82 };
83
84 vcc5v0_host: vcc5v0-host-regulator {
85 compatible = "regulator-fixed"
86 regulator-name = "vcc5v0_host"
87 regulator-boot-on;
88 regulator-always-on;
89 regulator-min-microvolt = <500
90 regulator-max-microvolt = <500
91 enable-active-high;
92 gpio = <&gpio4 RK_PB0 GPIO_ACT
93 pinctrl-names = "default";
94 pinctrl-0 = <&vcc5v0_host_en>;
95 vin-supply = <&vcc5v0_sys>;
96 };
97
98 vcc5v0_sys: vcc5v0-sys-regulator {
99 compatible = "regulator-fixed"
100 regulator-name = "vcc5v0_sys";
101 regulator-always-on;
102 regulator-boot-on;
103 regulator-min-microvolt = <500
104 regulator-max-microvolt = <500
105 };
106
107 vcc_1v1_nldo_s3: vcc-1v1-nldo-s3-regul
108 compatible = "regulator-fixed"
109 regulator-name = "vcc_1v1_nldo
110 regulator-always-on;
111 regulator-boot-on;
112 regulator-min-microvolt = <110
113 regulator-max-microvolt = <110
114 vin-supply = <&vcc5v0_sys>;
115 };
116 };
117
118 &combphy0_ps {
119 status = "okay";
120 };
121
122 &combphy1_ps {
123 status = "okay";
124 };
125
126 &combphy2_psu {
127 status = "okay";
128 };
129
130 &cpu_b0 {
131 cpu-supply = <&vdd_cpu_big0_s0>;
132 };
133
134 &cpu_b1 {
135 cpu-supply = <&vdd_cpu_big0_s0>;
136 };
137
138 &cpu_b2 {
139 cpu-supply = <&vdd_cpu_big1_s0>;
140 };
141
142 &cpu_b3 {
143 cpu-supply = <&vdd_cpu_big1_s0>;
144 };
145
146 &cpu_l0 {
147 cpu-supply = <&vdd_cpu_lit_s0>;
148 };
149
150 &cpu_l1 {
151 cpu-supply = <&vdd_cpu_lit_s0>;
152 };
153
154 &cpu_l2 {
155 cpu-supply = <&vdd_cpu_lit_s0>;
156 };
157
158 &cpu_l3 {
159 cpu-supply = <&vdd_cpu_lit_s0>;
160 };
161
162 &gpu {
163 mali-supply = <&vdd_gpu_s0>;
164 status = "okay";
165 };
166
167 &i2c0 {
168 pinctrl-names = "default";
169 pinctrl-0 = <&i2c0m2_xfer>;
170 status = "okay";
171
172 vdd_cpu_big0_s0: regulator@42 {
173 compatible = "rockchip,rk8602"
174 reg = <0x42>;
175 fcs,suspend-voltage-selector =
176 regulator-name = "vdd_cpu_big0
177 regulator-always-on;
178 regulator-boot-on;
179 regulator-min-microvolt = <550
180 regulator-max-microvolt = <105
181 regulator-ramp-delay = <2300>;
182 vin-supply = <&vcc5v0_sys>;
183
184 regulator-state-mem {
185 regulator-off-in-suspe
186 };
187 };
188
189 vdd_cpu_big1_s0: regulator@43 {
190 compatible = "rockchip,rk8603"
191 reg = <0x43>;
192 fcs,suspend-voltage-selector =
193 regulator-name = "vdd_cpu_big1
194 regulator-always-on;
195 regulator-boot-on;
196 regulator-min-microvolt = <550
197 regulator-max-microvolt = <105
198 regulator-ramp-delay = <2300>;
199 vin-supply = <&vcc5v0_sys>;
200
201 regulator-state-mem {
202 regulator-off-in-suspe
203 };
204 };
205 };
206
207 &i2c6 {
208 status = "okay";
209
210 hym8563: rtc@51 {
211 compatible = "haoyu,hym8563";
212 reg = <0x51>;
213 interrupt-parent = <&gpio0>;
214 interrupts = <RK_PB0 IRQ_TYPE_
215 #clock-cells = <0>;
216 clock-output-names = "hym8563"
217 pinctrl-names = "default";
218 pinctrl-0 = <&hym8563_int>;
219 wakeup-source;
220 };
221 };
222
223 &i2c7 {
224 status = "okay";
225
226 es8316: audio-codec@11 {
227 compatible = "everest,es8316";
228 reg = <0x11>;
229 assigned-clocks = <&cru I2S0_8
230 assigned-clock-rates = <122880
231 clocks = <&cru I2S0_8CH_MCLKOU
232 clock-names = "mclk";
233 #sound-dai-cells = <0>;
234
235 port {
236 es8316_p0_0: endpoint
237 remote-endpoin
238 };
239 };
240 };
241 };
242
243 &i2s0_8ch {
244 pinctrl-names = "default";
245 pinctrl-0 = <&i2s0_lrck
246 &i2s0_mclk
247 &i2s0_sclk
248 &i2s0_sdi0
249 &i2s0_sdo0>;
250 status = "okay";
251
252 i2s0_8ch_p0: port {
253 i2s0_8ch_p0_0: endpoint {
254 dai-format = "i2s";
255 mclk-fs = <256>;
256 remote-endpoint = <&es
257 };
258 };
259 };
260
261 /* phy1 - right ethernet port */
262 &pcie2x1l0 {
263 reset-gpios = <&gpio4 RK_PA5 GPIO_ACTI
264 status = "okay";
265 };
266
267 /* phy2 - WiFi */
268 &pcie2x1l1 {
269 reset-gpios = <&gpio3 RK_PD4 GPIO_ACTI
270 status = "okay";
271 };
272
273 /* phy0 - left ethernet port */
274 &pcie2x1l2 {
275 reset-gpios = <&gpio3 RK_PB0 GPIO_ACTI
276 status = "okay";
277 };
278
279 &pcie30phy {
280 status = "okay";
281 };
282
283 &pcie3x4 {
284 reset-gpios = <&gpio4 RK_PB6 GPIO_ACTI
285 vpcie3v3-supply = <&vcc3v3_pcie30>;
286 status = "okay";
287 };
288
289 &pinctrl {
290 hym8563 {
291 hym8563_int: hym8563-int {
292 rockchip,pins = <0 RK_
293 };
294 };
295
296 leds {
297 led_rgb_g: led-rgb-g {
298 rockchip,pins = <0 RK_
299 };
300 led_rgb_r: led-rgb-r {
301 rockchip,pins = <0 RK_
302 };
303 };
304
305 sound {
306 hp_detect: hp-detect {
307 rockchip,pins = <1 RK_
308 };
309 };
310
311 usb {
312 vcc5v0_host_en: vcc5v0-host-en
313 rockchip,pins = <4 RK_
314 };
315 };
316 };
317
318 &pwm1 {
319 status = "okay";
320 };
321
322 &saradc {
323 vref-supply = <&avcc_1v8_s0>;
324 status = "okay";
325 };
326
327 &sdhci {
328 bus-width = <8>;
329 no-sdio;
330 no-sd;
331 non-removable;
332 mmc-hs200-1_8v;
333 status = "okay";
334 };
335
336 &sdmmc {
337 bus-width = <4>;
338 cap-mmc-highspeed;
339 cap-sd-highspeed;
340 disable-wp;
341 max-frequency = <200000000>;
342 no-sdio;
343 no-mmc;
344 sd-uhs-sdr104;
345 vmmc-supply = <&vcc_3v3_s3>;
346 vqmmc-supply = <&vccio_sd_s0>;
347 status = "okay";
348 };
349
350 &spi2 {
351 assigned-clocks = <&cru CLK_SPI2>;
352 assigned-clock-rates = <200000000>;
353 num-cs = <1>;
354 pinctrl-names = "default";
355 pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>
356 status = "okay";
357
358 pmic@0 {
359 compatible = "rockchip,rk806";
360 spi-max-frequency = <1000000>;
361 reg = <0x0>;
362
363 interrupt-parent = <&gpio0>;
364 interrupts = <7 IRQ_TYPE_LEVEL
365
366 gpio-controller;
367 #gpio-cells = <2>;
368
369 pinctrl-names = "default";
370 pinctrl-0 = <&pmic_pins>, <&rk
371 <&rk806_dvs2_null>
372
373 system-power-controller;
374
375 vcc1-supply = <&vcc5v0_sys>;
376 vcc2-supply = <&vcc5v0_sys>;
377 vcc3-supply = <&vcc5v0_sys>;
378 vcc4-supply = <&vcc5v0_sys>;
379 vcc5-supply = <&vcc5v0_sys>;
380 vcc6-supply = <&vcc5v0_sys>;
381 vcc7-supply = <&vcc5v0_sys>;
382 vcc8-supply = <&vcc5v0_sys>;
383 vcc9-supply = <&vcc5v0_sys>;
384 vcc10-supply = <&vcc5v0_sys>;
385 vcc11-supply = <&vcc_2v0_pldo_
386 vcc12-supply = <&vcc5v0_sys>;
387 vcc13-supply = <&vcc_1v1_nldo_
388 vcc14-supply = <&vcc_1v1_nldo_
389 vcca-supply = <&vcc5v0_sys>;
390
391 rk806_dvs1_null: dvs1-null-pin
392 pins = "gpio_pwrctrl1"
393 function = "pin_fun0";
394 };
395
396 rk806_dvs2_null: dvs2-null-pin
397 pins = "gpio_pwrctrl2"
398 function = "pin_fun0";
399 };
400
401 rk806_dvs3_null: dvs3-null-pin
402 pins = "gpio_pwrctrl3"
403 function = "pin_fun0";
404 };
405
406 regulators {
407 vdd_gpu_s0: vdd_gpu_me
408 regulator-alwa
409 regulator-boot
410 regulator-min-
411 regulator-max-
412 regulator-ramp
413 regulator-name
414 regulator-enab
415
416 regulator-stat
417 regula
418 };
419 };
420
421 vdd_cpu_lit_s0: vdd_cp
422 regulator-alwa
423 regulator-boot
424 regulator-min-
425 regulator-max-
426 regulator-ramp
427 regulator-name
428
429 regulator-stat
430 regula
431 };
432 };
433
434 vdd_log_s0: dcdc-reg3
435 regulator-alwa
436 regulator-boot
437 regulator-min-
438 regulator-max-
439 regulator-ramp
440 regulator-name
441
442 regulator-stat
443 regula
444 regula
445 };
446 };
447
448 vdd_vdenc_s0: vdd_vden
449 regulator-alwa
450 regulator-boot
451 regulator-min-
452 regulator-max-
453 regulator-ramp
454 regulator-name
455
456 regulator-stat
457 regula
458 };
459 };
460
461 vdd_ddr_s0: dcdc-reg5
462 regulator-alwa
463 regulator-boot
464 regulator-min-
465 regulator-max-
466 regulator-ramp
467 regulator-name
468
469 regulator-stat
470 regula
471 regula
472 };
473 };
474
475 vdd2_ddr_s3: dcdc-reg6
476 regulator-alwa
477 regulator-boot
478 regulator-name
479
480 regulator-stat
481 regula
482 };
483 };
484
485 vcc_2v0_pldo_s3: dcdc-
486 regulator-alwa
487 regulator-boot
488 regulator-min-
489 regulator-max-
490 regulator-ramp
491 regulator-name
492
493 regulator-stat
494 regula
495 regula
496 };
497 };
498
499 vcc_3v3_s3: dcdc-reg8
500 regulator-alwa
501 regulator-boot
502 regulator-min-
503 regulator-max-
504 regulator-name
505
506 regulator-stat
507 regula
508 regula
509 };
510 };
511
512 vddq_ddr_s0: dcdc-reg9
513 regulator-alwa
514 regulator-boot
515 regulator-name
516
517 regulator-stat
518 regula
519 };
520 };
521
522 vcc_1v8_s3: dcdc-reg10
523 regulator-alwa
524 regulator-boot
525 regulator-min-
526 regulator-max-
527 regulator-name
528
529 regulator-stat
530 regula
531 regula
532 };
533 };
534
535 avcc_1v8_s0: pldo-reg1
536 regulator-alwa
537 regulator-boot
538 regulator-min-
539 regulator-max-
540 regulator-name
541
542 regulator-stat
543 regula
544 };
545 };
546
547 vcc_1v8_s0: pldo-reg2
548 regulator-alwa
549 regulator-boot
550 regulator-min-
551 regulator-max-
552 regulator-name
553
554 regulator-stat
555 regula
556 regula
557 };
558 };
559
560 avdd_1v2_s0: pldo-reg3
561 regulator-alwa
562 regulator-boot
563 regulator-min-
564 regulator-max-
565 regulator-name
566
567 regulator-stat
568 regula
569 };
570 };
571
572 vcc_3v3_s0: pldo-reg4
573 regulator-alwa
574 regulator-boot
575 regulator-min-
576 regulator-max-
577 regulator-ramp
578 regulator-name
579
580 regulator-stat
581 regula
582 };
583 };
584
585 vccio_sd_s0: pldo-reg5
586 regulator-alwa
587 regulator-boot
588 regulator-min-
589 regulator-max-
590 regulator-ramp
591 regulator-name
592
593 regulator-stat
594 regula
595 };
596 };
597
598 pldo6_s3: pldo-reg6 {
599 regulator-alwa
600 regulator-boot
601 regulator-min-
602 regulator-max-
603 regulator-name
604
605 regulator-stat
606 regula
607 regula
608 };
609 };
610
611 vdd_0v75_s3: nldo-reg1
612 regulator-alwa
613 regulator-boot
614 regulator-min-
615 regulator-max-
616 regulator-name
617
618 regulator-stat
619 regula
620 regula
621 };
622 };
623
624 vdd_ddr_pll_s0: nldo-r
625 regulator-alwa
626 regulator-boot
627 regulator-min-
628 regulator-max-
629 regulator-name
630
631 regulator-stat
632 regula
633 regula
634 };
635 };
636
637 avdd_0v75_s0: nldo-reg
638 regulator-alwa
639 regulator-boot
640 regulator-min-
641 regulator-max-
642 regulator-name
643
644 regulator-stat
645 regula
646 };
647 };
648
649 vdd_0v85_s0: nldo-reg4
650 regulator-alwa
651 regulator-boot
652 regulator-min-
653 regulator-max-
654 regulator-name
655
656 regulator-stat
657 regula
658 };
659 };
660
661 vdd_0v75_s0: nldo-reg5
662 regulator-alwa
663 regulator-boot
664 regulator-min-
665 regulator-max-
666 regulator-name
667
668 regulator-stat
669 regula
670 };
671 };
672 };
673 };
674 };
675
676 &tsadc {
677 status = "okay";
678 };
679
680 &u2phy0 {
681 status = "okay";
682 };
683
684 &u2phy0_otg {
685 status = "okay";
686 };
687
688 &u2phy1 {
689 status = "okay";
690 };
691
692 &u2phy1_otg {
693 status = "okay";
694 };
695
696 &u2phy3 {
697 status = "okay";
698 };
699
700 &u2phy3_host {
701 phy-supply = <&vcc5v0_host>;
702 status = "okay";
703 };
704
705 &uart2 {
706 pinctrl-0 = <&uart2m0_xfer>;
707 status = "okay";
708 };
709
710 &usbdp_phy1 {
711 status = "okay";
712 };
713
714 &usb_host1_ehci {
715 status = "okay";
716 };
717
718 &usb_host1_ohci {
719 status = "okay";
720 };
721
722 &usb_host1_xhci {
723 dr_mode = "host";
724 status = "okay";
725 };
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