1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /*
3 * Copyright (c) 2023 Edgeble AI Technologies
4 */
5
6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/leds/common.h>
8
9 / {
10 aliases {
11 mmc0 = &sdhci;
12 };
13
14 gpio-leds {
15 compatible = "gpio-leds";
16
17 led_user: led-0 {
18 color = <LED_COLOR_ID_
19 function = LED_FUNCTIO
20 gpios = <&gpio0 RK_PC2
21 linux,default-trigger
22 pinctrl-names = "defau
23 pinctrl-0 = <&led_user
24 };
25 };
26
27 vcc12v_dcin: vcc12v-dcin-regulator {
28 compatible = "regulator-fixed"
29 regulator-name = "vcc12v_dcin"
30 regulator-always-on;
31 regulator-boot-on;
32 regulator-min-microvolt = <120
33 regulator-max-microvolt = <120
34 };
35
36 vcc5v0_sys: vcc5v0-sys-regulator {
37 compatible = "regulator-fixed"
38 regulator-name = "vcc5v0_sys";
39 regulator-always-on;
40 regulator-boot-on;
41 regulator-min-microvolt = <500
42 regulator-max-microvolt = <500
43 vin-supply = <&vcc12v_dcin>;
44 };
45
46 vcc_1v1_nldo_s3: vcc-1v1-nldo-s3-regul
47 compatible = "regulator-fixed"
48 regulator-name = "vcc_1v1_nldo
49 regulator-always-on;
50 regulator-boot-on;
51 regulator-min-microvolt = <110
52 regulator-max-microvolt = <110
53 vin-supply = <&vcc5v0_sys>;
54 };
55 };
56
57 &cpu_b0 {
58 cpu-supply = <&vdd_cpu_big0_s0>;
59 };
60
61 &cpu_b1 {
62 cpu-supply = <&vdd_cpu_big0_s0>;
63 };
64
65 &cpu_b2 {
66 cpu-supply = <&vdd_cpu_big1_s0>;
67 };
68
69 &cpu_b3 {
70 cpu-supply = <&vdd_cpu_big1_s0>;
71 };
72
73 &cpu_l0 {
74 cpu-supply = <&vdd_cpu_lit_s0>;
75 };
76
77 &cpu_l1 {
78 cpu-supply = <&vdd_cpu_lit_s0>;
79 };
80
81 &cpu_l2 {
82 cpu-supply = <&vdd_cpu_lit_s0>;
83 };
84
85 &cpu_l3 {
86 cpu-supply = <&vdd_cpu_lit_s0>;
87 };
88
89 &i2c0 {
90 pinctrl-names = "default";
91 pinctrl-0 = <&i2c0m2_xfer>;
92 status = "okay";
93
94 vdd_cpu_big0_s0: regulator@42 {
95 compatible = "rockchip,rk8602"
96 reg = <0x42>;
97 fcs,suspend-voltage-selector =
98 regulator-name = "vdd_cpu_big0
99 regulator-always-on;
100 regulator-boot-on;
101 regulator-min-microvolt = <550
102 regulator-max-microvolt = <105
103 regulator-ramp-delay = <2300>;
104 vin-supply = <&vcc5v0_sys>;
105
106 regulator-state-mem {
107 regulator-off-in-suspe
108 };
109 };
110
111 vdd_cpu_big1_s0: regulator@43 {
112 compatible = "rockchip,rk8603"
113 reg = <0x43>;
114 fcs,suspend-voltage-selector =
115 regulator-name = "vdd_cpu_big1
116 regulator-always-on;
117 regulator-boot-on;
118 regulator-min-microvolt = <550
119 regulator-max-microvolt = <105
120 regulator-ramp-delay = <2300>;
121 vin-supply = <&vcc5v0_sys>;
122
123 regulator-state-mem {
124 regulator-off-in-suspe
125 };
126 };
127 };
128
129 &pinctrl {
130 leds {
131 led_user_en: led_user_en {
132 rockchip,pins = <0 RK_
133 };
134 };
135 };
136
137 &sdhci {
138 bus-width = <8>;
139 no-sdio;
140 no-sd;
141 non-removable;
142 mmc-hs400-1_8v;
143 mmc-hs400-enhanced-strobe;
144 status = "okay";
145 };
146
147 &spi2 {
148 status = "okay";
149 assigned-clocks = <&cru CLK_SPI2>;
150 assigned-clock-rates = <200000000>;
151 num-cs = <1>;
152 pinctrl-names = "default";
153 pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>
154
155 pmic@0 {
156 compatible = "rockchip,rk806";
157 spi-max-frequency = <1000000>;
158 reg = <0x0>;
159 interrupt-parent = <&gpio0>;
160 interrupts = <RK_PA7 IRQ_TYPE_
161 pinctrl-names = "default";
162 pinctrl-0 = <&pmic_pins>, <&rk
163 <&rk806_dvs2_null>
164
165 system-power-controller;
166
167 vcc1-supply = <&vcc5v0_sys>;
168 vcc2-supply = <&vcc5v0_sys>;
169 vcc3-supply = <&vcc5v0_sys>;
170 vcc4-supply = <&vcc5v0_sys>;
171 vcc5-supply = <&vcc5v0_sys>;
172 vcc6-supply = <&vcc5v0_sys>;
173 vcc7-supply = <&vcc5v0_sys>;
174 vcc8-supply = <&vcc5v0_sys>;
175 vcc9-supply = <&vcc5v0_sys>;
176 vcc10-supply = <&vcc5v0_sys>;
177 vcc11-supply = <&vcc_2v0_pldo_
178 vcc12-supply = <&vcc5v0_sys>;
179 vcc13-supply = <&vcc_1v1_nldo_
180 vcc14-supply = <&vcc_1v1_nldo_
181 vcca-supply = <&vcc5v0_sys>;
182
183 gpio-controller;
184 #gpio-cells = <2>;
185
186 rk806_dvs1_null: dvs1-null-pin
187 pins = "gpio_pwrctrl1"
188 function = "pin_fun0";
189 };
190
191 rk806_dvs2_null: dvs2-null-pin
192 pins = "gpio_pwrctrl2"
193 function = "pin_fun0";
194 };
195
196 rk806_dvs3_null: dvs3-null-pin
197 pins = "gpio_pwrctrl3"
198 function = "pin_fun0";
199 };
200
201 regulators {
202 vdd_gpu_s0: vdd_gpu_me
203 regulator-name
204 regulator-boot
205 regulator-min-
206 regulator-max-
207 regulator-ramp
208 regulator-enab
209
210 regulator-stat
211 regula
212 };
213 };
214
215 vdd_cpu_lit_s0: vdd_cp
216 regulator-name
217 regulator-alwa
218 regulator-boot
219 regulator-min-
220 regulator-max-
221 regulator-ramp
222
223 regulator-stat
224 regula
225 };
226 };
227
228 vdd_log_s0: dcdc-reg3
229 regulator-name
230 regulator-alwa
231 regulator-boot
232 regulator-min-
233 regulator-max-
234 regulator-ramp
235
236 regulator-stat
237 regula
238 regula
239 };
240 };
241
242 vdd_vdenc_s0: vdd_vden
243 regulator-name
244 regulator-alwa
245 regulator-boot
246 regulator-min-
247 regulator-max-
248 regulator-ramp
249
250 regulator-stat
251 regula
252 };
253 };
254
255 vdd_ddr_s0: dcdc-reg5
256 regulator-name
257 regulator-alwa
258 regulator-boot
259 regulator-min-
260 regulator-max-
261 regulator-ramp
262
263 regulator-stat
264 regula
265 regula
266 };
267 };
268
269 vdd2_ddr_s3: dcdc-reg6
270 regulator-name
271 regulator-alwa
272 regulator-boot
273
274 regulator-stat
275 regula
276 };
277 };
278
279 vcc_2v0_pldo_s3: dcdc-
280 regulator-name
281 regulator-alwa
282 regulator-boot
283 regulator-min-
284 regulator-max-
285 regulator-ramp
286
287 regulator-stat
288 regula
289 regula
290 };
291 };
292
293 vcc_3v3_s3: dcdc-reg8
294 regulator-name
295 regulator-alwa
296 regulator-boot
297 regulator-min-
298 regulator-max-
299
300 regulator-stat
301 regula
302 regula
303 };
304 };
305
306 vddq_ddr_s0: dcdc-reg9
307 regulator-name
308 regulator-alwa
309 regulator-boot
310
311 regulator-stat
312 regula
313 };
314 };
315
316 vcc_1v8_s3: dcdc-reg10
317 regulator-name
318 regulator-alwa
319 regulator-boot
320 regulator-min-
321 regulator-max-
322
323 regulator-stat
324 regula
325 regula
326 };
327 };
328
329 avcc_1v8_s0: pldo-reg1
330 regulator-name
331 regulator-alwa
332 regulator-boot
333 regulator-min-
334 regulator-max-
335
336 regulator-stat
337 regula
338 };
339 };
340
341 vcc_1v8_s0: pldo-reg2
342 regulator-name
343 regulator-alwa
344 regulator-boot
345 regulator-min-
346 regulator-max-
347
348 regulator-stat
349 regula
350 regula
351 };
352 };
353
354 avdd_1v2_s0: pldo-reg3
355 regulator-name
356 regulator-alwa
357 regulator-boot
358 regulator-min-
359 regulator-max-
360
361 regulator-stat
362 regula
363 };
364 };
365
366 vcc_3v3_s0: pldo-reg4
367 regulator-name
368 regulator-alwa
369 regulator-boot
370 regulator-min-
371 regulator-max-
372 regulator-ramp
373
374 regulator-stat
375 regula
376 };
377 };
378
379 vccio_sd_s0: pldo-reg5
380 regulator-name
381 regulator-alwa
382 regulator-boot
383 regulator-min-
384 regulator-max-
385 regulator-ramp
386
387 regulator-stat
388 regula
389 };
390 };
391
392 pldo6_s3: pldo-reg6 {
393 regulator-name
394 regulator-alwa
395 regulator-boot
396 regulator-min-
397 regulator-max-
398
399 regulator-stat
400 regula
401 regula
402 };
403 };
404
405 vdd_0v75_s3: nldo-reg1
406 regulator-name
407 regulator-alwa
408 regulator-boot
409 regulator-min-
410 regulator-max-
411
412 regulator-stat
413 regula
414 regula
415 };
416 };
417
418 vdd_ddr_pll_s0: nldo-r
419 regulator-name
420 regulator-alwa
421 regulator-boot
422 regulator-min-
423 regulator-max-
424
425 regulator-stat
426 regula
427 regula
428 };
429 };
430
431 avdd_0v75_s0: nldo-reg
432 regulator-name
433 regulator-alwa
434 regulator-boot
435 regulator-min-
436 regulator-max-
437
438 regulator-stat
439 regula
440 };
441 };
442
443 vdd_0v85_s0: nldo-reg4
444 regulator-name
445 regulator-alwa
446 regulator-boot
447 regulator-min-
448 regulator-max-
449
450 regulator-stat
451 regula
452 };
453 };
454
455 vdd_0v75_s0: nldo-reg5
456 regulator-name
457 regulator-alwa
458 regulator-boot
459 regulator-min-
460 regulator-max-
461
462 regulator-stat
463 regula
464 };
465 };
466 };
467 };
468 };
469
470 &tsadc {
471 status = "okay";
472 };
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