1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /*
3 * Copyright (c) 2021 Rockchip Electronics Co.
4 * Copyright (c) 2023 Thomas McKahan
5 * Copyright (c) 2024 Sebastian Kropatsch
6 *
7 */
8
9 /dts-v1/;
10
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/leds/common.h>
13 #include <dt-bindings/pinctrl/rockchip.h>
14 #include "rk3588.dtsi"
15
16 / {
17 model = "FriendlyElec CM3588";
18 compatible = "friendlyarm,cm3588", "ro
19
20 aliases {
21 mmc0 = &sdhci;
22 mmc1 = &sdmmc;
23 };
24
25 chosen {
26 stdout-path = "serial2:1500000
27 };
28
29 leds {
30 compatible = "gpio-leds";
31
32 led_sys: led-0 {
33 color = <LED_COLOR_ID_
34 function = LED_FUNCTIO
35 gpios = <&gpio2 RK_PC5
36 linux,default-trigger
37 pinctrl-names = "defau
38 pinctrl-0 = <&led_sys_
39 };
40
41 led_usr: led-1 {
42 color = <LED_COLOR_ID_
43 function = LED_FUNCTIO
44 gpios = <&gpio1 RK_PC6
45 pinctrl-names = "defau
46 pinctrl-0 = <&led_usr_
47 };
48 };
49
50 /* vcc_4v0_sys powers the RK806 and RK
51 vcc_4v0_sys: regulator-vcc-4v0-sys {
52 compatible = "regulator-fixed"
53 regulator-name = "vcc_4v0_sys"
54 regulator-always-on;
55 regulator-boot-on;
56 regulator-min-microvolt = <400
57 regulator-max-microvolt = <400
58 };
59
60 vcc_3v3_pcie20: regulator-vcc-3v3-pcie
61 compatible = "regulator-fixed"
62 regulator-name = "vcc_3v3_pcie
63 regulator-always-on;
64 regulator-boot-on;
65 regulator-min-microvolt = <330
66 regulator-max-microvolt = <330
67 vin-supply = <&vcc_3v3_s3>;
68 };
69
70 vcc_3v3_sd_s0: regulator-vcc-3v3-sd-s0
71 compatible = "regulator-fixed"
72 gpios = <&gpio4 RK_PA5 GPIO_AC
73 pinctrl-names = "default";
74 pinctrl-0 = <&sd_s0_pwr>;
75 regulator-boot-on;
76 regulator-max-microvolt = <330
77 regulator-min-microvolt = <330
78 regulator-name = "vcc_3v3_sd_s
79 vin-supply = <&vcc_3v3_s3>;
80 };
81
82 vcc_1v1_nldo_s3: regulator-vcc-1v1-nld
83 compatible = "regulator-fixed"
84 regulator-name = "vcc-1v1-nldo
85 regulator-always-on;
86 regulator-boot-on;
87 regulator-min-microvolt = <110
88 regulator-max-microvolt = <110
89 vin-supply = <&vcc_4v0_sys>;
90 };
91 };
92
93 /* Combo PHY 0 is configured to act as as PCIe
94 /* Used by PCIe controller 4 (pcie2x1l2) */
95 &combphy0_ps {
96 status = "okay";
97 };
98
99 &cpu_l0 {
100 cpu-supply = <&vdd_cpu_lit_s0>;
101 };
102
103 &cpu_l1 {
104 cpu-supply = <&vdd_cpu_lit_s0>;
105 };
106
107 &cpu_l2 {
108 cpu-supply = <&vdd_cpu_lit_s0>;
109 };
110
111 &cpu_l3 {
112 cpu-supply = <&vdd_cpu_lit_s0>;
113 };
114
115 &cpu_b0 {
116 cpu-supply = <&vdd_cpu_big0_s0>;
117 };
118
119 &cpu_b1 {
120 cpu-supply = <&vdd_cpu_big0_s0>;
121 };
122
123 &cpu_b2 {
124 cpu-supply = <&vdd_cpu_big1_s0>;
125 };
126
127 &cpu_b3 {
128 cpu-supply = <&vdd_cpu_big1_s0>;
129 };
130
131 &gpu {
132 mali-supply = <&vdd_gpu_s0>;
133 sram-supply = <&vdd_gpu_mem_s0>;
134 status = "okay";
135 };
136
137 &i2c0 {
138 pinctrl-names = "default";
139 pinctrl-0 = <&i2c0m2_xfer>;
140 status = "okay";
141
142 vdd_cpu_big0_s0: regulator@42 {
143 compatible = "rockchip,rk8602"
144 reg = <0x42>;
145 fcs,suspend-voltage-selector =
146 regulator-name = "vdd_cpu_big0
147 regulator-always-on;
148 regulator-boot-on;
149 regulator-min-microvolt = <550
150 regulator-max-microvolt = <105
151 regulator-ramp-delay = <2300>;
152 vin-supply = <&vcc_4v0_sys>;
153
154 regulator-state-mem {
155 regulator-off-in-suspe
156 };
157 };
158
159 vdd_cpu_big1_s0: regulator@43 {
160 compatible = "rockchip,rk8603"
161 reg = <0x43>;
162 fcs,suspend-voltage-selector =
163 regulator-name = "vdd_cpu_big1
164 regulator-always-on;
165 regulator-boot-on;
166 regulator-min-microvolt = <550
167 regulator-max-microvolt = <105
168 regulator-ramp-delay = <2300>;
169 vin-supply = <&vcc_4v0_sys>;
170
171 regulator-state-mem {
172 regulator-off-in-suspe
173 };
174 };
175 };
176
177 &i2c2 {
178 status = "okay";
179
180 vdd_npu_s0: regulator@42 {
181 compatible = "rockchip,rk8602"
182 reg = <0x42>;
183 fcs,suspend-voltage-selector =
184 regulator-name = "vdd_npu_s0";
185 regulator-always-on;
186 regulator-boot-on;
187 regulator-min-microvolt = <550
188 regulator-max-microvolt = <950
189 regulator-ramp-delay = <2300>;
190 vin-supply = <&vcc_4v0_sys>;
191
192 regulator-state-mem {
193 regulator-off-in-suspe
194 };
195 };
196 };
197
198 &i2c6 {
199 clock-frequency = <200000>;
200 pinctrl-names = "default";
201 pinctrl-0 = <&i2c6m0_xfer>;
202 status = "okay";
203
204 hym8563: rtc@51 {
205 compatible = "haoyu,hym8563";
206 reg = <0x51>;
207 #clock-cells = <0>;
208 clock-output-names = "hym8563"
209 interrupt-parent = <&gpio0>;
210 interrupts = <RK_PB0 IRQ_TYPE_
211 pinctrl-names = "default";
212 pinctrl-0 = <&hym8563_int>;
213 wakeup-source;
214 };
215 };
216
217 &i2c7 {
218 clock-frequency = <200000>;
219 status = "okay";
220
221 rt5616: audio-codec@1b {
222 compatible = "realtek,rt5616";
223 reg = <0x1b>;
224 #sound-dai-cells = <0>;
225 };
226 };
227
228 &i2s0_8ch {
229 pinctrl-names = "default";
230 pinctrl-0 = <&i2s0_lrck
231 &i2s0_mclk
232 &i2s0_sclk
233 &i2s0_sdi0
234 &i2s0_sdo0>;
235 status = "okay";
236 };
237
238 &i2s5_8ch {
239 status = "okay";
240 };
241
242 &i2s6_8ch {
243 status = "okay";
244 };
245
246 &i2s7_8ch {
247 status = "okay";
248 };
249
250 &pcie2x1l2 {
251 /* r8125 ethernet, @fe190000 */
252 pinctrl-names = "default";
253 pinctrl-0 = <&pcie2_2_rst>;
254 reset-gpios = <&gpio4 RK_PA4 GPIO_ACTI
255 vpcie3v3-supply = <&vcc_3v3_pcie20>;
256 status = "okay";
257 };
258
259 &pinctrl {
260 gpio-leds {
261 led_sys_pin: led-sys-pin {
262 rockchip,pins = <2 RK_
263 };
264
265 led_usr_pin: led-usr-pin {
266 rockchip,pins = <1 RK_
267 };
268 };
269
270 hym8563 {
271 hym8563_int: rtc-int {
272 rockchip,pins = <0 RK_
273 };
274 };
275
276 pcie {
277 pcie2_2_rst: pcie2-2-rst {
278 rockchip,pins = <4 RK_
279 };
280 };
281
282 sdmmc {
283 sd_s0_pwr: sd-s0-pwr {
284 rockchip,pins = <4 RK_
285 };
286 };
287 };
288
289 &saradc {
290 vref-supply = <&avcc_1v8_s0>;
291 status = "okay";
292 };
293
294 /* eMMC */
295 &sdhci {
296 bus-width = <8>;
297 mmc-hs400-1_8v;
298 mmc-hs400-enhanced-strobe;
299 no-sd;
300 no-sdio;
301 non-removable;
302 vmmc-supply = <&vcc_3v3_s3>;
303 vqmmc-supply = <&vcc_1v8_s3>;
304 status = "okay";
305 };
306
307 /* microSD card */
308 &sdmmc {
309 bus-width = <4>;
310 cap-sd-highspeed;
311 disable-wp;
312 max-frequency = <150000000>;
313 no-mmc;
314 no-sdio;
315 sd-uhs-sdr104;
316 vmmc-supply = <&vcc_3v3_sd_s0>;
317 vqmmc-supply = <&vccio_sd_s0>;
318 };
319
320 &spi2 {
321 assigned-clocks = <&cru CLK_SPI2>;
322 assigned-clock-rates = <200000000>;
323 num-cs = <1>;
324 pinctrl-names = "default";
325 pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>
326 status = "okay";
327
328 rk806_single: pmic@0 {
329 compatible = "rockchip,rk806";
330 reg = <0x0>;
331
332 interrupt-parent = <&gpio0>;
333 interrupts = <7 IRQ_TYPE_LEVEL
334
335 pinctrl-names = "default";
336 pinctrl-0 = <&pmic_pins>, <&rk
337 <&rk806_dvs2_null>
338
339 spi-max-frequency = <1000000>;
340 system-power-controller;
341
342 vcc1-supply = <&vcc_4v0_sys>;
343 vcc2-supply = <&vcc_4v0_sys>;
344 vcc3-supply = <&vcc_4v0_sys>;
345 vcc4-supply = <&vcc_4v0_sys>;
346 vcc5-supply = <&vcc_4v0_sys>;
347 vcc6-supply = <&vcc_4v0_sys>;
348 vcc7-supply = <&vcc_4v0_sys>;
349 vcc8-supply = <&vcc_4v0_sys>;
350 vcc9-supply = <&vcc_4v0_sys>;
351 vcc10-supply = <&vcc_4v0_sys>;
352 vcc11-supply = <&vcc_2v0_pldo_
353 vcc12-supply = <&vcc_4v0_sys>;
354 vcc13-supply = <&vcc_1v1_nldo_
355 vcc14-supply = <&vcc_1v1_nldo_
356 vcca-supply = <&vcc_4v0_sys>;
357
358 gpio-controller;
359 #gpio-cells = <2>;
360
361 rk806_dvs1_null: dvs1-null-pin
362 pins = "gpio_pwrctrl1"
363 function = "pin_fun0";
364 };
365
366 rk806_dvs2_null: dvs2-null-pin
367 pins = "gpio_pwrctrl2"
368 function = "pin_fun0";
369 };
370
371 rk806_dvs3_null: dvs3-null-pin
372 pins = "gpio_pwrctrl3"
373 function = "pin_fun0";
374 };
375
376 regulators {
377 vdd_gpu_s0: vdd_gpu_me
378 regulator-boot
379 regulator-min-
380 regulator-max-
381 regulator-ramp
382 regulator-name
383 regulator-enab
384
385 regulator-stat
386 regula
387 };
388 };
389
390 vdd_cpu_lit_s0: vdd_cp
391 regulator-alwa
392 regulator-boot
393 regulator-min-
394 regulator-max-
395 regulator-ramp
396 regulator-name
397
398 regulator-stat
399 regula
400 };
401 };
402
403 vdd_log_s0: dcdc-reg3
404 regulator-alwa
405 regulator-boot
406 regulator-min-
407 regulator-max-
408 regulator-ramp
409 regulator-name
410
411 regulator-stat
412 regula
413 regula
414 };
415 };
416
417 vdd_vdenc_s0: vdd_vden
418 regulator-alwa
419 regulator-boot
420 regulator-min-
421 regulator-max-
422 regulator-ramp
423 regulator-name
424
425 regulator-stat
426 regula
427 };
428 };
429
430 vdd_ddr_s0: dcdc-reg5
431 regulator-alwa
432 regulator-boot
433 regulator-min-
434 regulator-max-
435 regulator-ramp
436 regulator-name
437
438 regulator-stat
439 regula
440 regula
441 };
442 };
443
444 vdd2_ddr_s3: dcdc-reg6
445 regulator-alwa
446 regulator-boot
447 regulator-name
448
449 regulator-stat
450 regula
451 };
452 };
453
454 vcc_2v0_pldo_s3: dcdc-
455 regulator-alwa
456 regulator-boot
457 regulator-min-
458 regulator-max-
459 regulator-ramp
460 regulator-name
461
462 regulator-stat
463 regula
464 regula
465 };
466 };
467
468 vcc_3v3_s3: dcdc-reg8
469 regulator-alwa
470 regulator-boot
471 regulator-min-
472 regulator-max-
473 regulator-name
474
475 regulator-stat
476 regula
477 regula
478 };
479 };
480
481 vddq_ddr_s0: dcdc-reg9
482 regulator-alwa
483 regulator-boot
484 regulator-name
485
486 regulator-stat
487 regula
488 };
489 };
490
491 vcc_1v8_s3: dcdc-reg10
492 regulator-alwa
493 regulator-boot
494 regulator-min-
495 regulator-max-
496 regulator-name
497
498 regulator-stat
499 regula
500 regula
501 };
502 };
503
504 avcc_1v8_s0: pldo-reg1
505 regulator-alwa
506 regulator-boot
507 regulator-min-
508 regulator-max-
509 regulator-name
510
511 regulator-stat
512 regula
513 };
514 };
515
516 vcc_1v8_s0: pldo-reg2
517 regulator-alwa
518 regulator-boot
519 regulator-min-
520 regulator-max-
521 regulator-name
522
523 regulator-stat
524 regula
525 regula
526 };
527 };
528
529 avdd_1v2_s0: pldo-reg3
530 regulator-alwa
531 regulator-boot
532 regulator-min-
533 regulator-max-
534 regulator-name
535
536 regulator-stat
537 regula
538 };
539 };
540
541 vcc_3v3_s0: pldo-reg4
542 regulator-alwa
543 regulator-boot
544 regulator-min-
545 regulator-max-
546 regulator-ramp
547 regulator-name
548
549 regulator-stat
550 regula
551 };
552 };
553
554 vccio_sd_s0: pldo-reg5
555 regulator-alwa
556 regulator-boot
557 regulator-min-
558 regulator-max-
559 regulator-ramp
560 regulator-name
561
562 regulator-stat
563 regula
564 };
565 };
566
567 pldo6_s3: pldo-reg6 {
568 regulator-alwa
569 regulator-boot
570 regulator-min-
571 regulator-max-
572 regulator-name
573
574 regulator-stat
575 regula
576 regula
577 };
578 };
579
580 vdd_0v75_s3: nldo-reg1
581 regulator-alwa
582 regulator-boot
583 regulator-min-
584 regulator-max-
585 regulator-name
586
587 regulator-stat
588 regula
589 regula
590 };
591 };
592
593 vdd_ddr_pll_s0: nldo-r
594 regulator-alwa
595 regulator-boot
596 regulator-min-
597 regulator-max-
598 regulator-name
599
600 regulator-stat
601 regula
602 regula
603 };
604 };
605
606 avdd_0v75_s0: nldo-reg
607 regulator-alwa
608 regulator-boot
609 regulator-min-
610 regulator-max-
611 regulator-name
612
613 regulator-stat
614 regula
615 };
616 };
617
618 vdd_0v85_s0: nldo-reg4
619 regulator-alwa
620 regulator-boot
621 regulator-min-
622 regulator-max-
623 regulator-name
624
625 regulator-stat
626 regula
627 };
628 };
629
630 vdd_0v75_s0: nldo-reg5
631 regulator-alwa
632 regulator-boot
633 regulator-min-
634 regulator-max-
635 regulator-name
636
637 regulator-stat
638 regula
639 };
640 };
641 };
642 };
643 };
644
645 &tsadc {
646 status = "okay";
647 };
648
649 /* Debug UART */
650 &uart2 {
651 pinctrl-names = "default";
652 pinctrl-0 = <&uart2m0_xfer>;
653 };
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