1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /*
3 * Copyright (c) 2021 Rockchip Electronics Co.
4 * Copyright (c) 2023 Thomas McKahan
5 *
6 */
7
8 /dts-v1/;
9
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/input/input.h>
12 #include <dt-bindings/pinctrl/rockchip.h>
13 #include <dt-bindings/usb/pd.h>
14 #include "rk3588.dtsi"
15
16 / {
17 model = "FriendlyElec NanoPC-T6";
18 compatible = "friendlyarm,nanopc-t6",
19
20 aliases {
21 mmc0 = &sdhci;
22 mmc1 = &sdmmc;
23 };
24
25 adc-keys-0 {
26 compatible = "adc-keys";
27 io-channels = <&saradc 0>;
28 io-channel-names = "buttons";
29 keyup-threshold-microvolt = <1
30 poll-interval = <100>;
31
32 button-maskrom {
33 label = "Mask Rom";
34 linux,code = <KEY_SETU
35 press-threshold-microv
36 };
37 };
38
39 chosen {
40 stdout-path = "serial2:1500000
41 };
42
43 ir-receiver {
44 compatible = "gpio-ir-receiver
45 gpios = <&gpio0 RK_PD4 GPIO_AC
46 pinctrl-names = "default";
47 pinctrl-0 = <&ir_receiver_pin>
48 };
49
50 leds {
51 compatible = "gpio-leds";
52
53 sys_led: led-0 {
54 gpios = <&gpio2 RK_PB7
55 label = "system-led";
56 linux,default-trigger
57 pinctrl-names = "defau
58 pinctrl-0 = <&sys_led_
59 };
60
61 usr_led: led-1 {
62 gpios = <&gpio2 RK_PC0
63 label = "user-led";
64 pinctrl-names = "defau
65 pinctrl-0 = <&usr_led_
66 };
67 };
68
69 sound {
70 compatible = "simple-audio-car
71 pinctrl-names = "default";
72 pinctrl-0 = <&hp_det>;
73
74 simple-audio-card,name = "real
75 simple-audio-card,format = "i2
76 simple-audio-card,mclk-fs = <2
77
78 simple-audio-card,hp-det-gpio
79
80 simple-audio-card,widgets =
81 "Headphone", "Headphon
82 "Microphone", "Microph
83 simple-audio-card,routing =
84 "Headphones", "HPOL",
85 "Headphones", "HPOR",
86 "MIC1", "Microphone Ja
87 "Microphone Jack", "mi
88
89 simple-audio-card,cpu {
90 sound-dai = <&i2s0_8ch
91 };
92 simple-audio-card,codec {
93 sound-dai = <&rt5616>;
94 };
95 };
96
97 vcc12v_dcin: vcc12v-dcin-regulator {
98 compatible = "regulator-fixed"
99 regulator-name = "vcc12v_dcin"
100 regulator-always-on;
101 regulator-boot-on;
102 regulator-min-microvolt = <120
103 regulator-max-microvolt = <120
104 };
105
106 /* vcc5v0_sys powers peripherals */
107 vcc5v0_sys: vcc5v0-sys-regulator {
108 compatible = "regulator-fixed"
109 regulator-name = "vcc5v0_sys";
110 regulator-always-on;
111 regulator-boot-on;
112 regulator-min-microvolt = <500
113 regulator-max-microvolt = <500
114 vin-supply = <&vcc12v_dcin>;
115 };
116
117 /* vcc4v0_sys powers the RK806, RK860'
118 vcc4v0_sys: vcc4v0-sys-regulator {
119 compatible = "regulator-fixed"
120 regulator-name = "vcc4v0_sys";
121 regulator-always-on;
122 regulator-boot-on;
123 regulator-min-microvolt = <400
124 regulator-max-microvolt = <400
125 vin-supply = <&vcc12v_dcin>;
126 };
127
128 vcc_1v1_nldo_s3: vcc-1v1-nldo-s3-regul
129 compatible = "regulator-fixed"
130 regulator-name = "vcc-1v1-nldo
131 regulator-always-on;
132 regulator-boot-on;
133 regulator-min-microvolt = <110
134 regulator-max-microvolt = <110
135 vin-supply = <&vcc4v0_sys>;
136 };
137
138 vcc_3v3_pcie20: vcc3v3-pcie20-regulato
139 compatible = "regulator-fixed"
140 regulator-name = "vcc_3v3_pcie
141 regulator-always-on;
142 regulator-boot-on;
143 regulator-min-microvolt = <330
144 regulator-max-microvolt = <330
145 vin-supply = <&vcc_3v3_s3>;
146 };
147
148 vbus5v0_typec: vbus5v0-typec-regulator
149 compatible = "regulator-fixed"
150 enable-active-high;
151 gpio = <&gpio1 RK_PD2 GPIO_ACT
152 pinctrl-names = "default";
153 pinctrl-0 = <&typec5v_pwren>;
154 regulator-always-on;
155 regulator-boot-on;
156 regulator-name = "vbus5v0_type
157 regulator-min-microvolt = <500
158 regulator-max-microvolt = <500
159 vin-supply = <&vcc5v0_sys>;
160 };
161
162 vcc3v3_pcie2x1l0: vcc3v3-pcie2x1l0-reg
163 compatible = "regulator-fixed"
164 enable-active-high;
165 gpio = <&gpio4 RK_PC2 GPIO_ACT
166 pinctrl-names = "default";
167 pinctrl-0 = <&pcie_m2_1_pwren>
168 regulator-name = "vcc3v3_pcie2
169 regulator-min-microvolt = <330
170 regulator-max-microvolt = <330
171 vin-supply = <&vcc5v0_sys>;
172 };
173
174 vcc3v3_pcie30: vcc3v3-pcie30-regulator
175 compatible = "regulator-fixed"
176 enable-active-high;
177 gpios = <&gpio2 RK_PC5 GPIO_AC
178 pinctrl-names = "default";
179 pinctrl-0 = <&pcie_m2_0_pwren>
180 regulator-name = "vcc3v3_pcie3
181 regulator-min-microvolt = <330
182 regulator-max-microvolt = <330
183 vin-supply = <&vcc5v0_sys>;
184 };
185
186 vcc3v3_sd_s0: vcc3v3-sd-s0-regulator {
187 compatible = "regulator-fixed"
188 gpio = <&gpio4 RK_PA5 GPIO_ACT
189 regulator-boot-on;
190 regulator-max-microvolt = <330
191 regulator-min-microvolt = <330
192 regulator-name = "vcc3v3_sd_s0
193 vin-supply = <&vcc_3v3_s3>;
194 };
195 };
196
197 &combphy0_ps {
198 status = "okay";
199 };
200
201 &combphy1_ps {
202 status = "okay";
203 };
204
205 &combphy2_psu {
206 status = "okay";
207 };
208
209 &cpu_l0 {
210 cpu-supply = <&vdd_cpu_lit_s0>;
211 };
212
213 &cpu_l1 {
214 cpu-supply = <&vdd_cpu_lit_s0>;
215 };
216
217 &cpu_l2 {
218 cpu-supply = <&vdd_cpu_lit_s0>;
219 };
220
221 &cpu_l3 {
222 cpu-supply = <&vdd_cpu_lit_s0>;
223 };
224
225 &cpu_b0 {
226 cpu-supply = <&vdd_cpu_big0_s0>;
227 };
228
229 &cpu_b1 {
230 cpu-supply = <&vdd_cpu_big0_s0>;
231 };
232
233 &cpu_b2 {
234 cpu-supply = <&vdd_cpu_big1_s0>;
235 };
236
237 &cpu_b3 {
238 cpu-supply = <&vdd_cpu_big1_s0>;
239 };
240
241 &gpio0 {
242 gpio-line-names = /* GPIO0 A0-A7 */
243 "", "", "", "",
244 "", "", "", "",
245 /* GPIO0 B0-B7 */
246 "", "", "", "",
247 "", "", "", "",
248 /* GPIO0 C0-C7 */
249 "", "", "", "",
250 "HEADER_10", "HEADER
251 /* GPIO0 D0-D7 */
252 "", "", "", "",
253 "IR receiver [PWM3_I
254 };
255
256 &gpio1 {
257 gpio-line-names = /* GPIO1 A0-A7 */
258 "HEADER_27", "HEADER
259 "", "", "", "HEADER_
260 /* GPIO1 B0-B7 */
261 "HEADER_26", "HEADER
262 "HEADER_24", "HEADER
263 /* GPIO1 C0-C7 */
264 "", "", "", "",
265 "", "", "", "",
266 /* GPIO1 D0-D7 */
267 "", "", "", "",
268 "", "", "HEADER_05",
269 };
270
271 &gpio2 {
272 gpio-line-names = /* GPIO2 A0-A7 */
273 "", "", "", "",
274 "", "", "", "",
275 /* GPIO2 B0-B7 */
276 "", "", "", "",
277 "", "", "", "",
278 /* GPIO2 C0-C7 */
279 "", "CSI1_11", "CSI1
280 "", "", "", "",
281 /* GPIO2 D0-D7 */
282 "", "", "", "",
283 "", "", "", "";
284 };
285
286 &gpio3 {
287 gpio-line-names = /* GPIO3 A0-A7 */
288 "HEADER_35", "HEADER
289 "HEADER_37", "", "DS
290 /* GPIO3 B0-B7 */
291 "HEADER_33", "DSI0_1
292 "HEADER_18", "HEADER
293 /* GPIO3 C0-C7 */
294 "DSI0_08", "DSI0_14"
295 "", "", "", "",
296 /* GPIO3 D0-D7 */
297 "", "", "", "",
298 "", "DSI1_10", "", "
299 };
300
301 &gpio4 {
302 gpio-line-names = /* GPIO4 A0-A7 */
303 "DSI1_08", "DSI1_14"
304 "", "", "", "",
305 /* GPIO4 B0-B7 */
306 "", "", "", "",
307 "", "", "", "",
308 /* GPIO4 C0-C7 */
309 "", "", "", "",
310 "CSI0_11", "CSI0_12"
311 /* GPIO4 D0-D7 */
312 "", "", "", "",
313 "", "", "", "";
314 };
315
316 &gpu {
317 mali-supply = <&vdd_gpu_s0>;
318 status = "okay";
319 };
320
321 &i2c0 {
322 pinctrl-names = "default";
323 pinctrl-0 = <&i2c0m2_xfer>;
324 status = "okay";
325
326 vdd_cpu_big0_s0: regulator@42 {
327 compatible = "rockchip,rk8602"
328 reg = <0x42>;
329 fcs,suspend-voltage-selector =
330 regulator-name = "vdd_cpu_big0
331 regulator-always-on;
332 regulator-boot-on;
333 regulator-min-microvolt = <550
334 regulator-max-microvolt = <105
335 regulator-ramp-delay = <2300>;
336 vin-supply = <&vcc4v0_sys>;
337
338 regulator-state-mem {
339 regulator-off-in-suspe
340 };
341 };
342
343 vdd_cpu_big1_s0: regulator@43 {
344 compatible = "rockchip,rk8603"
345 reg = <0x43>;
346 fcs,suspend-voltage-selector =
347 regulator-name = "vdd_cpu_big1
348 regulator-always-on;
349 regulator-boot-on;
350 regulator-min-microvolt = <550
351 regulator-max-microvolt = <105
352 regulator-ramp-delay = <2300>;
353 vin-supply = <&vcc4v0_sys>;
354
355 regulator-state-mem {
356 regulator-off-in-suspe
357 };
358 };
359 };
360
361 &i2c2 {
362 status = "okay";
363
364 vdd_npu_s0: regulator@42 {
365 compatible = "rockchip,rk8602"
366 reg = <0x42>;
367 fcs,suspend-voltage-selector =
368 regulator-name = "vdd_npu_s0";
369 regulator-always-on;
370 regulator-boot-on;
371 regulator-min-microvolt = <550
372 regulator-max-microvolt = <950
373 regulator-ramp-delay = <2300>;
374 vin-supply = <&vcc4v0_sys>;
375
376 regulator-state-mem {
377 regulator-off-in-suspe
378 };
379 };
380 };
381
382 &i2c6 {
383 clock-frequency = <200000>;
384 status = "okay";
385
386 fusb302: typec-portc@22 {
387 compatible = "fcs,fusb302";
388 reg = <0x22>;
389 interrupt-parent = <&gpio0>;
390 interrupts = <RK_PD3 IRQ_TYPE_
391 pinctrl-0 = <&usbc0_int>;
392 pinctrl-names = "default";
393 vbus-supply = <&vbus5v0_typec>
394
395 connector {
396 compatible = "usb-c-co
397 data-role = "dual";
398 label = "USB-C";
399 power-role = "source";
400 source-pdos = <PDO_FIX
401
402 ports {
403 #address-cells
404 #size-cells =
405
406 port@0 {
407 reg =
408 usbc0_
409
410 };
411 };
412
413 port@1 {
414 reg =
415 usbc0_
416
417 };
418 };
419
420 port@2 {
421 reg =
422 usbc0_
423
424 };
425 };
426 };
427 };
428 };
429
430 hym8563: rtc@51 {
431 compatible = "haoyu,hym8563";
432 reg = <0x51>;
433 #clock-cells = <0>;
434 clock-output-names = "hym8563"
435 pinctrl-names = "default";
436 pinctrl-0 = <&hym8563_int>;
437 interrupt-parent = <&gpio0>;
438 interrupts = <RK_PB0 IRQ_TYPE_
439 wakeup-source;
440 };
441 };
442
443 &i2c7 {
444 clock-frequency = <200000>;
445 status = "okay";
446
447 rt5616: codec@1b {
448 compatible = "realtek,rt5616";
449 reg = <0x1b>;
450 clocks = <&cru I2S0_8CH_MCLKOU
451 clock-names = "mclk";
452 #sound-dai-cells = <0>;
453 assigned-clocks = <&cru I2S0_8
454 assigned-clock-rates = <122880
455
456 port {
457 rt5616_p0_0: endpoint
458 remote-endpoin
459 };
460 };
461 };
462
463 /* connected with MIPI-CSI1 */
464 };
465
466 &i2c8 {
467 pinctrl-0 = <&i2c8m2_xfer>;
468 };
469
470 &i2s0_8ch {
471 pinctrl-names = "default";
472 pinctrl-0 = <&i2s0_lrck
473 &i2s0_mclk
474 &i2s0_sclk
475 &i2s0_sdi0
476 &i2s0_sdo0>;
477 status = "okay";
478
479 i2s0_8ch_p0: port {
480 i2s0_8ch_p0_0: endpoint {
481 dai-format = "i2s";
482 mclk-fs = <256>;
483 remote-endpoint = <&rt
484 };
485 };
486 };
487
488 &pcie2x1l0 {
489 reset-gpios = <&gpio4 RK_PB3 GPIO_ACTI
490 vpcie3v3-supply = <&vcc_3v3_pcie20>;
491 pinctrl-names = "default";
492 pinctrl-0 = <&pcie2_0_rst>;
493 status = "okay";
494 };
495
496 &pcie2x1l1 {
497 reset-gpios = <&gpio4 RK_PA2 GPIO_ACTI
498 vpcie3v3-supply = <&vcc3v3_pcie2x1l0>;
499 pinctrl-names = "default";
500 pinctrl-0 = <&pcie2_1_rst>;
501 status = "okay";
502 };
503
504 &pcie2x1l2 {
505 reset-gpios = <&gpio4 RK_PA4 GPIO_ACTI
506 vpcie3v3-supply = <&vcc_3v3_pcie20>;
507 pinctrl-names = "default";
508 pinctrl-0 = <&pcie2_2_rst>;
509 status = "okay";
510 };
511
512 &pcie30phy {
513 status = "okay";
514 };
515
516 &pcie3x4 {
517 reset-gpios = <&gpio4 RK_PB6 GPIO_ACTI
518 vpcie3v3-supply = <&vcc3v3_pcie30>;
519 status = "okay";
520 };
521
522 &pinctrl {
523 gpio-leds {
524 sys_led_pin: sys-led-pin {
525 rockchip,pins = <2 RK_
526 };
527
528 usr_led_pin: usr-led-pin {
529 rockchip,pins = <2 RK_
530 };
531 };
532
533 headphone {
534 hp_det: hp-det {
535 rockchip,pins = <1 RK_
536 };
537 };
538
539 hym8563 {
540 hym8563_int: hym8563-int {
541 rockchip,pins = <0 RK_
542 };
543 };
544
545 ir-receiver {
546 ir_receiver_pin: ir-receiver-p
547 rockchip,pins = <0 RK_
548 };
549 };
550
551 pcie {
552 pcie2_0_rst: pcie2-0-rst {
553 rockchip,pins = <4 RK_
554 };
555
556 pcie2_1_rst: pcie2-1-rst {
557 rockchip,pins = <4 RK_
558 };
559
560 pcie2_2_rst: pcie2-2-rst {
561 rockchip,pins = <4 RK_
562 };
563
564 pcie_m2_0_pwren: pcie-m20-pwre
565 rockchip,pins = <2 RK_
566 };
567
568 pcie_m2_1_pwren: pcie-m21-pwre
569 rockchip,pins = <4 RK_
570 };
571 };
572
573 usb {
574 typec5v_pwren: typec5v-pwren {
575 rockchip,pins = <1 RK_
576 };
577
578 usbc0_int: usbc0-int {
579 rockchip,pins = <0 RK_
580 };
581 };
582 };
583
584 &pwm1 {
585 pinctrl-0 = <&pwm1m1_pins>;
586 status = "okay";
587 };
588
589 &saradc {
590 vref-supply = <&avcc_1v8_s0>;
591 status = "okay";
592 };
593
594 &sdhci {
595 bus-width = <8>;
596 no-sdio;
597 no-sd;
598 non-removable;
599 max-frequency = <200000000>;
600 mmc-hs400-1_8v;
601 mmc-hs400-enhanced-strobe;
602 status = "okay";
603 };
604
605 &sdmmc {
606 bus-width = <4>;
607 cap-mmc-highspeed;
608 cap-sd-highspeed;
609 cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_
610 disable-wp;
611 no-mmc;
612 no-sdio;
613 sd-uhs-sdr104;
614 vmmc-supply = <&vcc3v3_sd_s0>;
615 vqmmc-supply = <&vccio_sd_s0>;
616 status = "okay";
617 };
618
619 /* optional on non-LTS, populated on LTS versi
620 &sfc {
621 pinctrl-names = "default";
622 pinctrl-0 = <&fspim1_pins>;
623 status = "okay";
624
625 flash@0 {
626 compatible = "jedec,spi-nor";
627 reg = <0>;
628 spi-max-frequency = <104000000
629 spi-rx-bus-width = <4>;
630 spi-tx-bus-width = <1>;
631 };
632 };
633
634 &spi2 {
635 status = "okay";
636 assigned-clocks = <&cru CLK_SPI2>;
637 assigned-clock-rates = <200000000>;
638 pinctrl-names = "default";
639 pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>
640 num-cs = <1>;
641
642 pmic@0 {
643 compatible = "rockchip,rk806";
644 spi-max-frequency = <1000000>;
645 reg = <0x0>;
646
647 interrupt-parent = <&gpio0>;
648 interrupts = <7 IRQ_TYPE_LEVEL
649
650 pinctrl-names = "default";
651 pinctrl-0 = <&pmic_pins>, <&rk
652 <&rk806_dvs2_null>
653
654 system-power-controller;
655
656 vcc1-supply = <&vcc4v0_sys>;
657 vcc2-supply = <&vcc4v0_sys>;
658 vcc3-supply = <&vcc4v0_sys>;
659 vcc4-supply = <&vcc4v0_sys>;
660 vcc5-supply = <&vcc4v0_sys>;
661 vcc6-supply = <&vcc4v0_sys>;
662 vcc7-supply = <&vcc4v0_sys>;
663 vcc8-supply = <&vcc4v0_sys>;
664 vcc9-supply = <&vcc4v0_sys>;
665 vcc10-supply = <&vcc4v0_sys>;
666 vcc11-supply = <&vcc_2v0_pldo_
667 vcc12-supply = <&vcc4v0_sys>;
668 vcc13-supply = <&vcc_1v1_nldo_
669 vcc14-supply = <&vcc_1v1_nldo_
670 vcca-supply = <&vcc4v0_sys>;
671
672 gpio-controller;
673 #gpio-cells = <2>;
674
675 rk806_dvs1_null: dvs1-null-pin
676 pins = "gpio_pwrctrl1"
677 function = "pin_fun0";
678 };
679
680 rk806_dvs2_null: dvs2-null-pin
681 pins = "gpio_pwrctrl2"
682 function = "pin_fun0";
683 };
684
685 rk806_dvs3_null: dvs3-null-pin
686 pins = "gpio_pwrctrl3"
687 function = "pin_fun0";
688 };
689
690 regulators {
691 vdd_gpu_s0: vdd_gpu_me
692 regulator-boot
693 regulator-min-
694 regulator-max-
695 regulator-ramp
696 regulator-name
697 regulator-enab
698
699 regulator-stat
700 regula
701 };
702 };
703
704 vdd_cpu_lit_s0: vdd_cp
705 regulator-alwa
706 regulator-boot
707 regulator-min-
708 regulator-max-
709 regulator-ramp
710 regulator-name
711
712 regulator-stat
713 regula
714 };
715 };
716
717 vdd_log_s0: dcdc-reg3
718 regulator-alwa
719 regulator-boot
720 regulator-min-
721 regulator-max-
722 regulator-ramp
723 regulator-name
724
725 regulator-stat
726 regula
727 regula
728 };
729 };
730
731 vdd_vdenc_s0: vdd_vden
732 regulator-alwa
733 regulator-boot
734 regulator-min-
735 regulator-max-
736 regulator-ramp
737 regulator-name
738
739 regulator-stat
740 regula
741 };
742 };
743
744 vdd_ddr_s0: dcdc-reg5
745 regulator-alwa
746 regulator-boot
747 regulator-min-
748 regulator-max-
749 regulator-ramp
750 regulator-name
751
752 regulator-stat
753 regula
754 regula
755 };
756 };
757
758 vdd2_ddr_s3: dcdc-reg6
759 regulator-alwa
760 regulator-boot
761 regulator-name
762
763 regulator-stat
764 regula
765 };
766 };
767
768 vcc_2v0_pldo_s3: dcdc-
769 regulator-alwa
770 regulator-boot
771 regulator-min-
772 regulator-max-
773 regulator-ramp
774 regulator-name
775
776 regulator-stat
777 regula
778 regula
779 };
780 };
781
782 vcc_3v3_s3: dcdc-reg8
783 regulator-alwa
784 regulator-boot
785 regulator-min-
786 regulator-max-
787 regulator-name
788
789 regulator-stat
790 regula
791 regula
792 };
793 };
794
795 vddq_ddr_s0: dcdc-reg9
796 regulator-alwa
797 regulator-boot
798 regulator-name
799
800 regulator-stat
801 regula
802 };
803 };
804
805 vcc_1v8_s3: dcdc-reg10
806 regulator-alwa
807 regulator-boot
808 regulator-min-
809 regulator-max-
810 regulator-name
811
812 regulator-stat
813 regula
814 regula
815 };
816 };
817
818 avcc_1v8_s0: pldo-reg1
819 regulator-alwa
820 regulator-boot
821 regulator-min-
822 regulator-max-
823 regulator-name
824
825 regulator-stat
826 regula
827 };
828 };
829
830 vcc_1v8_s0: pldo-reg2
831 regulator-alwa
832 regulator-boot
833 regulator-min-
834 regulator-max-
835 regulator-name
836
837 regulator-stat
838 regula
839 regula
840 };
841 };
842
843 avdd_1v2_s0: pldo-reg3
844 regulator-alwa
845 regulator-boot
846 regulator-min-
847 regulator-max-
848 regulator-name
849
850 regulator-stat
851 regula
852 };
853 };
854
855 vcc_3v3_s0: pldo-reg4
856 regulator-alwa
857 regulator-boot
858 regulator-min-
859 regulator-max-
860 regulator-ramp
861 regulator-name
862
863 regulator-stat
864 regula
865 };
866 };
867
868 vccio_sd_s0: pldo-reg5
869 regulator-alwa
870 regulator-boot
871 regulator-min-
872 regulator-max-
873 regulator-ramp
874 regulator-name
875
876 regulator-stat
877 regula
878 };
879 };
880
881 pldo6_s3: pldo-reg6 {
882 regulator-alwa
883 regulator-boot
884 regulator-min-
885 regulator-max-
886 regulator-name
887
888 regulator-stat
889 regula
890 regula
891 };
892 };
893
894 vdd_0v75_s3: nldo-reg1
895 regulator-alwa
896 regulator-boot
897 regulator-min-
898 regulator-max-
899 regulator-name
900
901 regulator-stat
902 regula
903 regula
904 };
905 };
906
907 vdd_ddr_pll_s0: nldo-r
908 regulator-alwa
909 regulator-boot
910 regulator-min-
911 regulator-max-
912 regulator-name
913
914 regulator-stat
915 regula
916 regula
917 };
918 };
919
920 avdd_0v75_s0: nldo-reg
921 regulator-alwa
922 regulator-boot
923 regulator-min-
924 regulator-max-
925 regulator-name
926
927 regulator-stat
928 regula
929 };
930 };
931
932 vdd_0v85_s0: nldo-reg4
933 regulator-alwa
934 regulator-boot
935 regulator-min-
936 regulator-max-
937 regulator-name
938
939 regulator-stat
940 regula
941 };
942 };
943
944 vdd_0v75_s0: nldo-reg5
945 regulator-alwa
946 regulator-boot
947 regulator-min-
948 regulator-max-
949 regulator-name
950
951 regulator-stat
952 regula
953 };
954 };
955 };
956 };
957 };
958
959 &tsadc {
960 status = "okay";
961 };
962
963 &uart2 {
964 pinctrl-0 = <&uart2m0_xfer>;
965 status = "okay";
966 };
967
968 &u2phy0 {
969 status = "okay";
970 };
971
972 &u2phy0_otg {
973 status = "okay";
974 };
975
976 &u2phy2_host {
977 status = "okay";
978 };
979
980 &u2phy3_host {
981 status = "okay";
982 };
983
984 &u2phy2 {
985 status = "okay";
986 };
987
988 &u2phy3 {
989 status = "okay";
990 };
991
992 &usbdp_phy0 {
993 mode-switch;
994 orientation-switch;
995 sbu1-dc-gpios = <&gpio4 RK_PA6 GPIO_AC
996 sbu2-dc-gpios = <&gpio4 RK_PA7 GPIO_AC
997 status = "okay";
998
999 port {
1000 #address-cells = <1>;
1001 #size-cells = <0>;
1002
1003 usbdp_phy0_typec_ss: endpoint
1004 reg = <0>;
1005 remote-endpoint = <&u
1006 };
1007
1008 usbdp_phy0_typec_sbu: endpoin
1009 reg = <1>;
1010 remote-endpoint = <&u
1011 };
1012 };
1013 };
1014
1015 &usb_host0_ehci {
1016 status = "okay";
1017 };
1018
1019 &usb_host0_ohci {
1020 status = "okay";
1021 };
1022
1023 &usb_host0_xhci {
1024 dr_mode = "host";
1025 status = "okay";
1026 usb-role-switch;
1027
1028 port {
1029 usb_host0_xhci_drd_sw: endpoi
1030 remote-endpoint = <&u
1031 };
1032 };
1033 };
1034
1035 &usb_host1_ehci {
1036 status = "okay";
1037 };
1038
1039 &usb_host1_ohci {
1040 status = "okay";
1041 };
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