1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /*
3 * Copyright (c) 2023 Theobroma Systems Design
4 */
5
6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/leds/common.h>
8 #include <dt-bindings/pinctrl/rockchip.h>
9 #include "rk3588.dtsi"
10
11 / {
12 compatible = "tsd,rk3588-tiger", "rock
13
14 aliases {
15 mmc0 = &sdhci;
16 rtc0 = &rtc_twi;
17 };
18
19 emmc_pwrseq: emmc-pwrseq {
20 compatible = "mmc-pwrseq-emmc"
21 pinctrl-0 = <&emmc_reset>;
22 pinctrl-names = "default";
23 reset-gpios = <&gpio2 RK_PA3 G
24 };
25
26 extcon_usb3: extcon-usb3 {
27 compatible = "linux,extcon-usb
28 id-gpios = <&gpio3 RK_PC0 GPIO
29 pinctrl-names = "default";
30 pinctrl-0 = <&usb3_id>;
31 status = "disabled";
32 };
33
34 leds {
35 compatible = "gpio-leds";
36 pinctrl-names = "default";
37 pinctrl-0 = <&module_led_pin>;
38
39 /* Named LED1 on the board */
40 led-1 {
41 gpios = <&gpio1 RK_PD3
42 function = LED_FUNCTIO
43 linux,default-trigger
44 color = <LED_COLOR_ID_
45 };
46 };
47
48 /*
49 * 100MHz reference clock for PCIe per
50 * clock generator.
51 * The clock output is gated via the O
52 * This is modeled as a fixed-clock pl
53 */
54 pcie_refclk_gen: pcie-refclk-gen-clock
55 compatible = "fixed-clock";
56 #clock-cells = <0>;
57 clock-frequency = <100000000>;
58 };
59
60 pcie_refclk: pcie-refclk-clock {
61 compatible = "gpio-gate-clock"
62 clocks = <&pcie_refclk_gen>;
63 #clock-cells = <0>;
64 enable-gpios = <&gpio4 RK_PB4
65 };
66
67 vcc_1v1_nldo_s3: vcc-1v1-nldo-s3-regul
68 compatible = "regulator-fixed"
69 regulator-name = "vcc_1v1_nldo
70 regulator-always-on;
71 regulator-boot-on;
72 regulator-min-microvolt = <110
73 regulator-max-microvolt = <110
74 vin-supply = <&vcc5v0_sys>;
75 };
76
77 vcc_1v2_s3: vcc-1v2-s3-regulator {
78 compatible = "regulator-fixed"
79 regulator-name = "vcc_1v2_s3";
80 regulator-always-on;
81 regulator-boot-on;
82 regulator-min-microvolt = <120
83 regulator-max-microvolt = <120
84 vin-supply = <&vcc5v0_sys>;
85 };
86
87 vcc5v0_sys: vcc5v0-sys-regulator {
88 compatible = "regulator-fixed"
89 regulator-name = "vcc5v0_sys";
90 regulator-always-on;
91 regulator-boot-on;
92 regulator-min-microvolt = <500
93 regulator-max-microvolt = <500
94 vin-supply = <&vcc5v0_baseboar
95 };
96 };
97
98 &cpu_b0 {
99 cpu-supply = <&vdd_cpu_big0_s0>;
100 };
101
102 &cpu_b1 {
103 cpu-supply = <&vdd_cpu_big0_s0>;
104 };
105
106 &cpu_b2 {
107 cpu-supply = <&vdd_cpu_big1_s0>;
108 };
109
110 &cpu_b3 {
111 cpu-supply = <&vdd_cpu_big1_s0>;
112 };
113
114 &cpu_l0 {
115 cpu-supply = <&vdd_cpu_lit_s0>;
116 };
117
118 &cpu_l1 {
119 cpu-supply = <&vdd_cpu_lit_s0>;
120 };
121
122 &cpu_l2 {
123 cpu-supply = <&vdd_cpu_lit_s0>;
124 };
125
126 &cpu_l3 {
127 cpu-supply = <&vdd_cpu_lit_s0>;
128 };
129
130 &gmac0 {
131 clock_in_out = "output";
132 phy-handle = <&rgmii_phy>;
133 phy-mode = "rgmii";
134 phy-supply = <&vcc_1v2_s3>;
135 pinctrl-names = "default";
136 pinctrl-0 = <&gmac0_miim
137 &gmac0_rx_bus2
138 &gmac0_tx_bus2
139 &gmac0_rgmii_clk
140 &gmac0_rgmii_bus
141 ð0_pins
142 ð_reset>;
143 tx_delay = <0x10>;
144 rx_delay = <0x10>;
145 snps,reset-gpio = <&gpio4 RK_PC3 GPIO_
146 snps,reset-active-low;
147 snps,reset-delays-us = <0 10000 100000
148 };
149
150 &gpu {
151 mali-supply = <&vdd_gpu_s0>;
152 status = "okay";
153 };
154
155 &i2c1 {
156 pinctrl-0 = <&i2c1m0_xfer>;
157 };
158
159 &i2c1m0_xfer {
160 rockchip,pins =
161 /* i2c1_scl_m0 */
162 <0 RK_PB5 9 &pcfg_pull_none_dr
163 /* i2c1_sda_m0 */
164 <0 RK_PB6 9 &pcfg_pull_none_dr
165 };
166
167 &i2c2 {
168 pinctrl-0 = <&i2c2m3_xfer>;
169 status = "okay";
170 };
171
172 &i2c2m3_xfer {
173 rockchip,pins =
174 /* i2c2_scl_m3 */
175 <1 RK_PC5 9 &pcfg_pull_none_dr
176 /* i2c2_sda_m3 */
177 <1 RK_PC4 9 &pcfg_pull_none_dr
178 };
179
180 &i2c3 {
181 pinctrl-0 = <&i2c3m0_xfer>;
182 };
183
184 &i2c4 {
185 pinctrl-0 = <&i2c4m4_xfer>;
186 status = "okay";
187
188 vdd_npu_s0: regulator@42 {
189 compatible = "rockchip,rk8602"
190 reg = <0x42>;
191 fcs,suspend-voltage-selector =
192 regulator-name = "vdd_npu_s0";
193 regulator-always-on;
194 regulator-boot-on;
195 regulator-min-microvolt = <550
196 regulator-max-microvolt = <950
197 regulator-ramp-delay = <2300>;
198 vin-supply = <&vcc5v0_sys>;
199
200 regulator-state-mem {
201 regulator-off-in-suspe
202 };
203 };
204 };
205
206 &i2c5 {
207 pinctrl-0 = <&i2c5m1_xfer>;
208 };
209
210 &i2c5m1_xfer {
211 rockchip,pins =
212 /* i2c5_scl_m1 */
213 <4 RK_PB6 9 &pcfg_pull_none_dr
214 /* i2c5_sda_m1 */
215 <4 RK_PB7 9 &pcfg_pull_none_dr
216 };
217
218 &i2c6 {
219 /*
220 * Mule-ATtiny can handle up to Fast m
221 * but SOC can handle only up to (400k
222 */
223 clock-frequency = <400000>;
224 status = "okay";
225
226 fan@18 {
227 compatible = "ti,amc6821";
228 reg = <0x18>;
229 };
230
231 rtc_twi: rtc@6f {
232 compatible = "isil,isl1208";
233 reg = <0x6f>;
234 };
235 };
236
237 &i2c6m0_xfer {
238 rockchip,pins =
239 /* i2c6_scl_m0 */
240 <0 RK_PD0 9 &pcfg_pull_none_dr
241 /* i2c6_sda_m0 */
242 <0 RK_PC7 9 &pcfg_pull_none_dr
243 };
244
245 &i2c7 {
246 status = "okay";
247
248 vdd_cpu_big0_s0: regulator@42 {
249 compatible = "rockchip,rk8602"
250 reg = <0x42>;
251 fcs,suspend-voltage-selector =
252 regulator-name = "vdd_cpu_big0
253 regulator-always-on;
254 regulator-boot-on;
255 regulator-min-microvolt = <550
256 regulator-max-microvolt = <105
257 regulator-ramp-delay = <2300>;
258 vin-supply = <&vcc5v0_sys>;
259
260 regulator-state-mem {
261 regulator-off-in-suspe
262 };
263 };
264
265 vdd_cpu_big1_s0: regulator@43 {
266 compatible = "rockchip,rk8603"
267 reg = <0x43>;
268 fcs,suspend-voltage-selector =
269 regulator-name = "vdd_cpu_big1
270 regulator-always-on;
271 regulator-boot-on;
272 regulator-min-microvolt = <550
273 regulator-max-microvolt = <105
274 regulator-ramp-delay = <2300>;
275 vin-supply = <&vcc5v0_sys>;
276
277 regulator-state-mem {
278 regulator-off-in-suspe
279 };
280 };
281 };
282
283 &i2c7m0_xfer {
284 rockchip,pins =
285 /* i2c7_scl_m0 */
286 <1 RK_PD0 9 &pcfg_pull_none_dr
287 /* i2c7_sda_m0 */
288 <1 RK_PD1 9 &pcfg_pull_none_dr
289 };
290
291 &i2c8 {
292 pinctrl-0 = <&i2c8m2_xfer>;
293 };
294
295 &mdio0 {
296 rgmii_phy: ethernet-phy@6 {
297 /* KSZ9031 or KSZ9131 */
298 compatible = "ethernet-phy-iee
299 reg = <0x6>;
300 clocks = <&cru REFCLKO25M_ETH0
301 };
302 };
303
304 &pcie3x4 {
305 /*
306 * The board has a gpio-controlled "pc
307 * so add it to the list of clocks.
308 */
309 clocks = <&cru ACLK_PCIE_4L_MSTR>, <&c
310 <&cru ACLK_PCIE_4L_DBI>, <&cr
311 <&cru CLK_PCIE_AUX0>, <&cru C
312 <&pcie_refclk>;
313 clock-names = "aclk_mst", "aclk_slv",
314 "aclk_dbi", "pclk",
315 "aux", "pipe",
316 "ref";
317 reset-gpios = <&gpio3 RK_PB6 GPIO_ACTI
318 };
319
320 &pinctrl {
321 emmc {
322 emmc_reset: emmc-reset {
323 rockchip,pins = <2 RK_
324 };
325 };
326
327 ethernet {
328 eth_reset: eth-reset {
329 rockchip,pins = <4 RK_
330 };
331 };
332
333 leds {
334 module_led_pin: module-led-pin
335 rockchip,pins = <1 RK_
336 };
337 };
338
339 usb3 {
340 usb3_id: usb3-id {
341 rockchip,pins =
342 <3 RK_PC0 RK_FUNC_GP
343 };
344 };
345 };
346
347 &pwm0 {
348 pinctrl-0 = <&pwm0m1_pins>;
349 pinctrl-names = "default";
350 };
351
352 &saradc {
353 vref-supply = <&vcc_1v8_s0>;
354 status = "okay";
355 };
356
357 &sdhci {
358 bus-width = <8>;
359 cap-mmc-highspeed;
360 mmc-ddr-1_8v;
361 mmc-hs200-1_8v;
362 mmc-hs400-1_8v;
363 mmc-hs400-enhanced-strobe;
364 mmc-pwrseq = <&emmc_pwrseq>;
365 no-sdio;
366 no-sd;
367 non-removable;
368 pinctrl-names = "default";
369 pinctrl-0 = <&emmc_bus8 &emmc_cmd &emm
370 supports-cqe;
371 vmmc-supply = <&vcc_3v3_s3>;
372 vqmmc-supply = <&vcc_1v8_s3>;
373 status = "okay";
374 };
375
376 &sdmmc {
377 bus-width = <4>;
378 cap-sd-highspeed;
379 max-frequency = <150000000>;
380 vqmmc-supply = <&vccio_sd_s0>;
381 };
382
383 &spi0 {
384 pinctrl-0 = <&spi0m1_cs0 &spi0m1_cs1 &
385 };
386
387 &spi2 {
388 assigned-clocks = <&cru CLK_SPI2>;
389 assigned-clock-rates = <200000000>;
390 num-cs = <1>;
391 pinctrl-names = "default";
392 pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>
393 status = "okay";
394
395 pmic@0 {
396 compatible = "rockchip,rk806";
397 reg = <0x0>;
398 interrupt-parent = <&gpio0>;
399 interrupts = <7 IRQ_TYPE_LEVEL
400 gpio-controller;
401 #gpio-cells = <2>;
402 pinctrl-names = "default";
403 pinctrl-0 = <&pmic_pins>, <&rk
404 <&rk806_dvs2_null>
405 spi-max-frequency = <1000000>;
406 system-power-controller;
407 vcc1-supply = <&vcc5v0_sys>;
408 vcc2-supply = <&vcc5v0_sys>;
409 vcc3-supply = <&vcc5v0_sys>;
410 vcc4-supply = <&vcc5v0_sys>;
411 vcc5-supply = <&vcc5v0_sys>;
412 vcc6-supply = <&vcc5v0_sys>;
413 vcc7-supply = <&vcc5v0_sys>;
414 vcc8-supply = <&vcc5v0_sys>;
415 vcc9-supply = <&vcc5v0_sys>;
416 vcc10-supply = <&vcc5v0_sys>;
417 vcc11-supply = <&vcc_2v0_pldo_
418 vcc12-supply = <&vcc5v0_sys>;
419 vcc13-supply = <&vcc_1v1_nldo_
420 vcc14-supply = <&vcc_1v1_nldo_
421 vcca-supply = <&vcc5v0_sys>;
422
423 rk806_dvs1_null: dvs1-null-pin
424 pins = "gpio_pwrctrl1"
425 function = "pin_fun0";
426 };
427
428 rk806_dvs2_null: dvs2-null-pin
429 pins = "gpio_pwrctrl2"
430 function = "pin_fun0";
431 };
432
433 rk806_dvs3_null: dvs3-null-pin
434 pins = "gpio_pwrctrl3"
435 function = "pin_fun0";
436 };
437
438 regulators {
439 vdd_gpu_s0: dcdc-reg1
440 regulator-boot
441 regulator-min-
442 regulator-max-
443 regulator-ramp
444 regulator-name
445 regulator-enab
446
447 regulator-stat
448 regula
449 };
450 };
451
452 vdd_cpu_lit_s0: dcdc-r
453 regulator-name
454 regulator-alwa
455 regulator-boot
456 regulator-min-
457 regulator-max-
458 regulator-ramp
459
460 regulator-stat
461 regula
462 };
463 };
464
465 vdd_log_s0: dcdc-reg3
466 regulator-name
467 regulator-alwa
468 regulator-boot
469 regulator-min-
470 regulator-max-
471 regulator-ramp
472
473 regulator-stat
474 regula
475 regula
476 };
477 };
478
479 vdd_vdenc_s0: dcdc-reg
480 regulator-name
481 regulator-alwa
482 regulator-boot
483 regulator-min-
484 regulator-max-
485 regulator-ramp
486
487 regulator-stat
488 regula
489 };
490 };
491
492 vdd_ddr_s0: dcdc-reg5
493 regulator-name
494 regulator-alwa
495 regulator-boot
496 regulator-min-
497 regulator-max-
498 regulator-ramp
499
500 regulator-stat
501 regula
502 regula
503 };
504 };
505
506 vdd2_ddr_s3: dcdc-reg6
507 regulator-name
508 regulator-alwa
509 regulator-boot
510
511 regulator-stat
512 regula
513 };
514 };
515
516 vcc_2v0_pldo_s3: dcdc-
517 regulator-name
518 regulator-alwa
519 regulator-boot
520 regulator-min-
521 regulator-max-
522 regulator-ramp
523
524 regulator-stat
525 regula
526 regula
527 };
528 };
529
530 vcc_3v3_s3: dcdc-reg8
531 regulator-name
532 regulator-alwa
533 regulator-boot
534 regulator-min-
535 regulator-max-
536
537 regulator-stat
538 regula
539 regula
540 };
541 };
542
543 vddq_ddr_s0: dcdc-reg9
544 regulator-name
545 regulator-alwa
546 regulator-boot
547
548 regulator-stat
549 regula
550 };
551 };
552
553 vcc_1v8_s3: dcdc-reg10
554 regulator-name
555 regulator-alwa
556 regulator-boot
557 regulator-min-
558 regulator-max-
559
560 regulator-stat
561 regula
562 regula
563 };
564 };
565
566 vcca_1v8_s0: pldo-reg1
567 regulator-name
568 regulator-alwa
569 regulator-boot
570 regulator-min-
571 regulator-max-
572
573 regulator-stat
574 regula
575 };
576 };
577
578 vcc_1v8_s0: pldo-reg2
579 regulator-name
580 regulator-alwa
581 regulator-boot
582 regulator-min-
583 regulator-max-
584
585 regulator-stat
586 regula
587 regula
588 };
589 };
590
591 vdda_1v2_s0: pldo-reg3
592 regulator-name
593 regulator-alwa
594 regulator-boot
595 regulator-min-
596 regulator-max-
597
598 regulator-stat
599 regula
600 };
601 };
602
603 vcca_3v3_s0: pldo-reg4
604 regulator-name
605 regulator-alwa
606 regulator-boot
607 regulator-min-
608 regulator-max-
609 regulator-ramp
610
611 regulator-stat
612 regula
613 };
614 };
615
616 vccio_sd_s0: pldo-reg5
617 regulator-name
618 regulator-alwa
619 regulator-boot
620 regulator-min-
621 regulator-max-
622 regulator-ramp
623
624 regulator-stat
625 regula
626 };
627 };
628
629 pldo6_s3: pldo-reg6 {
630 regulator-name
631 regulator-alwa
632 regulator-boot
633 regulator-min-
634 regulator-max-
635
636 regulator-stat
637 regula
638 regula
639 };
640 };
641
642 vdd_0v75_s3: nldo-reg1
643 regulator-name
644 regulator-alwa
645 regulator-boot
646 regulator-min-
647 regulator-max-
648
649 regulator-stat
650 regula
651 regula
652 };
653 };
654
655 vdda_ddr_pll_s0: nldo-
656 regulator-name
657 regulator-alwa
658 regulator-boot
659 regulator-min-
660 regulator-max-
661
662 regulator-stat
663 regula
664 regula
665 };
666 };
667
668 vdda_0v75_s0: nldo-reg
669 regulator-name
670 regulator-alwa
671 regulator-boot
672 regulator-min-
673 regulator-max-
674
675 regulator-stat
676 regula
677 };
678 };
679
680 vdda_0v85_s0: nldo-reg
681 regulator-name
682 regulator-alwa
683 regulator-boot
684 regulator-min-
685 regulator-max-
686
687 regulator-stat
688 regula
689 };
690 };
691
692 vdd_0v75_s0: nldo-reg5
693 regulator-name
694 regulator-alwa
695 regulator-boot
696 regulator-min-
697 regulator-max-
698
699 regulator-stat
700 regula
701 };
702 };
703 };
704 };
705 };
706
707 &tsadc {
708 status = "okay";
709 };
710
711 /* Routed to UART0 on the Q7 connector */
712 &uart2 {
713 pinctrl-0 = <&uart2m2_xfer>;
714 };
715
716 /* Mule-ATtiny UPDI */
717 &uart4 {
718 pinctrl-0 = <&uart4m2_xfer>;
719 status = "okay";
720 };
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