1 // SPDX-License-Identifier: (GPL-2.0-only OR M <<
2 /* 1 /*
3 * Spreadtrum SC9836 SoC DTS file 2 * Spreadtrum SC9836 SoC DTS file
4 * 3 *
5 * Copyright (C) 2014, Spreadtrum Communicatio 4 * Copyright (C) 2014, Spreadtrum Communications Inc.
>> 5 *
>> 6 * This file is licensed under a dual GPLv2 or X11 license.
6 */ 7 */
7 8
8 #include "sharkl64.dtsi" 9 #include "sharkl64.dtsi"
9 #include <dt-bindings/interrupt-controller/arm 10 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 11
11 / { 12 / {
12 compatible = "sprd,sc9836"; 13 compatible = "sprd,sc9836";
13 14
14 cpus { 15 cpus {
15 #address-cells = <2>; 16 #address-cells = <2>;
16 #size-cells = <0>; 17 #size-cells = <0>;
17 18
18 cpu0: cpu@0 { 19 cpu0: cpu@0 {
19 device_type = "cpu"; 20 device_type = "cpu";
20 compatible = "arm,cort !! 21 compatible = "arm,cortex-a53", "arm,armv8";
21 reg = <0x0 0x0>; 22 reg = <0x0 0x0>;
22 enable-method = "psci" 23 enable-method = "psci";
23 }; 24 };
24 25
25 cpu1: cpu@1 { 26 cpu1: cpu@1 {
26 device_type = "cpu"; 27 device_type = "cpu";
27 compatible = "arm,cort !! 28 compatible = "arm,cortex-a53", "arm,armv8";
28 reg = <0x0 0x1>; 29 reg = <0x0 0x1>;
29 enable-method = "psci" 30 enable-method = "psci";
30 }; 31 };
31 32
32 cpu2: cpu@2 { 33 cpu2: cpu@2 {
33 device_type = "cpu"; 34 device_type = "cpu";
34 compatible = "arm,cort !! 35 compatible = "arm,cortex-a53", "arm,armv8";
35 reg = <0x0 0x2>; 36 reg = <0x0 0x2>;
36 enable-method = "psci" 37 enable-method = "psci";
37 }; 38 };
38 39
39 cpu3: cpu@3 { 40 cpu3: cpu@3 {
40 device_type = "cpu"; 41 device_type = "cpu";
41 compatible = "arm,cort !! 42 compatible = "arm,cortex-a53", "arm,armv8";
42 reg = <0x0 0x3>; 43 reg = <0x0 0x3>;
43 enable-method = "psci" 44 enable-method = "psci";
44 }; 45 };
45 }; 46 };
46 47
47 etf@10003000 { 48 etf@10003000 {
48 compatible = "arm,coresight-tm 49 compatible = "arm,coresight-tmc", "arm,primecell";
49 reg = <0 0x10003000 0 0x1000>; 50 reg = <0 0x10003000 0 0x1000>;
50 clocks = <&clk26mhz>; 51 clocks = <&clk26mhz>;
51 clock-names = "apb_pclk"; 52 clock-names = "apb_pclk";
52 in-ports { !! 53 port {
53 port { !! 54 etf_in: endpoint {
54 etf_in: endpoi !! 55 slave-mode;
55 remote !! 56 remote-endpoint = <&funnel_out_port0>;
56 }; <<
57 }; 57 };
58 }; 58 };
59 }; 59 };
60 60
61 funnel@10001000 { 61 funnel@10001000 {
62 compatible = "arm,coresight-dy !! 62 compatible = "arm,coresight-funnel", "arm,primecell";
63 reg = <0 0x10001000 0 0x1000>; 63 reg = <0 0x10001000 0 0x1000>;
64 clocks = <&clk26mhz>; 64 clocks = <&clk26mhz>;
65 clock-names = "apb_pclk"; 65 clock-names = "apb_pclk";
>> 66 ports {
>> 67 #address-cells = <1>;
>> 68 #size-cells = <0>;
66 69
67 out-ports { !! 70 /* funnel output port */
68 port { !! 71 port@0 {
>> 72 reg = <0>;
69 funnel_out_por 73 funnel_out_port0: endpoint {
70 remote 74 remote-endpoint = <&etf_in>;
71 }; 75 };
72 }; 76 };
73 }; <<
74 <<
75 in-ports { <<
76 #address-cells = <1>; <<
77 #size-cells = <0>; <<
78 77
79 port@0 { !! 78 /* funnel input port 0-4 */
>> 79 port@1 {
80 reg = <0>; 80 reg = <0>;
81 funnel_in_port 81 funnel_in_port0: endpoint {
>> 82 slave-mode;
82 remote 83 remote-endpoint = <&etm0_out>;
83 }; 84 };
84 }; 85 };
85 86
86 port@1 { !! 87 port@2 {
87 reg = <1>; 88 reg = <1>;
88 funnel_in_port 89 funnel_in_port1: endpoint {
>> 90 slave-mode;
89 remote 91 remote-endpoint = <&etm1_out>;
90 }; 92 };
91 }; 93 };
92 94
93 port@2 { !! 95 port@3 {
94 reg = <2>; 96 reg = <2>;
95 funnel_in_port 97 funnel_in_port2: endpoint {
>> 98 slave-mode;
96 remote 99 remote-endpoint = <&etm2_out>;
97 }; 100 };
98 }; 101 };
99 102
100 port@3 { !! 103 port@4 {
101 reg = <3>; 104 reg = <3>;
102 funnel_in_port 105 funnel_in_port3: endpoint {
>> 106 slave-mode;
103 remote 107 remote-endpoint = <&etm3_out>;
104 }; 108 };
105 }; 109 };
106 110
107 port@4 { !! 111 port@5 {
108 reg = <4>; 112 reg = <4>;
109 funnel_in_port 113 funnel_in_port4: endpoint {
>> 114 slave-mode;
110 remote 115 remote-endpoint = <&stm_out>;
111 }; 116 };
112 }; 117 };
113 /* Other input ports a 118 /* Other input ports aren't connected to anyone */
114 }; 119 };
115 }; 120 };
116 121
117 etm@10440000 { 122 etm@10440000 {
118 compatible = "arm,coresight-et 123 compatible = "arm,coresight-etm4x", "arm,primecell";
119 reg = <0 0x10440000 0 0x1000>; 124 reg = <0 0x10440000 0 0x1000>;
120 125
121 cpu = <&cpu0>; 126 cpu = <&cpu0>;
122 clocks = <&clk26mhz>; 127 clocks = <&clk26mhz>;
123 clock-names = "apb_pclk"; 128 clock-names = "apb_pclk";
124 out-ports { !! 129 port {
125 port { !! 130 etm0_out: endpoint {
126 etm0_out: endp !! 131 remote-endpoint = <&funnel_in_port0>;
127 remote <<
128 }; <<
129 }; 132 };
130 }; 133 };
131 }; 134 };
132 135
133 etm@10540000 { 136 etm@10540000 {
134 compatible = "arm,coresight-et 137 compatible = "arm,coresight-etm4x", "arm,primecell";
135 reg = <0 0x10540000 0 0x1000>; 138 reg = <0 0x10540000 0 0x1000>;
136 139
137 cpu = <&cpu1>; 140 cpu = <&cpu1>;
138 clocks = <&clk26mhz>; 141 clocks = <&clk26mhz>;
139 clock-names = "apb_pclk"; 142 clock-names = "apb_pclk";
140 out-ports { !! 143 port {
141 port { !! 144 etm1_out: endpoint {
142 etm1_out: endp !! 145 remote-endpoint = <&funnel_in_port1>;
143 remote <<
144 }; <<
145 }; 146 };
146 }; 147 };
147 }; 148 };
148 149
149 etm@10640000 { 150 etm@10640000 {
150 compatible = "arm,coresight-et 151 compatible = "arm,coresight-etm4x", "arm,primecell";
151 reg = <0 0x10640000 0 0x1000>; 152 reg = <0 0x10640000 0 0x1000>;
152 153
153 cpu = <&cpu2>; 154 cpu = <&cpu2>;
154 clocks = <&clk26mhz>; 155 clocks = <&clk26mhz>;
155 clock-names = "apb_pclk"; 156 clock-names = "apb_pclk";
156 out-ports { !! 157 port {
157 port { !! 158 etm2_out: endpoint {
158 etm2_out: endp !! 159 remote-endpoint = <&funnel_in_port2>;
159 remote <<
160 }; <<
161 }; 160 };
162 }; 161 };
163 }; 162 };
164 163
165 etm@10740000 { 164 etm@10740000 {
166 compatible = "arm,coresight-et 165 compatible = "arm,coresight-etm4x", "arm,primecell";
167 reg = <0 0x10740000 0 0x1000>; 166 reg = <0 0x10740000 0 0x1000>;
168 167
169 cpu = <&cpu3>; 168 cpu = <&cpu3>;
170 clocks = <&clk26mhz>; 169 clocks = <&clk26mhz>;
171 clock-names = "apb_pclk"; 170 clock-names = "apb_pclk";
172 out-ports { !! 171 port {
173 port { !! 172 etm3_out: endpoint {
174 etm3_out: endp !! 173 remote-endpoint = <&funnel_in_port3>;
175 remote <<
176 }; <<
177 }; 174 };
178 }; 175 };
179 }; 176 };
180 177
181 stm@10006000 { 178 stm@10006000 {
182 compatible = "arm,coresight-st 179 compatible = "arm,coresight-stm", "arm,primecell";
183 reg = <0 0x10006000 0 0x1000>, 180 reg = <0 0x10006000 0 0x1000>,
184 <0 0x01000000 0 0x180000 181 <0 0x01000000 0 0x180000>;
185 reg-names = "stm-base", "stm-s 182 reg-names = "stm-base", "stm-stimulus-base";
186 clocks = <&clk26mhz>; 183 clocks = <&clk26mhz>;
187 clock-names = "apb_pclk"; 184 clock-names = "apb_pclk";
188 out-ports { !! 185 port {
189 port { !! 186 stm_out: endpoint {
190 stm_out: endpo !! 187 remote-endpoint = <&funnel_in_port4>;
191 remote <<
192 }; <<
193 }; 188 };
194 }; 189 };
195 }; 190 };
196 191
197 gic: interrupt-controller@12001000 { 192 gic: interrupt-controller@12001000 {
198 compatible = "arm,gic-400"; 193 compatible = "arm,gic-400";
199 reg = <0 0x12001000 0 0x1000>, 194 reg = <0 0x12001000 0 0x1000>,
200 <0 0x12002000 0 0x2000>, 195 <0 0x12002000 0 0x2000>,
201 <0 0x12004000 0 0x2000>, 196 <0 0x12004000 0 0x2000>,
202 <0 0x12006000 0 0x2000>; 197 <0 0x12006000 0 0x2000>;
203 #interrupt-cells = <3>; 198 #interrupt-cells = <3>;
204 interrupt-controller; 199 interrupt-controller;
205 interrupts = <GIC_PPI 9 (GIC_C 200 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
206 }; 201 };
207 202
208 psci { 203 psci {
209 compatible = "arm,psci"; !! 204 compatible = "arm,psci";
210 method = "smc"; !! 205 method = "smc";
211 cpu_on = <0xc4000003>; !! 206 cpu_on = <0xc4000003>;
212 cpu_off = <0x84000002>; !! 207 cpu_off = <0x84000002>;
213 cpu_suspend = <0xc4000001>; !! 208 cpu_suspend = <0xc4000001>;
214 }; 209 };
215 210
216 timer { 211 timer {
217 compatible = "arm,armv8-timer" 212 compatible = "arm,armv8-timer";
218 interrupts = <GIC_PPI 13 (GIC_ 213 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
219 <GIC_PPI 14 (GIC_ 214 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
220 <GIC_PPI 11 (GIC_ 215 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
221 <GIC_PPI 10 (GIC_ 216 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
222 }; 217 };
223 }; 218 };
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