1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) <<
2 /* 1 /*
3 * Spreadtrum SC9860 SoC 2 * Spreadtrum SC9860 SoC
4 * 3 *
5 * Copyright (C) 2016, Spreadtrum Communicatio 4 * Copyright (C) 2016, Spreadtrum Communications Inc.
>> 5 *
>> 6 * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 */ 7 */
7 8
8 #include <dt-bindings/interrupt-controller/arm 9 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/input/input.h> <<
10 #include <dt-bindings/gpio/gpio.h> <<
11 #include "whale2.dtsi" 10 #include "whale2.dtsi"
12 11
13 / { 12 / {
14 cpus { 13 cpus {
15 #address-cells = <2>; 14 #address-cells = <2>;
16 #size-cells = <0>; 15 #size-cells = <0>;
17 16
18 cpu-map { 17 cpu-map {
19 cluster0 { 18 cluster0 {
20 core0 { 19 core0 {
21 cpu = 20 cpu = <&CPU0>;
22 }; 21 };
23 core1 { 22 core1 {
24 cpu = 23 cpu = <&CPU1>;
25 }; 24 };
26 core2 { 25 core2 {
27 cpu = 26 cpu = <&CPU2>;
28 }; 27 };
29 core3 { 28 core3 {
30 cpu = 29 cpu = <&CPU3>;
31 }; 30 };
32 }; 31 };
33 32
34 cluster1 { 33 cluster1 {
35 core0 { 34 core0 {
36 cpu = 35 cpu = <&CPU4>;
37 }; 36 };
38 core1 { 37 core1 {
39 cpu = 38 cpu = <&CPU5>;
40 }; 39 };
41 core2 { 40 core2 {
42 cpu = 41 cpu = <&CPU6>;
43 }; 42 };
44 core3 { 43 core3 {
45 cpu = 44 cpu = <&CPU7>;
46 }; 45 };
47 }; 46 };
48 }; 47 };
49 48
50 CPU0: cpu@530000 { 49 CPU0: cpu@530000 {
51 device_type = "cpu"; 50 device_type = "cpu";
52 compatible = "arm,cort !! 51 compatible = "arm,cortex-a53", "arm,armv8";
53 reg = <0x0 0x530000>; 52 reg = <0x0 0x530000>;
54 enable-method = "psci" 53 enable-method = "psci";
55 cpu-idle-states = <&CO 54 cpu-idle-states = <&CORE_PD &CLUSTER_PD>;
56 }; 55 };
57 56
58 CPU1: cpu@530001 { 57 CPU1: cpu@530001 {
59 device_type = "cpu"; 58 device_type = "cpu";
60 compatible = "arm,cort !! 59 compatible = "arm,cortex-a53", "arm,armv8";
61 reg = <0x0 0x530001>; 60 reg = <0x0 0x530001>;
62 enable-method = "psci" 61 enable-method = "psci";
63 cpu-idle-states = <&CO 62 cpu-idle-states = <&CORE_PD &CLUSTER_PD>;
64 }; 63 };
65 64
66 CPU2: cpu@530002 { 65 CPU2: cpu@530002 {
67 device_type = "cpu"; 66 device_type = "cpu";
68 compatible = "arm,cort !! 67 compatible = "arm,cortex-a53", "arm,armv8";
69 reg = <0x0 0x530002>; 68 reg = <0x0 0x530002>;
70 enable-method = "psci" 69 enable-method = "psci";
71 cpu-idle-states = <&CO 70 cpu-idle-states = <&CORE_PD &CLUSTER_PD>;
72 }; 71 };
73 72
74 CPU3: cpu@530003 { 73 CPU3: cpu@530003 {
75 device_type = "cpu"; 74 device_type = "cpu";
76 compatible = "arm,cort !! 75 compatible = "arm,cortex-a53", "arm,armv8";
77 reg = <0x0 0x530003>; 76 reg = <0x0 0x530003>;
78 enable-method = "psci" 77 enable-method = "psci";
79 cpu-idle-states = <&CO 78 cpu-idle-states = <&CORE_PD &CLUSTER_PD>;
80 }; 79 };
81 80
82 CPU4: cpu@530100 { 81 CPU4: cpu@530100 {
83 device_type = "cpu"; 82 device_type = "cpu";
84 compatible = "arm,cort !! 83 compatible = "arm,cortex-a53", "arm,armv8";
85 reg = <0x0 0x530100>; 84 reg = <0x0 0x530100>;
86 enable-method = "psci" 85 enable-method = "psci";
87 cpu-idle-states = <&CO 86 cpu-idle-states = <&CORE_PD &CLUSTER_PD>;
88 }; 87 };
89 88
90 CPU5: cpu@530101 { 89 CPU5: cpu@530101 {
91 device_type = "cpu"; 90 device_type = "cpu";
92 compatible = "arm,cort !! 91 compatible = "arm,cortex-a53", "arm,armv8";
93 reg = <0x0 0x530101>; 92 reg = <0x0 0x530101>;
94 enable-method = "psci" 93 enable-method = "psci";
95 cpu-idle-states = <&CO 94 cpu-idle-states = <&CORE_PD &CLUSTER_PD>;
96 }; 95 };
97 96
98 CPU6: cpu@530102 { 97 CPU6: cpu@530102 {
99 device_type = "cpu"; 98 device_type = "cpu";
100 compatible = "arm,cort !! 99 compatible = "arm,cortex-a53", "arm,armv8";
101 reg = <0x0 0x530102>; 100 reg = <0x0 0x530102>;
102 enable-method = "psci" 101 enable-method = "psci";
103 cpu-idle-states = <&CO 102 cpu-idle-states = <&CORE_PD &CLUSTER_PD>;
104 }; 103 };
105 104
106 CPU7: cpu@530103 { 105 CPU7: cpu@530103 {
107 device_type = "cpu"; 106 device_type = "cpu";
108 compatible = "arm,cort !! 107 compatible = "arm,cortex-a53", "arm,armv8";
109 reg = <0x0 0x530103>; 108 reg = <0x0 0x530103>;
110 enable-method = "psci" 109 enable-method = "psci";
111 cpu-idle-states = <&CO 110 cpu-idle-states = <&CORE_PD &CLUSTER_PD>;
112 }; 111 };
113 }; 112 };
114 113
115 idle-states { !! 114 idle-states{
116 entry-method = "psci"; !! 115 entry-method = "arm,psci";
117 116
118 CORE_PD: core_pd { 117 CORE_PD: core_pd {
119 compatible = "arm,idle 118 compatible = "arm,idle-state";
120 entry-latency-us = <10 119 entry-latency-us = <1000>;
121 exit-latency-us = <700 120 exit-latency-us = <700>;
122 min-residency-us = <25 121 min-residency-us = <2500>;
123 local-timer-stop; 122 local-timer-stop;
124 arm,psci-suspend-param 123 arm,psci-suspend-param = <0x00010002>;
125 }; 124 };
126 125
127 CLUSTER_PD: cluster_pd { 126 CLUSTER_PD: cluster_pd {
128 compatible = "arm,idle 127 compatible = "arm,idle-state";
129 entry-latency-us = <10 128 entry-latency-us = <1000>;
130 exit-latency-us = <100 129 exit-latency-us = <1000>;
131 min-residency-us = <30 130 min-residency-us = <3000>;
132 local-timer-stop; 131 local-timer-stop;
133 arm,psci-suspend-param 132 arm,psci-suspend-param = <0x01010003>;
134 }; 133 };
135 }; 134 };
136 135
>> 136 gic: interrupt-controller@12001000 {
>> 137 compatible = "arm,gic-400";
>> 138 reg = <0 0x12001000 0 0x1000>,
>> 139 <0 0x12002000 0 0x2000>,
>> 140 <0 0x12004000 0 0x2000>,
>> 141 <0 0x12006000 0 0x2000>;
>> 142 #interrupt-cells = <3>;
>> 143 interrupt-controller;
>> 144 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8)
>> 145 | IRQ_TYPE_LEVEL_HIGH)>;
>> 146 };
>> 147
137 psci { 148 psci {
138 compatible = "arm,psci-0.2"; 149 compatible = "arm,psci-0.2";
139 method = "smc"; 150 method = "smc";
140 }; 151 };
141 152
142 timer { 153 timer {
143 compatible = "arm,armv8-timer" 154 compatible = "arm,armv8-timer";
144 interrupts = <GIC_PPI 13 (GIC_ 155 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8)
145 | IRQ 156 | IRQ_TYPE_LEVEL_LOW)>,
146 <GIC_PPI 14 (GIC_ 157 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8)
147 | IRQ 158 | IRQ_TYPE_LEVEL_LOW)>,
148 <GIC_PPI 11 (GIC_ 159 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8)
149 | IRQ 160 | IRQ_TYPE_LEVEL_LOW)>,
150 <GIC_PPI 10 (GIC_ 161 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8)
151 | IRQ 162 | IRQ_TYPE_LEVEL_LOW)>;
152 }; 163 };
153 164
154 pmu { 165 pmu {
155 compatible = "arm,cortex-a53-p !! 166 compatible = "arm,cortex-a53-pmu", "arm,armv8-pmuv3";
156 interrupts = <GIC_SPI 122 IRQ_ 167 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
157 <GIC_SPI 123 IRQ_ 168 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
158 <GIC_SPI 124 IRQ_ 169 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
159 <GIC_SPI 125 IRQ_ 170 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
160 <GIC_SPI 154 IRQ_ 171 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
161 <GIC_SPI 155 IRQ_ 172 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
162 <GIC_SPI 156 IRQ_ 173 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>,
163 <GIC_SPI 157 IRQ_ 174 <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
164 interrupt-affinity = <&CPU0>, 175 interrupt-affinity = <&CPU0>,
165 <&CPU1>, 176 <&CPU1>,
166 <&CPU2>, 177 <&CPU2>,
167 <&CPU3>, 178 <&CPU3>,
168 <&CPU4>, 179 <&CPU4>,
169 <&CPU5>, 180 <&CPU5>,
170 <&CPU6>, 181 <&CPU6>,
171 <&CPU7>; 182 <&CPU7>;
172 }; 183 };
173 184
174 soc { 185 soc {
175 gic: interrupt-controller@1200 <<
176 compatible = "arm,gic- <<
177 reg = <0 0x12001000 0 <<
178 <0 0x12002000 0 <<
179 <0 0x12004000 0 <<
180 <0 0x12006000 0 <<
181 #interrupt-cells = <3> <<
182 interrupt-controller; <<
183 interrupts = <GIC_PPI <<
184 <<
185 }; <<
186 <<
187 pmu_gate: pmu-gate { <<
188 compatible = "sprd,sc9 <<
189 sprd,syscon = <&pmu_re <<
190 clocks = <&ext_26m>; <<
191 #clock-cells = <1>; <<
192 }; <<
193 <<
194 pll: pll { <<
195 compatible = "sprd,sc9 <<
196 sprd,syscon = <&ana_re <<
197 clocks = <&pmu_gate 0> <<
198 #clock-cells = <1>; <<
199 }; <<
200 <<
201 ap_clk: clock-controller@20000 <<
202 compatible = "sprd,sc9 <<
203 reg = <0 0x20000000 0 <<
204 clocks = <&ext_26m>, < <<
205 <&pmu_gate 0> <<
206 #clock-cells = <1>; <<
207 }; <<
208 <<
209 aon_prediv: aon-prediv@402d000 <<
210 compatible = "sprd,sc9 <<
211 reg = <0 0x402d0000 0 <<
212 clocks = <&ext_26m>, < <<
213 <&pmu_gate 0> <<
214 #clock-cells = <1>; <<
215 }; <<
216 <<
217 apahb_gate: apahb-gate { <<
218 compatible = "sprd,sc9 <<
219 sprd,syscon = <&ap_ahb <<
220 clocks = <&aon_prediv <<
221 #clock-cells = <1>; <<
222 }; <<
223 <<
224 aon_gate: aon-gate { <<
225 compatible = "sprd,sc9 <<
226 sprd,syscon = <&aon_re <<
227 clocks = <&aon_prediv <<
228 #clock-cells = <1>; <<
229 }; <<
230 <<
231 aonsecure_clk: clock-controlle <<
232 compatible = "sprd,sc9 <<
233 reg = <0 0x40880000 0 <<
234 clocks = <&ext_26m>, < <<
235 #clock-cells = <1>; <<
236 }; <<
237 <<
238 agcp_gate: agcp-gate { <<
239 compatible = "sprd,sc9 <<
240 sprd,syscon = <&agcp_r <<
241 clocks = <&aon_prediv <<
242 #clock-cells = <1>; <<
243 }; <<
244 <<
245 gpu_clk: clock-controller@6020 <<
246 compatible = "sprd,sc9 <<
247 reg = <0 0x60200000 0 <<
248 clocks = <&pll 0>; <<
249 #clock-cells = <1>; <<
250 }; <<
251 <<
252 vsp_clk: clock-controller@6100 <<
253 compatible = "sprd,sc9 <<
254 reg = <0 0x61000000 0 <<
255 clocks = <&ext_26m>, < <<
256 #clock-cells = <1>; <<
257 }; <<
258 <<
259 vsp_gate: vsp-gate { <<
260 compatible = "sprd,sc9 <<
261 sprd,syscon = <&vsp_re <<
262 clocks = <&vsp_clk 0>; <<
263 #clock-cells = <1>; <<
264 }; <<
265 <<
266 cam_clk: clock-controller@6200 <<
267 compatible = "sprd,sc9 <<
268 reg = <0 0x62000000 0 <<
269 clocks = <&ext_26m>, < <<
270 #clock-cells = <1>; <<
271 }; <<
272 <<
273 cam_gate: cam-gate { <<
274 compatible = "sprd,sc9 <<
275 sprd,syscon = <&cam_re <<
276 clocks = <&cam_clk 0>; <<
277 #clock-cells = <1>; <<
278 }; <<
279 <<
280 disp_clk: clock-controller@630 <<
281 compatible = "sprd,sc9 <<
282 reg = <0 0x63000000 0 <<
283 clocks = <&ext_26m>, < <<
284 #clock-cells = <1>; <<
285 }; <<
286 <<
287 disp_gate: disp-gate { <<
288 compatible = "sprd,sc9 <<
289 sprd,syscon = <&disp_r <<
290 clocks = <&disp_clk 0> <<
291 #clock-cells = <1>; <<
292 }; <<
293 <<
294 apapb_gate: apapb-gate { <<
295 compatible = "sprd,sc9 <<
296 sprd,syscon = <&ap_apb <<
297 clocks = <&ap_clk 0>; <<
298 #clock-cells = <1>; <<
299 }; <<
300 <<
301 funnel@10001000 { /* SoC Funne 186 funnel@10001000 { /* SoC Funnel */
302 compatible = "arm,core !! 187 compatible = "arm,coresight-funnel", "arm,primecell";
303 reg = <0 0x10001000 0 188 reg = <0 0x10001000 0 0x1000>;
304 clocks = <&ext_26m>; 189 clocks = <&ext_26m>;
305 clock-names = "apb_pcl 190 clock-names = "apb_pclk";
306 out-ports { !! 191 ports {
307 port { !! 192 #address-cells = <1>;
>> 193 #size-cells = <0>;
>> 194
>> 195 port@0 {
>> 196 reg = <0>;
308 soc_fu 197 soc_funnel_out_port: endpoint {
309 198 remote-endpoint = <&etb_in>;
310 }; 199 };
311 }; 200 };
312 }; <<
313 <<
314 in-ports { <<
315 #address-cells <<
316 #size-cells = <<
317 201
318 port@0 { !! 202 port@1 {
319 reg = 203 reg = <0>;
320 soc_fu 204 soc_funnel_in_port0: endpoint {
>> 205 slave-mode;
321 206 remote-endpoint =
322 207 <&main_funnel_out_port>;
323 }; 208 };
324 }; 209 };
325 210
326 port@4 { !! 211 port@2 {
327 reg = 212 reg = <4>;
328 soc_fu 213 soc_funnel_in_port1: endpoint {
329 !! 214 slave-mode;
>> 215 remote-endpioint =
330 216 <&stm_out_port>;
331 }; 217 };
332 }; 218 };
333 }; 219 };
334 }; 220 };
335 221
336 etb@10003000 { 222 etb@10003000 {
337 compatible = "arm,core 223 compatible = "arm,coresight-tmc", "arm,primecell";
338 reg = <0 0x10003000 0 224 reg = <0 0x10003000 0 0x1000>;
339 clocks = <&ext_26m>; 225 clocks = <&ext_26m>;
340 clock-names = "apb_pcl 226 clock-names = "apb_pclk";
341 out-ports { !! 227 port {
342 port { !! 228 etb_in: endpoint {
343 etb_in !! 229 slave-mode;
344 !! 230 remote-endpoint =
345 !! 231 <&soc_funnel_out_port>;
346 }; <<
347 }; 232 };
348 }; 233 };
349 }; 234 };
350 235
351 stm@10006000 { 236 stm@10006000 {
352 compatible = "arm,core 237 compatible = "arm,coresight-stm", "arm,primecell";
353 reg = <0 0x10006000 0 238 reg = <0 0x10006000 0 0x1000>,
354 <0 0x01000000 0 239 <0 0x01000000 0 0x180000>;
355 reg-names = "stm-base" 240 reg-names = "stm-base", "stm-stimulus-base";
356 clocks = <&ext_26m>; 241 clocks = <&ext_26m>;
357 clock-names = "apb_pcl 242 clock-names = "apb_pclk";
358 out-ports { !! 243 port {
359 port { !! 244 stm_out_port: endpoint {
360 stm_ou !! 245 remote-endpoint =
361 !! 246 <&soc_funnel_in_port1>;
362 <<
363 }; <<
364 }; 247 };
365 }; 248 };
366 }; 249 };
367 250
368 funnel@11001000 { /* Cluster0 251 funnel@11001000 { /* Cluster0 Funnel */
369 compatible = "arm,core !! 252 compatible = "arm,coresight-funnel", "arm,primecell";
370 reg = <0 0x11001000 0 253 reg = <0 0x11001000 0 0x1000>;
371 clocks = <&ext_26m>; 254 clocks = <&ext_26m>;
372 clock-names = "apb_pcl 255 clock-names = "apb_pclk";
373 out-ports { !! 256 ports {
374 port { !! 257 #address-cells = <1>;
>> 258 #size-cells = <0>;
>> 259
>> 260 port@0 {
>> 261 reg = <0>;
375 cluste 262 cluster0_funnel_out_port: endpoint {
376 263 remote-endpoint =
377 264 <&cluster0_etf_in>;
378 }; 265 };
379 }; 266 };
380 }; <<
381 <<
382 in-ports { <<
383 #address-cells <<
384 #size-cells = <<
385 267
386 port@0 { !! 268 port@1 {
387 reg = 269 reg = <0>;
388 cluste 270 cluster0_funnel_in_port0: endpoint {
>> 271 slave-mode;
389 272 remote-endpoint = <&etm0_out>;
390 }; 273 };
391 }; 274 };
392 275
393 port@1 { !! 276 port@2 {
394 reg = 277 reg = <1>;
395 cluste 278 cluster0_funnel_in_port1: endpoint {
>> 279 slave-mode;
396 280 remote-endpoint = <&etm1_out>;
397 }; 281 };
398 }; 282 };
399 283
400 port@2 { !! 284 port@3 {
401 reg = 285 reg = <2>;
402 cluste 286 cluster0_funnel_in_port2: endpoint {
>> 287 slave-mode;
403 288 remote-endpoint = <&etm2_out>;
404 }; 289 };
405 }; 290 };
406 291
407 port@4 { 292 port@4 {
408 reg = 293 reg = <4>;
409 cluste 294 cluster0_funnel_in_port3: endpoint {
>> 295 slave-mode;
410 296 remote-endpoint = <&etm3_out>;
411 }; 297 };
412 }; 298 };
413 }; 299 };
414 }; 300 };
415 301
416 funnel@11002000 { /* Cluster1 302 funnel@11002000 { /* Cluster1 Funnel */
417 compatible = "arm,core !! 303 compatible = "arm,coresight-funnel", "arm,primecell";
418 reg = <0 0x11002000 0 304 reg = <0 0x11002000 0 0x1000>;
419 clocks = <&ext_26m>; 305 clocks = <&ext_26m>;
420 clock-names = "apb_pcl 306 clock-names = "apb_pclk";
421 out-ports { !! 307 ports {
422 port { !! 308 #address-cells = <1>;
>> 309 #size-cells = <0>;
>> 310
>> 311 port@0 {
>> 312 reg = <0>;
423 cluste 313 cluster1_funnel_out_port: endpoint {
424 314 remote-endpoint =
425 315 <&cluster1_etf_in>;
426 }; 316 };
427 }; 317 };
428 }; <<
429 <<
430 in-ports { <<
431 #address-cells <<
432 #size-cells = <<
433 318
434 port@0 { !! 319 port@1 {
435 reg = 320 reg = <0>;
436 cluste 321 cluster1_funnel_in_port0: endpoint {
>> 322 slave-mode;
437 323 remote-endpoint = <&etm4_out>;
438 }; 324 };
439 }; 325 };
440 326
441 port@1 { !! 327 port@2 {
442 reg = 328 reg = <1>;
443 cluste 329 cluster1_funnel_in_port1: endpoint {
>> 330 slave-mode;
444 331 remote-endpoint = <&etm5_out>;
445 }; 332 };
446 }; 333 };
447 334
448 port@2 { !! 335 port@3 {
449 reg = 336 reg = <2>;
450 cluste 337 cluster1_funnel_in_port2: endpoint {
>> 338 slave-mode;
451 339 remote-endpoint = <&etm6_out>;
452 }; 340 };
453 }; 341 };
454 342
455 port@3 { !! 343 port@4 {
456 reg = 344 reg = <3>;
457 cluste 345 cluster1_funnel_in_port3: endpoint {
>> 346 slave-mode;
458 347 remote-endpoint = <&etm7_out>;
459 }; 348 };
460 }; 349 };
461 }; 350 };
462 }; 351 };
463 352
464 etf@11003000 { /* ETF on Clus 353 etf@11003000 { /* ETF on Cluster0 */
465 compatible = "arm,core 354 compatible = "arm,coresight-tmc", "arm,primecell";
466 reg = <0 0x11003000 0 355 reg = <0 0x11003000 0 0x1000>;
467 clocks = <&ext_26m>; 356 clocks = <&ext_26m>;
468 clock-names = "apb_pcl 357 clock-names = "apb_pclk";
469 358
470 out-ports { !! 359 ports {
471 port { !! 360 #address-cells = <1>;
>> 361 #size-cells = <0>;
>> 362
>> 363 port@0 {
>> 364 reg = <0>;
472 cluste 365 cluster0_etf_out: endpoint {
473 366 remote-endpoint =
474 367 <&main_funnel_in_port0>;
475 }; 368 };
476 }; 369 };
477 }; <<
478 370
479 in-ports { !! 371 port@1 {
480 port { !! 372 reg = <0>;
481 cluste 373 cluster0_etf_in: endpoint {
>> 374 slave-mode;
482 375 remote-endpoint =
483 376 <&cluster0_funnel_out_port>;
484 }; 377 };
485 }; 378 };
486 }; 379 };
487 }; 380 };
488 381
489 etf@11004000 { /* ETF on Clust 382 etf@11004000 { /* ETF on Cluster1 */
490 compatible = "arm,core 383 compatible = "arm,coresight-tmc", "arm,primecell";
491 reg = <0 0x11004000 0 384 reg = <0 0x11004000 0 0x1000>;
492 clocks = <&ext_26m>; 385 clocks = <&ext_26m>;
493 clock-names = "apb_pcl 386 clock-names = "apb_pclk";
494 387
495 out-ports { !! 388 ports {
496 port { !! 389 #address-cells = <1>;
>> 390 #size-cells = <0>;
>> 391
>> 392 port@0 {
>> 393 reg = <0>;
497 cluste 394 cluster1_etf_out: endpoint {
498 395 remote-endpoint =
499 396 <&main_funnel_in_port1>;
500 }; 397 };
501 }; 398 };
502 }; <<
503 399
504 in-ports { !! 400 port@1 {
505 port { !! 401 reg = <0>;
506 cluste 402 cluster1_etf_in: endpoint {
>> 403 slave-mode;
507 404 remote-endpoint =
508 405 <&cluster1_funnel_out_port>;
509 }; 406 };
510 }; 407 };
511 }; 408 };
512 }; 409 };
513 410
514 funnel@11005000 { /* Main Funn 411 funnel@11005000 { /* Main Funnel */
515 compatible = "arm,core !! 412 compatible = "arm,coresight-funnel", "arm,primecell";
516 reg = <0 0x11005000 0 413 reg = <0 0x11005000 0 0x1000>;
517 clocks = <&ext_26m>; 414 clocks = <&ext_26m>;
518 clock-names = "apb_pcl 415 clock-names = "apb_pclk";
519 416
520 out-ports { !! 417 ports {
521 port { !! 418 #address-cells = <1>;
>> 419 #size-cells = <0>;
>> 420
>> 421 port@0 {
>> 422 reg = <0>;
522 main_f 423 main_funnel_out_port: endpoint {
523 424 remote-endpoint =
524 425 <&soc_funnel_in_port0>;
525 }; 426 };
526 }; 427 };
527 }; <<
528 <<
529 in-ports { <<
530 #address-cells <<
531 #size-cells = <<
532 428
533 port@0 { !! 429 port@1 {
534 reg = 430 reg = <0>;
535 main_f 431 main_funnel_in_port0: endpoint {
>> 432 slave-mode;
536 433 remote-endpoint =
537 434 <&cluster0_etf_out>;
538 }; 435 };
539 }; 436 };
540 437
541 port@1 { !! 438 port@2 {
542 reg = 439 reg = <1>;
543 main_f 440 main_funnel_in_port1: endpoint {
>> 441 slave-mode;
544 442 remote-endpoint =
545 443 <&cluster1_etf_out>;
546 }; 444 };
547 }; 445 };
548 }; 446 };
549 }; 447 };
550 448
551 etm@11440000 { 449 etm@11440000 {
552 compatible = "arm,core 450 compatible = "arm,coresight-etm4x", "arm,primecell";
553 reg = <0 0x11440000 0 451 reg = <0 0x11440000 0 0x1000>;
554 cpu = <&CPU0>; 452 cpu = <&CPU0>;
555 clocks = <&ext_26m>; 453 clocks = <&ext_26m>;
556 clock-names = "apb_pcl 454 clock-names = "apb_pclk";
557 455
558 out-ports { !! 456 port {
559 port { !! 457 etm0_out: endpoint {
560 etm0_o !! 458 remote-endpoint =
561 !! 459 <&cluster0_funnel_in_port0>;
562 <<
563 }; <<
564 }; 460 };
565 }; 461 };
566 }; 462 };
567 463
568 etm@11540000 { 464 etm@11540000 {
569 compatible = "arm,core 465 compatible = "arm,coresight-etm4x", "arm,primecell";
570 reg = <0 0x11540000 0 466 reg = <0 0x11540000 0 0x1000>;
571 cpu = <&CPU1>; 467 cpu = <&CPU1>;
572 clocks = <&ext_26m>; 468 clocks = <&ext_26m>;
573 clock-names = "apb_pcl 469 clock-names = "apb_pclk";
574 470
575 out-ports { !! 471 port {
576 port { !! 472 etm1_out: endpoint {
577 etm1_o !! 473 remote-endpoint =
578 !! 474 <&cluster0_funnel_in_port1>;
579 <<
580 }; <<
581 }; 475 };
582 }; 476 };
583 }; 477 };
584 478
585 etm@11640000 { 479 etm@11640000 {
586 compatible = "arm,core 480 compatible = "arm,coresight-etm4x", "arm,primecell";
587 reg = <0 0x11640000 0 481 reg = <0 0x11640000 0 0x1000>;
588 cpu = <&CPU2>; 482 cpu = <&CPU2>;
589 clocks = <&ext_26m>; 483 clocks = <&ext_26m>;
590 clock-names = "apb_pcl 484 clock-names = "apb_pclk";
591 485
592 out-ports { !! 486 port {
593 port { !! 487 etm2_out: endpoint {
594 etm2_o !! 488 remote-endpoint =
595 !! 489 <&cluster0_funnel_in_port2>;
596 <<
597 }; <<
598 }; 490 };
599 }; 491 };
600 }; 492 };
601 493
602 etm@11740000 { 494 etm@11740000 {
603 compatible = "arm,core 495 compatible = "arm,coresight-etm4x", "arm,primecell";
604 reg = <0 0x11740000 0 496 reg = <0 0x11740000 0 0x1000>;
605 cpu = <&CPU3>; 497 cpu = <&CPU3>;
606 clocks = <&ext_26m>; 498 clocks = <&ext_26m>;
607 clock-names = "apb_pcl 499 clock-names = "apb_pclk";
608 500
609 out-ports { !! 501 port {
610 port { !! 502 etm3_out: endpoint {
611 etm3_o !! 503 remote-endpoint =
612 !! 504 <&cluster0_funnel_in_port3>;
613 <<
614 }; <<
615 }; 505 };
616 }; 506 };
617 }; 507 };
618 508
619 etm@11840000 { 509 etm@11840000 {
620 compatible = "arm,core 510 compatible = "arm,coresight-etm4x", "arm,primecell";
621 reg = <0 0x11840000 0 511 reg = <0 0x11840000 0 0x1000>;
622 cpu = <&CPU4>; 512 cpu = <&CPU4>;
623 clocks = <&ext_26m>; 513 clocks = <&ext_26m>;
624 clock-names = "apb_pcl 514 clock-names = "apb_pclk";
625 515
626 out-ports { !! 516 port {
627 port { !! 517 etm4_out: endpoint {
628 etm4_o !! 518 remote-endpoint =
629 !! 519 <&cluster1_funnel_in_port0>;
630 <<
631 }; <<
632 }; 520 };
633 }; 521 };
634 }; 522 };
635 523
636 etm@11940000 { 524 etm@11940000 {
637 compatible = "arm,core 525 compatible = "arm,coresight-etm4x", "arm,primecell";
638 reg = <0 0x11940000 0 526 reg = <0 0x11940000 0 0x1000>;
639 cpu = <&CPU5>; 527 cpu = <&CPU5>;
640 clocks = <&ext_26m>; 528 clocks = <&ext_26m>;
641 clock-names = "apb_pcl 529 clock-names = "apb_pclk";
642 530
643 out-ports { !! 531 port {
644 port { !! 532 etm5_out: endpoint {
645 etm5_o !! 533 remote-endpoint =
646 !! 534 <&cluster1_funnel_in_port1>;
647 <<
648 }; <<
649 }; 535 };
650 }; 536 };
651 }; 537 };
652 538
653 etm@11a40000 { 539 etm@11a40000 {
654 compatible = "arm,core 540 compatible = "arm,coresight-etm4x", "arm,primecell";
655 reg = <0 0x11a40000 0 541 reg = <0 0x11a40000 0 0x1000>;
656 cpu = <&CPU6>; 542 cpu = <&CPU6>;
657 clocks = <&ext_26m>; 543 clocks = <&ext_26m>;
658 clock-names = "apb_pcl 544 clock-names = "apb_pclk";
659 545
660 out-ports { !! 546 port {
661 port { !! 547 etm6_out: endpoint {
662 etm6_o !! 548 remote-endpoint =
663 !! 549 <&cluster1_funnel_in_port2>;
664 <<
665 }; <<
666 }; 550 };
667 }; 551 };
668 }; 552 };
669 553
670 etm@11b40000 { 554 etm@11b40000 {
671 compatible = "arm,core 555 compatible = "arm,coresight-etm4x", "arm,primecell";
672 reg = <0 0x11b40000 0 556 reg = <0 0x11b40000 0 0x1000>;
673 cpu = <&CPU7>; 557 cpu = <&CPU7>;
674 clocks = <&ext_26m>; 558 clocks = <&ext_26m>;
675 clock-names = "apb_pcl 559 clock-names = "apb_pclk";
676 560
677 out-ports { !! 561 port {
678 port { !! 562 etm7_out: endpoint {
679 etm7_o !! 563 remote-endpoint =
680 !! 564 <&cluster1_funnel_in_port3>;
681 <<
682 }; <<
683 }; 565 };
684 }; 566 };
685 }; 567 };
686 }; 568 };
687 }; 569 };
Linux® is a registered trademark of Linus Torvalds in the United States and other countries.
TOMOYO® is a registered trademark of NTT DATA CORPORATION.