1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) <<
2 /* 1 /*
3 * Spreadtrum SC9860 SoC 2 * Spreadtrum SC9860 SoC
4 * 3 *
5 * Copyright (C) 2016, Spreadtrum Communicatio 4 * Copyright (C) 2016, Spreadtrum Communications Inc.
>> 5 *
>> 6 * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 */ 7 */
7 8
8 #include <dt-bindings/interrupt-controller/arm 9 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/input/input.h> <<
10 #include <dt-bindings/gpio/gpio.h> <<
11 #include "whale2.dtsi" 10 #include "whale2.dtsi"
12 11
13 / { 12 / {
14 cpus { 13 cpus {
15 #address-cells = <2>; 14 #address-cells = <2>;
16 #size-cells = <0>; 15 #size-cells = <0>;
17 16
18 cpu-map { 17 cpu-map {
19 cluster0 { 18 cluster0 {
20 core0 { 19 core0 {
21 cpu = 20 cpu = <&CPU0>;
22 }; 21 };
23 core1 { 22 core1 {
24 cpu = 23 cpu = <&CPU1>;
25 }; 24 };
26 core2 { 25 core2 {
27 cpu = 26 cpu = <&CPU2>;
28 }; 27 };
29 core3 { 28 core3 {
30 cpu = 29 cpu = <&CPU3>;
31 }; 30 };
32 }; 31 };
33 32
34 cluster1 { 33 cluster1 {
35 core0 { 34 core0 {
36 cpu = 35 cpu = <&CPU4>;
37 }; 36 };
38 core1 { 37 core1 {
39 cpu = 38 cpu = <&CPU5>;
40 }; 39 };
41 core2 { 40 core2 {
42 cpu = 41 cpu = <&CPU6>;
43 }; 42 };
44 core3 { 43 core3 {
45 cpu = 44 cpu = <&CPU7>;
46 }; 45 };
47 }; 46 };
48 }; 47 };
49 48
50 CPU0: cpu@530000 { 49 CPU0: cpu@530000 {
51 device_type = "cpu"; 50 device_type = "cpu";
52 compatible = "arm,cort !! 51 compatible = "arm,cortex-a53", "arm,armv8";
53 reg = <0x0 0x530000>; 52 reg = <0x0 0x530000>;
54 enable-method = "psci" 53 enable-method = "psci";
55 cpu-idle-states = <&CO 54 cpu-idle-states = <&CORE_PD &CLUSTER_PD>;
56 }; 55 };
57 56
58 CPU1: cpu@530001 { 57 CPU1: cpu@530001 {
59 device_type = "cpu"; 58 device_type = "cpu";
60 compatible = "arm,cort !! 59 compatible = "arm,cortex-a53", "arm,armv8";
61 reg = <0x0 0x530001>; 60 reg = <0x0 0x530001>;
62 enable-method = "psci" 61 enable-method = "psci";
63 cpu-idle-states = <&CO 62 cpu-idle-states = <&CORE_PD &CLUSTER_PD>;
64 }; 63 };
65 64
66 CPU2: cpu@530002 { 65 CPU2: cpu@530002 {
67 device_type = "cpu"; 66 device_type = "cpu";
68 compatible = "arm,cort !! 67 compatible = "arm,cortex-a53", "arm,armv8";
69 reg = <0x0 0x530002>; 68 reg = <0x0 0x530002>;
70 enable-method = "psci" 69 enable-method = "psci";
71 cpu-idle-states = <&CO 70 cpu-idle-states = <&CORE_PD &CLUSTER_PD>;
72 }; 71 };
73 72
74 CPU3: cpu@530003 { 73 CPU3: cpu@530003 {
75 device_type = "cpu"; 74 device_type = "cpu";
76 compatible = "arm,cort !! 75 compatible = "arm,cortex-a53", "arm,armv8";
77 reg = <0x0 0x530003>; 76 reg = <0x0 0x530003>;
78 enable-method = "psci" 77 enable-method = "psci";
79 cpu-idle-states = <&CO 78 cpu-idle-states = <&CORE_PD &CLUSTER_PD>;
80 }; 79 };
81 80
82 CPU4: cpu@530100 { 81 CPU4: cpu@530100 {
83 device_type = "cpu"; 82 device_type = "cpu";
84 compatible = "arm,cort !! 83 compatible = "arm,cortex-a53", "arm,armv8";
85 reg = <0x0 0x530100>; 84 reg = <0x0 0x530100>;
86 enable-method = "psci" 85 enable-method = "psci";
87 cpu-idle-states = <&CO 86 cpu-idle-states = <&CORE_PD &CLUSTER_PD>;
88 }; 87 };
89 88
90 CPU5: cpu@530101 { 89 CPU5: cpu@530101 {
91 device_type = "cpu"; 90 device_type = "cpu";
92 compatible = "arm,cort !! 91 compatible = "arm,cortex-a53", "arm,armv8";
93 reg = <0x0 0x530101>; 92 reg = <0x0 0x530101>;
94 enable-method = "psci" 93 enable-method = "psci";
95 cpu-idle-states = <&CO 94 cpu-idle-states = <&CORE_PD &CLUSTER_PD>;
96 }; 95 };
97 96
98 CPU6: cpu@530102 { 97 CPU6: cpu@530102 {
99 device_type = "cpu"; 98 device_type = "cpu";
100 compatible = "arm,cort !! 99 compatible = "arm,cortex-a53", "arm,armv8";
101 reg = <0x0 0x530102>; 100 reg = <0x0 0x530102>;
102 enable-method = "psci" 101 enable-method = "psci";
103 cpu-idle-states = <&CO 102 cpu-idle-states = <&CORE_PD &CLUSTER_PD>;
104 }; 103 };
105 104
106 CPU7: cpu@530103 { 105 CPU7: cpu@530103 {
107 device_type = "cpu"; 106 device_type = "cpu";
108 compatible = "arm,cort !! 107 compatible = "arm,cortex-a53", "arm,armv8";
109 reg = <0x0 0x530103>; 108 reg = <0x0 0x530103>;
110 enable-method = "psci" 109 enable-method = "psci";
111 cpu-idle-states = <&CO 110 cpu-idle-states = <&CORE_PD &CLUSTER_PD>;
112 }; 111 };
113 }; 112 };
114 113
115 idle-states { !! 114 idle-states{
116 entry-method = "psci"; !! 115 entry-method = "arm,psci";
117 116
118 CORE_PD: core_pd { 117 CORE_PD: core_pd {
119 compatible = "arm,idle 118 compatible = "arm,idle-state";
120 entry-latency-us = <10 119 entry-latency-us = <1000>;
121 exit-latency-us = <700 120 exit-latency-us = <700>;
122 min-residency-us = <25 121 min-residency-us = <2500>;
123 local-timer-stop; 122 local-timer-stop;
124 arm,psci-suspend-param 123 arm,psci-suspend-param = <0x00010002>;
125 }; 124 };
126 125
127 CLUSTER_PD: cluster_pd { 126 CLUSTER_PD: cluster_pd {
128 compatible = "arm,idle 127 compatible = "arm,idle-state";
129 entry-latency-us = <10 128 entry-latency-us = <1000>;
130 exit-latency-us = <100 129 exit-latency-us = <1000>;
131 min-residency-us = <30 130 min-residency-us = <3000>;
132 local-timer-stop; 131 local-timer-stop;
133 arm,psci-suspend-param 132 arm,psci-suspend-param = <0x01010003>;
134 }; 133 };
135 }; 134 };
136 135
>> 136 gic: interrupt-controller@12001000 {
>> 137 compatible = "arm,gic-400";
>> 138 reg = <0 0x12001000 0 0x1000>,
>> 139 <0 0x12002000 0 0x2000>,
>> 140 <0 0x12004000 0 0x2000>,
>> 141 <0 0x12006000 0 0x2000>;
>> 142 #interrupt-cells = <3>;
>> 143 interrupt-controller;
>> 144 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8)
>> 145 | IRQ_TYPE_LEVEL_HIGH)>;
>> 146 };
>> 147
137 psci { 148 psci {
138 compatible = "arm,psci-0.2"; 149 compatible = "arm,psci-0.2";
139 method = "smc"; 150 method = "smc";
140 }; 151 };
141 152
142 timer { 153 timer {
143 compatible = "arm,armv8-timer" 154 compatible = "arm,armv8-timer";
144 interrupts = <GIC_PPI 13 (GIC_ 155 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8)
145 | IRQ 156 | IRQ_TYPE_LEVEL_LOW)>,
146 <GIC_PPI 14 (GIC_ 157 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8)
147 | IRQ 158 | IRQ_TYPE_LEVEL_LOW)>,
148 <GIC_PPI 11 (GIC_ 159 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8)
149 | IRQ 160 | IRQ_TYPE_LEVEL_LOW)>,
150 <GIC_PPI 10 (GIC_ 161 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8)
151 | IRQ 162 | IRQ_TYPE_LEVEL_LOW)>;
152 }; 163 };
153 164
154 pmu { 165 pmu {
155 compatible = "arm,cortex-a53-p !! 166 compatible = "arm,cortex-a53-pmu", "arm,armv8-pmuv3";
156 interrupts = <GIC_SPI 122 IRQ_ 167 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
157 <GIC_SPI 123 IRQ_ 168 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
158 <GIC_SPI 124 IRQ_ 169 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
159 <GIC_SPI 125 IRQ_ 170 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
160 <GIC_SPI 154 IRQ_ 171 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
161 <GIC_SPI 155 IRQ_ 172 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
162 <GIC_SPI 156 IRQ_ 173 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>,
163 <GIC_SPI 157 IRQ_ 174 <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
164 interrupt-affinity = <&CPU0>, 175 interrupt-affinity = <&CPU0>,
165 <&CPU1>, 176 <&CPU1>,
166 <&CPU2>, 177 <&CPU2>,
167 <&CPU3>, 178 <&CPU3>,
168 <&CPU4>, 179 <&CPU4>,
169 <&CPU5>, 180 <&CPU5>,
170 <&CPU6>, 181 <&CPU6>,
171 <&CPU7>; 182 <&CPU7>;
172 }; 183 };
173 184
174 soc { 185 soc {
175 gic: interrupt-controller@1200 <<
176 compatible = "arm,gic- <<
177 reg = <0 0x12001000 0 <<
178 <0 0x12002000 0 <<
179 <0 0x12004000 0 <<
180 <0 0x12006000 0 <<
181 #interrupt-cells = <3> <<
182 interrupt-controller; <<
183 interrupts = <GIC_PPI <<
184 <<
185 }; <<
186 <<
187 pmu_gate: pmu-gate { 186 pmu_gate: pmu-gate {
188 compatible = "sprd,sc9 187 compatible = "sprd,sc9860-pmu-gate";
189 sprd,syscon = <&pmu_re 188 sprd,syscon = <&pmu_regs>; /* 0x402b0000 */
190 clocks = <&ext_26m>; 189 clocks = <&ext_26m>;
191 #clock-cells = <1>; 190 #clock-cells = <1>;
192 }; 191 };
193 192
194 pll: pll { 193 pll: pll {
195 compatible = "sprd,sc9 194 compatible = "sprd,sc9860-pll";
196 sprd,syscon = <&ana_re 195 sprd,syscon = <&ana_regs>; /* 0x40400000 */
197 clocks = <&pmu_gate 0> 196 clocks = <&pmu_gate 0>;
198 #clock-cells = <1>; 197 #clock-cells = <1>;
199 }; 198 };
200 199
201 ap_clk: clock-controller@20000 200 ap_clk: clock-controller@20000000 {
202 compatible = "sprd,sc9 201 compatible = "sprd,sc9860-ap-clk";
203 reg = <0 0x20000000 0 202 reg = <0 0x20000000 0 0x400>;
204 clocks = <&ext_26m>, < 203 clocks = <&ext_26m>, <&pll 0>,
205 <&pmu_gate 0> 204 <&pmu_gate 0>;
206 #clock-cells = <1>; 205 #clock-cells = <1>;
207 }; 206 };
208 207
209 aon_prediv: aon-prediv@402d000 !! 208 aon_prediv: aon-prediv {
210 compatible = "sprd,sc9 209 compatible = "sprd,sc9860-aon-prediv";
211 reg = <0 0x402d0000 0 210 reg = <0 0x402d0000 0 0x400>;
212 clocks = <&ext_26m>, < 211 clocks = <&ext_26m>, <&pll 0>,
213 <&pmu_gate 0> 212 <&pmu_gate 0>;
214 #clock-cells = <1>; 213 #clock-cells = <1>;
215 }; 214 };
216 215
217 apahb_gate: apahb-gate { 216 apahb_gate: apahb-gate {
218 compatible = "sprd,sc9 217 compatible = "sprd,sc9860-apahb-gate";
219 sprd,syscon = <&ap_ahb 218 sprd,syscon = <&ap_ahb_regs>; /* 0x20210000 */
220 clocks = <&aon_prediv 219 clocks = <&aon_prediv 0>;
221 #clock-cells = <1>; 220 #clock-cells = <1>;
222 }; 221 };
223 222
224 aon_gate: aon-gate { 223 aon_gate: aon-gate {
225 compatible = "sprd,sc9 224 compatible = "sprd,sc9860-aon-gate";
226 sprd,syscon = <&aon_re 225 sprd,syscon = <&aon_regs>; /* 0x402e0000 */
227 clocks = <&aon_prediv 226 clocks = <&aon_prediv 0>;
228 #clock-cells = <1>; 227 #clock-cells = <1>;
229 }; 228 };
230 229
231 aonsecure_clk: clock-controlle 230 aonsecure_clk: clock-controller@40880000 {
232 compatible = "sprd,sc9 231 compatible = "sprd,sc9860-aonsecure-clk";
233 reg = <0 0x40880000 0 232 reg = <0 0x40880000 0 0x400>;
234 clocks = <&ext_26m>, < 233 clocks = <&ext_26m>, <&pll 0>;
235 #clock-cells = <1>; 234 #clock-cells = <1>;
236 }; 235 };
237 236
238 agcp_gate: agcp-gate { 237 agcp_gate: agcp-gate {
239 compatible = "sprd,sc9 238 compatible = "sprd,sc9860-agcp-gate";
240 sprd,syscon = <&agcp_r 239 sprd,syscon = <&agcp_regs>; /* 0x415e0000 */
241 clocks = <&aon_prediv 240 clocks = <&aon_prediv 0>;
242 #clock-cells = <1>; 241 #clock-cells = <1>;
243 }; 242 };
244 243
245 gpu_clk: clock-controller@6020 244 gpu_clk: clock-controller@60200000 {
246 compatible = "sprd,sc9 245 compatible = "sprd,sc9860-gpu-clk";
247 reg = <0 0x60200000 0 246 reg = <0 0x60200000 0 0x400>;
248 clocks = <&pll 0>; 247 clocks = <&pll 0>;
249 #clock-cells = <1>; 248 #clock-cells = <1>;
250 }; 249 };
251 250
252 vsp_clk: clock-controller@6100 251 vsp_clk: clock-controller@61000000 {
253 compatible = "sprd,sc9 252 compatible = "sprd,sc9860-vsp-clk";
254 reg = <0 0x61000000 0 253 reg = <0 0x61000000 0 0x400>;
255 clocks = <&ext_26m>, < 254 clocks = <&ext_26m>, <&pll 0>;
256 #clock-cells = <1>; 255 #clock-cells = <1>;
257 }; 256 };
258 257
259 vsp_gate: vsp-gate { 258 vsp_gate: vsp-gate {
260 compatible = "sprd,sc9 259 compatible = "sprd,sc9860-vsp-gate";
261 sprd,syscon = <&vsp_re 260 sprd,syscon = <&vsp_regs>; /* 0x61100000 */
262 clocks = <&vsp_clk 0>; 261 clocks = <&vsp_clk 0>;
263 #clock-cells = <1>; 262 #clock-cells = <1>;
264 }; 263 };
265 264
266 cam_clk: clock-controller@6200 265 cam_clk: clock-controller@62000000 {
267 compatible = "sprd,sc9 266 compatible = "sprd,sc9860-cam-clk";
268 reg = <0 0x62000000 0 267 reg = <0 0x62000000 0 0x4000>;
269 clocks = <&ext_26m>, < 268 clocks = <&ext_26m>, <&pll 0>;
270 #clock-cells = <1>; 269 #clock-cells = <1>;
271 }; 270 };
272 271
273 cam_gate: cam-gate { 272 cam_gate: cam-gate {
274 compatible = "sprd,sc9 273 compatible = "sprd,sc9860-cam-gate";
275 sprd,syscon = <&cam_re 274 sprd,syscon = <&cam_regs>; /* 0x62100000 */
276 clocks = <&cam_clk 0>; 275 clocks = <&cam_clk 0>;
277 #clock-cells = <1>; 276 #clock-cells = <1>;
278 }; 277 };
279 278
280 disp_clk: clock-controller@630 279 disp_clk: clock-controller@63000000 {
281 compatible = "sprd,sc9 280 compatible = "sprd,sc9860-disp-clk";
282 reg = <0 0x63000000 0 281 reg = <0 0x63000000 0 0x400>;
283 clocks = <&ext_26m>, < 282 clocks = <&ext_26m>, <&pll 0>;
284 #clock-cells = <1>; 283 #clock-cells = <1>;
285 }; 284 };
286 285
287 disp_gate: disp-gate { 286 disp_gate: disp-gate {
288 compatible = "sprd,sc9 287 compatible = "sprd,sc9860-disp-gate";
289 sprd,syscon = <&disp_r 288 sprd,syscon = <&disp_regs>; /* 0x63100000 */
290 clocks = <&disp_clk 0> 289 clocks = <&disp_clk 0>;
291 #clock-cells = <1>; 290 #clock-cells = <1>;
292 }; 291 };
293 292
294 apapb_gate: apapb-gate { 293 apapb_gate: apapb-gate {
295 compatible = "sprd,sc9 294 compatible = "sprd,sc9860-apapb-gate";
296 sprd,syscon = <&ap_apb 295 sprd,syscon = <&ap_apb_regs>; /* 0x70b00000 */
297 clocks = <&ap_clk 0>; 296 clocks = <&ap_clk 0>;
298 #clock-cells = <1>; 297 #clock-cells = <1>;
299 }; 298 };
300 299
301 funnel@10001000 { /* SoC Funne 300 funnel@10001000 { /* SoC Funnel */
302 compatible = "arm,core !! 301 compatible = "arm,coresight-funnel", "arm,primecell";
303 reg = <0 0x10001000 0 302 reg = <0 0x10001000 0 0x1000>;
304 clocks = <&ext_26m>; 303 clocks = <&ext_26m>;
305 clock-names = "apb_pcl 304 clock-names = "apb_pclk";
306 out-ports { !! 305 ports {
307 port { !! 306 #address-cells = <1>;
>> 307 #size-cells = <0>;
>> 308
>> 309 port@0 {
>> 310 reg = <0>;
308 soc_fu 311 soc_funnel_out_port: endpoint {
309 312 remote-endpoint = <&etb_in>;
310 }; 313 };
311 }; 314 };
312 }; <<
313 315
314 in-ports { !! 316 port@1 {
315 #address-cells <<
316 #size-cells = <<
317 <<
318 port@0 { <<
319 reg = 317 reg = <0>;
320 soc_fu 318 soc_funnel_in_port0: endpoint {
>> 319 slave-mode;
321 320 remote-endpoint =
322 321 <&main_funnel_out_port>;
323 }; 322 };
324 }; 323 };
325 324
326 port@4 { !! 325 port@2 {
327 reg = 326 reg = <4>;
328 soc_fu 327 soc_funnel_in_port1: endpoint {
329 !! 328 slave-mode;
>> 329 remote-endpioint =
330 330 <&stm_out_port>;
331 }; 331 };
332 }; 332 };
333 }; 333 };
334 }; 334 };
335 335
336 etb@10003000 { 336 etb@10003000 {
337 compatible = "arm,core 337 compatible = "arm,coresight-tmc", "arm,primecell";
338 reg = <0 0x10003000 0 338 reg = <0 0x10003000 0 0x1000>;
339 clocks = <&ext_26m>; 339 clocks = <&ext_26m>;
340 clock-names = "apb_pcl 340 clock-names = "apb_pclk";
341 out-ports { !! 341 port {
342 port { !! 342 etb_in: endpoint {
343 etb_in !! 343 slave-mode;
344 !! 344 remote-endpoint =
345 !! 345 <&soc_funnel_out_port>;
346 }; <<
347 }; 346 };
348 }; 347 };
349 }; 348 };
350 349
351 stm@10006000 { 350 stm@10006000 {
352 compatible = "arm,core 351 compatible = "arm,coresight-stm", "arm,primecell";
353 reg = <0 0x10006000 0 352 reg = <0 0x10006000 0 0x1000>,
354 <0 0x01000000 0 353 <0 0x01000000 0 0x180000>;
355 reg-names = "stm-base" 354 reg-names = "stm-base", "stm-stimulus-base";
356 clocks = <&ext_26m>; 355 clocks = <&ext_26m>;
357 clock-names = "apb_pcl 356 clock-names = "apb_pclk";
358 out-ports { !! 357 port {
359 port { !! 358 stm_out_port: endpoint {
360 stm_ou !! 359 remote-endpoint =
361 !! 360 <&soc_funnel_in_port1>;
362 <<
363 }; <<
364 }; 361 };
365 }; 362 };
366 }; 363 };
367 364
368 funnel@11001000 { /* Cluster0 365 funnel@11001000 { /* Cluster0 Funnel */
369 compatible = "arm,core !! 366 compatible = "arm,coresight-funnel", "arm,primecell";
370 reg = <0 0x11001000 0 367 reg = <0 0x11001000 0 0x1000>;
371 clocks = <&ext_26m>; 368 clocks = <&ext_26m>;
372 clock-names = "apb_pcl 369 clock-names = "apb_pclk";
373 out-ports { !! 370 ports {
374 port { !! 371 #address-cells = <1>;
>> 372 #size-cells = <0>;
>> 373
>> 374 port@0 {
>> 375 reg = <0>;
375 cluste 376 cluster0_funnel_out_port: endpoint {
376 377 remote-endpoint =
377 378 <&cluster0_etf_in>;
378 }; 379 };
379 }; 380 };
380 }; <<
381 <<
382 in-ports { <<
383 #address-cells <<
384 #size-cells = <<
385 381
386 port@0 { !! 382 port@1 {
387 reg = 383 reg = <0>;
388 cluste 384 cluster0_funnel_in_port0: endpoint {
>> 385 slave-mode;
389 386 remote-endpoint = <&etm0_out>;
390 }; 387 };
391 }; 388 };
392 389
393 port@1 { !! 390 port@2 {
394 reg = 391 reg = <1>;
395 cluste 392 cluster0_funnel_in_port1: endpoint {
>> 393 slave-mode;
396 394 remote-endpoint = <&etm1_out>;
397 }; 395 };
398 }; 396 };
399 397
400 port@2 { !! 398 port@3 {
401 reg = 399 reg = <2>;
402 cluste 400 cluster0_funnel_in_port2: endpoint {
>> 401 slave-mode;
403 402 remote-endpoint = <&etm2_out>;
404 }; 403 };
405 }; 404 };
406 405
407 port@4 { 406 port@4 {
408 reg = 407 reg = <4>;
409 cluste 408 cluster0_funnel_in_port3: endpoint {
>> 409 slave-mode;
410 410 remote-endpoint = <&etm3_out>;
411 }; 411 };
412 }; 412 };
413 }; 413 };
414 }; 414 };
415 415
416 funnel@11002000 { /* Cluster1 416 funnel@11002000 { /* Cluster1 Funnel */
417 compatible = "arm,core !! 417 compatible = "arm,coresight-funnel", "arm,primecell";
418 reg = <0 0x11002000 0 418 reg = <0 0x11002000 0 0x1000>;
419 clocks = <&ext_26m>; 419 clocks = <&ext_26m>;
420 clock-names = "apb_pcl 420 clock-names = "apb_pclk";
421 out-ports { !! 421 ports {
422 port { !! 422 #address-cells = <1>;
>> 423 #size-cells = <0>;
>> 424
>> 425 port@0 {
>> 426 reg = <0>;
423 cluste 427 cluster1_funnel_out_port: endpoint {
424 428 remote-endpoint =
425 429 <&cluster1_etf_in>;
426 }; 430 };
427 }; 431 };
428 }; <<
429 432
430 in-ports { !! 433 port@1 {
431 #address-cells <<
432 #size-cells = <<
433 <<
434 port@0 { <<
435 reg = 434 reg = <0>;
436 cluste 435 cluster1_funnel_in_port0: endpoint {
>> 436 slave-mode;
437 437 remote-endpoint = <&etm4_out>;
438 }; 438 };
439 }; 439 };
440 440
441 port@1 { !! 441 port@2 {
442 reg = 442 reg = <1>;
443 cluste 443 cluster1_funnel_in_port1: endpoint {
>> 444 slave-mode;
444 445 remote-endpoint = <&etm5_out>;
445 }; 446 };
446 }; 447 };
447 448
448 port@2 { !! 449 port@3 {
449 reg = 450 reg = <2>;
450 cluste 451 cluster1_funnel_in_port2: endpoint {
>> 452 slave-mode;
451 453 remote-endpoint = <&etm6_out>;
452 }; 454 };
453 }; 455 };
454 456
455 port@3 { !! 457 port@4 {
456 reg = 458 reg = <3>;
457 cluste 459 cluster1_funnel_in_port3: endpoint {
>> 460 slave-mode;
458 461 remote-endpoint = <&etm7_out>;
459 }; 462 };
460 }; 463 };
461 }; 464 };
462 }; 465 };
463 466
464 etf@11003000 { /* ETF on Clus 467 etf@11003000 { /* ETF on Cluster0 */
465 compatible = "arm,core 468 compatible = "arm,coresight-tmc", "arm,primecell";
466 reg = <0 0x11003000 0 469 reg = <0 0x11003000 0 0x1000>;
467 clocks = <&ext_26m>; 470 clocks = <&ext_26m>;
468 clock-names = "apb_pcl 471 clock-names = "apb_pclk";
469 472
470 out-ports { !! 473 ports {
471 port { !! 474 #address-cells = <1>;
>> 475 #size-cells = <0>;
>> 476
>> 477 port@0 {
>> 478 reg = <0>;
472 cluste 479 cluster0_etf_out: endpoint {
473 480 remote-endpoint =
474 481 <&main_funnel_in_port0>;
475 }; 482 };
476 }; 483 };
477 }; <<
478 484
479 in-ports { !! 485 port@1 {
480 port { !! 486 reg = <0>;
481 cluste 487 cluster0_etf_in: endpoint {
>> 488 slave-mode;
482 489 remote-endpoint =
483 490 <&cluster0_funnel_out_port>;
484 }; 491 };
485 }; 492 };
486 }; 493 };
487 }; 494 };
488 495
489 etf@11004000 { /* ETF on Clust 496 etf@11004000 { /* ETF on Cluster1 */
490 compatible = "arm,core 497 compatible = "arm,coresight-tmc", "arm,primecell";
491 reg = <0 0x11004000 0 498 reg = <0 0x11004000 0 0x1000>;
492 clocks = <&ext_26m>; 499 clocks = <&ext_26m>;
493 clock-names = "apb_pcl 500 clock-names = "apb_pclk";
494 501
495 out-ports { !! 502 ports {
496 port { !! 503 #address-cells = <1>;
>> 504 #size-cells = <0>;
>> 505
>> 506 port@0 {
>> 507 reg = <0>;
497 cluste 508 cluster1_etf_out: endpoint {
498 509 remote-endpoint =
499 510 <&main_funnel_in_port1>;
500 }; 511 };
501 }; 512 };
502 }; <<
503 513
504 in-ports { !! 514 port@1 {
505 port { !! 515 reg = <0>;
506 cluste 516 cluster1_etf_in: endpoint {
>> 517 slave-mode;
507 518 remote-endpoint =
508 519 <&cluster1_funnel_out_port>;
509 }; 520 };
510 }; 521 };
511 }; 522 };
512 }; 523 };
513 524
514 funnel@11005000 { /* Main Funn 525 funnel@11005000 { /* Main Funnel */
515 compatible = "arm,core !! 526 compatible = "arm,coresight-funnel", "arm,primecell";
516 reg = <0 0x11005000 0 527 reg = <0 0x11005000 0 0x1000>;
517 clocks = <&ext_26m>; 528 clocks = <&ext_26m>;
518 clock-names = "apb_pcl 529 clock-names = "apb_pclk";
519 530
520 out-ports { !! 531 ports {
521 port { !! 532 #address-cells = <1>;
>> 533 #size-cells = <0>;
>> 534
>> 535 port@0 {
>> 536 reg = <0>;
522 main_f 537 main_funnel_out_port: endpoint {
523 538 remote-endpoint =
524 539 <&soc_funnel_in_port0>;
525 }; 540 };
526 }; 541 };
527 }; <<
528 542
529 in-ports { !! 543 port@1 {
530 #address-cells <<
531 #size-cells = <<
532 <<
533 port@0 { <<
534 reg = 544 reg = <0>;
535 main_f 545 main_funnel_in_port0: endpoint {
>> 546 slave-mode;
536 547 remote-endpoint =
537 548 <&cluster0_etf_out>;
538 }; 549 };
539 }; 550 };
540 551
541 port@1 { !! 552 port@2 {
542 reg = 553 reg = <1>;
543 main_f 554 main_funnel_in_port1: endpoint {
>> 555 slave-mode;
544 556 remote-endpoint =
545 557 <&cluster1_etf_out>;
546 }; 558 };
547 }; 559 };
548 }; 560 };
549 }; 561 };
550 562
551 etm@11440000 { 563 etm@11440000 {
552 compatible = "arm,core 564 compatible = "arm,coresight-etm4x", "arm,primecell";
553 reg = <0 0x11440000 0 565 reg = <0 0x11440000 0 0x1000>;
554 cpu = <&CPU0>; 566 cpu = <&CPU0>;
555 clocks = <&ext_26m>; 567 clocks = <&ext_26m>;
556 clock-names = "apb_pcl 568 clock-names = "apb_pclk";
557 569
558 out-ports { !! 570 port {
559 port { !! 571 etm0_out: endpoint {
560 etm0_o !! 572 remote-endpoint =
561 !! 573 <&cluster0_funnel_in_port0>;
562 <<
563 }; <<
564 }; 574 };
565 }; 575 };
566 }; 576 };
567 577
568 etm@11540000 { 578 etm@11540000 {
569 compatible = "arm,core 579 compatible = "arm,coresight-etm4x", "arm,primecell";
570 reg = <0 0x11540000 0 580 reg = <0 0x11540000 0 0x1000>;
571 cpu = <&CPU1>; 581 cpu = <&CPU1>;
572 clocks = <&ext_26m>; 582 clocks = <&ext_26m>;
573 clock-names = "apb_pcl 583 clock-names = "apb_pclk";
574 584
575 out-ports { !! 585 port {
576 port { !! 586 etm1_out: endpoint {
577 etm1_o !! 587 remote-endpoint =
578 !! 588 <&cluster0_funnel_in_port1>;
579 <<
580 }; <<
581 }; 589 };
582 }; 590 };
583 }; 591 };
584 592
585 etm@11640000 { 593 etm@11640000 {
586 compatible = "arm,core 594 compatible = "arm,coresight-etm4x", "arm,primecell";
587 reg = <0 0x11640000 0 595 reg = <0 0x11640000 0 0x1000>;
588 cpu = <&CPU2>; 596 cpu = <&CPU2>;
589 clocks = <&ext_26m>; 597 clocks = <&ext_26m>;
590 clock-names = "apb_pcl 598 clock-names = "apb_pclk";
591 599
592 out-ports { !! 600 port {
593 port { !! 601 etm2_out: endpoint {
594 etm2_o !! 602 remote-endpoint =
595 !! 603 <&cluster0_funnel_in_port2>;
596 <<
597 }; <<
598 }; 604 };
599 }; 605 };
600 }; 606 };
601 607
602 etm@11740000 { 608 etm@11740000 {
603 compatible = "arm,core 609 compatible = "arm,coresight-etm4x", "arm,primecell";
604 reg = <0 0x11740000 0 610 reg = <0 0x11740000 0 0x1000>;
605 cpu = <&CPU3>; 611 cpu = <&CPU3>;
606 clocks = <&ext_26m>; 612 clocks = <&ext_26m>;
607 clock-names = "apb_pcl 613 clock-names = "apb_pclk";
608 614
609 out-ports { !! 615 port {
610 port { !! 616 etm3_out: endpoint {
611 etm3_o !! 617 remote-endpoint =
612 !! 618 <&cluster0_funnel_in_port3>;
613 <<
614 }; <<
615 }; 619 };
616 }; 620 };
617 }; 621 };
618 622
619 etm@11840000 { 623 etm@11840000 {
620 compatible = "arm,core 624 compatible = "arm,coresight-etm4x", "arm,primecell";
621 reg = <0 0x11840000 0 625 reg = <0 0x11840000 0 0x1000>;
622 cpu = <&CPU4>; 626 cpu = <&CPU4>;
623 clocks = <&ext_26m>; 627 clocks = <&ext_26m>;
624 clock-names = "apb_pcl 628 clock-names = "apb_pclk";
625 629
626 out-ports { !! 630 port {
627 port { !! 631 etm4_out: endpoint {
628 etm4_o !! 632 remote-endpoint =
629 !! 633 <&cluster1_funnel_in_port0>;
630 <<
631 }; <<
632 }; 634 };
633 }; 635 };
634 }; 636 };
635 637
636 etm@11940000 { 638 etm@11940000 {
637 compatible = "arm,core 639 compatible = "arm,coresight-etm4x", "arm,primecell";
638 reg = <0 0x11940000 0 640 reg = <0 0x11940000 0 0x1000>;
639 cpu = <&CPU5>; 641 cpu = <&CPU5>;
640 clocks = <&ext_26m>; 642 clocks = <&ext_26m>;
641 clock-names = "apb_pcl 643 clock-names = "apb_pclk";
642 644
643 out-ports { !! 645 port {
644 port { !! 646 etm5_out: endpoint {
645 etm5_o !! 647 remote-endpoint =
646 !! 648 <&cluster1_funnel_in_port1>;
647 <<
648 }; <<
649 }; 649 };
650 }; 650 };
651 }; 651 };
652 652
653 etm@11a40000 { 653 etm@11a40000 {
654 compatible = "arm,core 654 compatible = "arm,coresight-etm4x", "arm,primecell";
655 reg = <0 0x11a40000 0 655 reg = <0 0x11a40000 0 0x1000>;
656 cpu = <&CPU6>; 656 cpu = <&CPU6>;
657 clocks = <&ext_26m>; 657 clocks = <&ext_26m>;
658 clock-names = "apb_pcl 658 clock-names = "apb_pclk";
659 659
660 out-ports { !! 660 port {
661 port { !! 661 etm6_out: endpoint {
662 etm6_o !! 662 remote-endpoint =
663 !! 663 <&cluster1_funnel_in_port2>;
664 <<
665 }; <<
666 }; 664 };
667 }; 665 };
668 }; 666 };
669 667
670 etm@11b40000 { 668 etm@11b40000 {
671 compatible = "arm,core 669 compatible = "arm,coresight-etm4x", "arm,primecell";
672 reg = <0 0x11b40000 0 670 reg = <0 0x11b40000 0 0x1000>;
673 cpu = <&CPU7>; 671 cpu = <&CPU7>;
674 clocks = <&ext_26m>; 672 clocks = <&ext_26m>;
675 clock-names = "apb_pcl 673 clock-names = "apb_pclk";
676 674
677 out-ports { !! 675 port {
678 port { !! 676 etm7_out: endpoint {
679 etm7_o !! 677 remote-endpoint =
680 !! 678 <&cluster1_funnel_in_port3>;
681 <<
682 }; <<
683 }; 679 };
684 }; 680 };
685 }; 681 };
686 }; 682 };
687 }; 683 };
Linux® is a registered trademark of Linus Torvalds in the United States and other countries.
TOMOYO® is a registered trademark of NTT DATA CORPORATION.