1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) <<
2 /* 1 /*
3 * Spreadtrum SC9860 SoC 2 * Spreadtrum SC9860 SoC
4 * 3 *
5 * Copyright (C) 2016, Spreadtrum Communicatio 4 * Copyright (C) 2016, Spreadtrum Communications Inc.
>> 5 *
>> 6 * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 */ 7 */
7 8
8 #include <dt-bindings/interrupt-controller/arm 9 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/input/input.h> 10 #include <dt-bindings/input/input.h>
10 #include <dt-bindings/gpio/gpio.h> 11 #include <dt-bindings/gpio/gpio.h>
11 #include "whale2.dtsi" 12 #include "whale2.dtsi"
12 13
13 / { 14 / {
14 cpus { 15 cpus {
15 #address-cells = <2>; 16 #address-cells = <2>;
16 #size-cells = <0>; 17 #size-cells = <0>;
17 18
18 cpu-map { 19 cpu-map {
19 cluster0 { 20 cluster0 {
20 core0 { 21 core0 {
21 cpu = 22 cpu = <&CPU0>;
22 }; 23 };
23 core1 { 24 core1 {
24 cpu = 25 cpu = <&CPU1>;
25 }; 26 };
26 core2 { 27 core2 {
27 cpu = 28 cpu = <&CPU2>;
28 }; 29 };
29 core3 { 30 core3 {
30 cpu = 31 cpu = <&CPU3>;
31 }; 32 };
32 }; 33 };
33 34
34 cluster1 { 35 cluster1 {
35 core0 { 36 core0 {
36 cpu = 37 cpu = <&CPU4>;
37 }; 38 };
38 core1 { 39 core1 {
39 cpu = 40 cpu = <&CPU5>;
40 }; 41 };
41 core2 { 42 core2 {
42 cpu = 43 cpu = <&CPU6>;
43 }; 44 };
44 core3 { 45 core3 {
45 cpu = 46 cpu = <&CPU7>;
46 }; 47 };
47 }; 48 };
48 }; 49 };
49 50
50 CPU0: cpu@530000 { 51 CPU0: cpu@530000 {
51 device_type = "cpu"; 52 device_type = "cpu";
52 compatible = "arm,cort !! 53 compatible = "arm,cortex-a53", "arm,armv8";
53 reg = <0x0 0x530000>; 54 reg = <0x0 0x530000>;
54 enable-method = "psci" 55 enable-method = "psci";
55 cpu-idle-states = <&CO 56 cpu-idle-states = <&CORE_PD &CLUSTER_PD>;
56 }; 57 };
57 58
58 CPU1: cpu@530001 { 59 CPU1: cpu@530001 {
59 device_type = "cpu"; 60 device_type = "cpu";
60 compatible = "arm,cort !! 61 compatible = "arm,cortex-a53", "arm,armv8";
61 reg = <0x0 0x530001>; 62 reg = <0x0 0x530001>;
62 enable-method = "psci" 63 enable-method = "psci";
63 cpu-idle-states = <&CO 64 cpu-idle-states = <&CORE_PD &CLUSTER_PD>;
64 }; 65 };
65 66
66 CPU2: cpu@530002 { 67 CPU2: cpu@530002 {
67 device_type = "cpu"; 68 device_type = "cpu";
68 compatible = "arm,cort !! 69 compatible = "arm,cortex-a53", "arm,armv8";
69 reg = <0x0 0x530002>; 70 reg = <0x0 0x530002>;
70 enable-method = "psci" 71 enable-method = "psci";
71 cpu-idle-states = <&CO 72 cpu-idle-states = <&CORE_PD &CLUSTER_PD>;
72 }; 73 };
73 74
74 CPU3: cpu@530003 { 75 CPU3: cpu@530003 {
75 device_type = "cpu"; 76 device_type = "cpu";
76 compatible = "arm,cort !! 77 compatible = "arm,cortex-a53", "arm,armv8";
77 reg = <0x0 0x530003>; 78 reg = <0x0 0x530003>;
78 enable-method = "psci" 79 enable-method = "psci";
79 cpu-idle-states = <&CO 80 cpu-idle-states = <&CORE_PD &CLUSTER_PD>;
80 }; 81 };
81 82
82 CPU4: cpu@530100 { 83 CPU4: cpu@530100 {
83 device_type = "cpu"; 84 device_type = "cpu";
84 compatible = "arm,cort !! 85 compatible = "arm,cortex-a53", "arm,armv8";
85 reg = <0x0 0x530100>; 86 reg = <0x0 0x530100>;
86 enable-method = "psci" 87 enable-method = "psci";
87 cpu-idle-states = <&CO 88 cpu-idle-states = <&CORE_PD &CLUSTER_PD>;
88 }; 89 };
89 90
90 CPU5: cpu@530101 { 91 CPU5: cpu@530101 {
91 device_type = "cpu"; 92 device_type = "cpu";
92 compatible = "arm,cort !! 93 compatible = "arm,cortex-a53", "arm,armv8";
93 reg = <0x0 0x530101>; 94 reg = <0x0 0x530101>;
94 enable-method = "psci" 95 enable-method = "psci";
95 cpu-idle-states = <&CO 96 cpu-idle-states = <&CORE_PD &CLUSTER_PD>;
96 }; 97 };
97 98
98 CPU6: cpu@530102 { 99 CPU6: cpu@530102 {
99 device_type = "cpu"; 100 device_type = "cpu";
100 compatible = "arm,cort !! 101 compatible = "arm,cortex-a53", "arm,armv8";
101 reg = <0x0 0x530102>; 102 reg = <0x0 0x530102>;
102 enable-method = "psci" 103 enable-method = "psci";
103 cpu-idle-states = <&CO 104 cpu-idle-states = <&CORE_PD &CLUSTER_PD>;
104 }; 105 };
105 106
106 CPU7: cpu@530103 { 107 CPU7: cpu@530103 {
107 device_type = "cpu"; 108 device_type = "cpu";
108 compatible = "arm,cort !! 109 compatible = "arm,cortex-a53", "arm,armv8";
109 reg = <0x0 0x530103>; 110 reg = <0x0 0x530103>;
110 enable-method = "psci" 111 enable-method = "psci";
111 cpu-idle-states = <&CO 112 cpu-idle-states = <&CORE_PD &CLUSTER_PD>;
112 }; 113 };
113 }; 114 };
114 115
115 idle-states { !! 116 idle-states{
116 entry-method = "psci"; !! 117 entry-method = "arm,psci";
117 118
118 CORE_PD: core_pd { 119 CORE_PD: core_pd {
119 compatible = "arm,idle 120 compatible = "arm,idle-state";
120 entry-latency-us = <10 121 entry-latency-us = <1000>;
121 exit-latency-us = <700 122 exit-latency-us = <700>;
122 min-residency-us = <25 123 min-residency-us = <2500>;
123 local-timer-stop; 124 local-timer-stop;
124 arm,psci-suspend-param 125 arm,psci-suspend-param = <0x00010002>;
125 }; 126 };
126 127
127 CLUSTER_PD: cluster_pd { 128 CLUSTER_PD: cluster_pd {
128 compatible = "arm,idle 129 compatible = "arm,idle-state";
129 entry-latency-us = <10 130 entry-latency-us = <1000>;
130 exit-latency-us = <100 131 exit-latency-us = <1000>;
131 min-residency-us = <30 132 min-residency-us = <3000>;
132 local-timer-stop; 133 local-timer-stop;
133 arm,psci-suspend-param 134 arm,psci-suspend-param = <0x01010003>;
134 }; 135 };
135 }; 136 };
136 137
>> 138 gic: interrupt-controller@12001000 {
>> 139 compatible = "arm,gic-400";
>> 140 reg = <0 0x12001000 0 0x1000>,
>> 141 <0 0x12002000 0 0x2000>,
>> 142 <0 0x12004000 0 0x2000>,
>> 143 <0 0x12006000 0 0x2000>;
>> 144 #interrupt-cells = <3>;
>> 145 interrupt-controller;
>> 146 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8)
>> 147 | IRQ_TYPE_LEVEL_HIGH)>;
>> 148 };
>> 149
137 psci { 150 psci {
138 compatible = "arm,psci-0.2"; 151 compatible = "arm,psci-0.2";
139 method = "smc"; 152 method = "smc";
140 }; 153 };
141 154
142 timer { 155 timer {
143 compatible = "arm,armv8-timer" 156 compatible = "arm,armv8-timer";
144 interrupts = <GIC_PPI 13 (GIC_ 157 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8)
145 | IRQ 158 | IRQ_TYPE_LEVEL_LOW)>,
146 <GIC_PPI 14 (GIC_ 159 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8)
147 | IRQ 160 | IRQ_TYPE_LEVEL_LOW)>,
148 <GIC_PPI 11 (GIC_ 161 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8)
149 | IRQ 162 | IRQ_TYPE_LEVEL_LOW)>,
150 <GIC_PPI 10 (GIC_ 163 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8)
151 | IRQ 164 | IRQ_TYPE_LEVEL_LOW)>;
152 }; 165 };
153 166
154 pmu { 167 pmu {
155 compatible = "arm,cortex-a53-p !! 168 compatible = "arm,cortex-a53-pmu", "arm,armv8-pmuv3";
156 interrupts = <GIC_SPI 122 IRQ_ 169 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
157 <GIC_SPI 123 IRQ_ 170 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
158 <GIC_SPI 124 IRQ_ 171 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
159 <GIC_SPI 125 IRQ_ 172 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
160 <GIC_SPI 154 IRQ_ 173 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
161 <GIC_SPI 155 IRQ_ 174 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
162 <GIC_SPI 156 IRQ_ 175 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>,
163 <GIC_SPI 157 IRQ_ 176 <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
164 interrupt-affinity = <&CPU0>, 177 interrupt-affinity = <&CPU0>,
165 <&CPU1>, 178 <&CPU1>,
166 <&CPU2>, 179 <&CPU2>,
167 <&CPU3>, 180 <&CPU3>,
168 <&CPU4>, 181 <&CPU4>,
169 <&CPU5>, 182 <&CPU5>,
170 <&CPU6>, 183 <&CPU6>,
171 <&CPU7>; 184 <&CPU7>;
172 }; 185 };
173 186
174 soc { 187 soc {
175 gic: interrupt-controller@1200 <<
176 compatible = "arm,gic- <<
177 reg = <0 0x12001000 0 <<
178 <0 0x12002000 0 <<
179 <0 0x12004000 0 <<
180 <0 0x12006000 0 <<
181 #interrupt-cells = <3> <<
182 interrupt-controller; <<
183 interrupts = <GIC_PPI <<
184 <<
185 }; <<
186 <<
187 pmu_gate: pmu-gate { 188 pmu_gate: pmu-gate {
188 compatible = "sprd,sc9 189 compatible = "sprd,sc9860-pmu-gate";
189 sprd,syscon = <&pmu_re 190 sprd,syscon = <&pmu_regs>; /* 0x402b0000 */
190 clocks = <&ext_26m>; 191 clocks = <&ext_26m>;
191 #clock-cells = <1>; 192 #clock-cells = <1>;
192 }; 193 };
193 194
194 pll: pll { 195 pll: pll {
195 compatible = "sprd,sc9 196 compatible = "sprd,sc9860-pll";
196 sprd,syscon = <&ana_re 197 sprd,syscon = <&ana_regs>; /* 0x40400000 */
197 clocks = <&pmu_gate 0> 198 clocks = <&pmu_gate 0>;
198 #clock-cells = <1>; 199 #clock-cells = <1>;
199 }; 200 };
200 201
201 ap_clk: clock-controller@20000 202 ap_clk: clock-controller@20000000 {
202 compatible = "sprd,sc9 203 compatible = "sprd,sc9860-ap-clk";
203 reg = <0 0x20000000 0 204 reg = <0 0x20000000 0 0x400>;
204 clocks = <&ext_26m>, < 205 clocks = <&ext_26m>, <&pll 0>,
205 <&pmu_gate 0> 206 <&pmu_gate 0>;
206 #clock-cells = <1>; 207 #clock-cells = <1>;
207 }; 208 };
208 209
209 aon_prediv: aon-prediv@402d000 !! 210 aon_prediv: aon-prediv {
210 compatible = "sprd,sc9 211 compatible = "sprd,sc9860-aon-prediv";
211 reg = <0 0x402d0000 0 212 reg = <0 0x402d0000 0 0x400>;
212 clocks = <&ext_26m>, < 213 clocks = <&ext_26m>, <&pll 0>,
213 <&pmu_gate 0> 214 <&pmu_gate 0>;
214 #clock-cells = <1>; 215 #clock-cells = <1>;
215 }; 216 };
216 217
217 apahb_gate: apahb-gate { 218 apahb_gate: apahb-gate {
218 compatible = "sprd,sc9 219 compatible = "sprd,sc9860-apahb-gate";
219 sprd,syscon = <&ap_ahb 220 sprd,syscon = <&ap_ahb_regs>; /* 0x20210000 */
220 clocks = <&aon_prediv 221 clocks = <&aon_prediv 0>;
221 #clock-cells = <1>; 222 #clock-cells = <1>;
222 }; 223 };
223 224
224 aon_gate: aon-gate { 225 aon_gate: aon-gate {
225 compatible = "sprd,sc9 226 compatible = "sprd,sc9860-aon-gate";
226 sprd,syscon = <&aon_re 227 sprd,syscon = <&aon_regs>; /* 0x402e0000 */
227 clocks = <&aon_prediv 228 clocks = <&aon_prediv 0>;
228 #clock-cells = <1>; 229 #clock-cells = <1>;
229 }; 230 };
230 231
231 aonsecure_clk: clock-controlle 232 aonsecure_clk: clock-controller@40880000 {
232 compatible = "sprd,sc9 233 compatible = "sprd,sc9860-aonsecure-clk";
233 reg = <0 0x40880000 0 234 reg = <0 0x40880000 0 0x400>;
234 clocks = <&ext_26m>, < 235 clocks = <&ext_26m>, <&pll 0>;
235 #clock-cells = <1>; 236 #clock-cells = <1>;
236 }; 237 };
237 238
238 agcp_gate: agcp-gate { 239 agcp_gate: agcp-gate {
239 compatible = "sprd,sc9 240 compatible = "sprd,sc9860-agcp-gate";
240 sprd,syscon = <&agcp_r 241 sprd,syscon = <&agcp_regs>; /* 0x415e0000 */
241 clocks = <&aon_prediv 242 clocks = <&aon_prediv 0>;
242 #clock-cells = <1>; 243 #clock-cells = <1>;
243 }; 244 };
244 245
245 gpu_clk: clock-controller@6020 246 gpu_clk: clock-controller@60200000 {
246 compatible = "sprd,sc9 247 compatible = "sprd,sc9860-gpu-clk";
247 reg = <0 0x60200000 0 248 reg = <0 0x60200000 0 0x400>;
248 clocks = <&pll 0>; 249 clocks = <&pll 0>;
249 #clock-cells = <1>; 250 #clock-cells = <1>;
250 }; 251 };
251 252
252 vsp_clk: clock-controller@6100 253 vsp_clk: clock-controller@61000000 {
253 compatible = "sprd,sc9 254 compatible = "sprd,sc9860-vsp-clk";
254 reg = <0 0x61000000 0 255 reg = <0 0x61000000 0 0x400>;
255 clocks = <&ext_26m>, < 256 clocks = <&ext_26m>, <&pll 0>;
256 #clock-cells = <1>; 257 #clock-cells = <1>;
257 }; 258 };
258 259
259 vsp_gate: vsp-gate { 260 vsp_gate: vsp-gate {
260 compatible = "sprd,sc9 261 compatible = "sprd,sc9860-vsp-gate";
261 sprd,syscon = <&vsp_re 262 sprd,syscon = <&vsp_regs>; /* 0x61100000 */
262 clocks = <&vsp_clk 0>; 263 clocks = <&vsp_clk 0>;
263 #clock-cells = <1>; 264 #clock-cells = <1>;
264 }; 265 };
265 266
266 cam_clk: clock-controller@6200 267 cam_clk: clock-controller@62000000 {
267 compatible = "sprd,sc9 268 compatible = "sprd,sc9860-cam-clk";
268 reg = <0 0x62000000 0 269 reg = <0 0x62000000 0 0x4000>;
269 clocks = <&ext_26m>, < 270 clocks = <&ext_26m>, <&pll 0>;
270 #clock-cells = <1>; 271 #clock-cells = <1>;
271 }; 272 };
272 273
273 cam_gate: cam-gate { 274 cam_gate: cam-gate {
274 compatible = "sprd,sc9 275 compatible = "sprd,sc9860-cam-gate";
275 sprd,syscon = <&cam_re 276 sprd,syscon = <&cam_regs>; /* 0x62100000 */
276 clocks = <&cam_clk 0>; 277 clocks = <&cam_clk 0>;
277 #clock-cells = <1>; 278 #clock-cells = <1>;
278 }; 279 };
279 280
280 disp_clk: clock-controller@630 281 disp_clk: clock-controller@63000000 {
281 compatible = "sprd,sc9 282 compatible = "sprd,sc9860-disp-clk";
282 reg = <0 0x63000000 0 283 reg = <0 0x63000000 0 0x400>;
283 clocks = <&ext_26m>, < 284 clocks = <&ext_26m>, <&pll 0>;
284 #clock-cells = <1>; 285 #clock-cells = <1>;
285 }; 286 };
286 287
287 disp_gate: disp-gate { 288 disp_gate: disp-gate {
288 compatible = "sprd,sc9 289 compatible = "sprd,sc9860-disp-gate";
289 sprd,syscon = <&disp_r 290 sprd,syscon = <&disp_regs>; /* 0x63100000 */
290 clocks = <&disp_clk 0> 291 clocks = <&disp_clk 0>;
291 #clock-cells = <1>; 292 #clock-cells = <1>;
292 }; 293 };
293 294
294 apapb_gate: apapb-gate { 295 apapb_gate: apapb-gate {
295 compatible = "sprd,sc9 296 compatible = "sprd,sc9860-apapb-gate";
296 sprd,syscon = <&ap_apb 297 sprd,syscon = <&ap_apb_regs>; /* 0x70b00000 */
297 clocks = <&ap_clk 0>; 298 clocks = <&ap_clk 0>;
298 #clock-cells = <1>; 299 #clock-cells = <1>;
299 }; 300 };
300 301
301 funnel@10001000 { /* SoC Funne 302 funnel@10001000 { /* SoC Funnel */
302 compatible = "arm,core !! 303 compatible = "arm,coresight-funnel", "arm,primecell";
303 reg = <0 0x10001000 0 304 reg = <0 0x10001000 0 0x1000>;
304 clocks = <&ext_26m>; 305 clocks = <&ext_26m>;
305 clock-names = "apb_pcl 306 clock-names = "apb_pclk";
306 out-ports { !! 307 ports {
307 port { !! 308 #address-cells = <1>;
>> 309 #size-cells = <0>;
>> 310
>> 311 port@0 {
>> 312 reg = <0>;
308 soc_fu 313 soc_funnel_out_port: endpoint {
309 314 remote-endpoint = <&etb_in>;
310 }; 315 };
311 }; 316 };
312 }; <<
313 <<
314 in-ports { <<
315 #address-cells <<
316 #size-cells = <<
317 317
318 port@0 { !! 318 port@1 {
319 reg = 319 reg = <0>;
320 soc_fu 320 soc_funnel_in_port0: endpoint {
>> 321 slave-mode;
321 322 remote-endpoint =
322 323 <&main_funnel_out_port>;
323 }; 324 };
324 }; 325 };
325 326
326 port@4 { !! 327 port@2 {
327 reg = 328 reg = <4>;
328 soc_fu 329 soc_funnel_in_port1: endpoint {
>> 330 slave-mode;
329 331 remote-endpoint =
330 332 <&stm_out_port>;
331 }; 333 };
332 }; 334 };
333 }; 335 };
334 }; 336 };
335 337
336 etb@10003000 { 338 etb@10003000 {
337 compatible = "arm,core 339 compatible = "arm,coresight-tmc", "arm,primecell";
338 reg = <0 0x10003000 0 340 reg = <0 0x10003000 0 0x1000>;
339 clocks = <&ext_26m>; 341 clocks = <&ext_26m>;
340 clock-names = "apb_pcl 342 clock-names = "apb_pclk";
341 out-ports { !! 343 port {
342 port { !! 344 etb_in: endpoint {
343 etb_in !! 345 slave-mode;
344 !! 346 remote-endpoint =
345 !! 347 <&soc_funnel_out_port>;
346 }; <<
347 }; 348 };
348 }; 349 };
349 }; 350 };
350 351
351 stm@10006000 { 352 stm@10006000 {
352 compatible = "arm,core 353 compatible = "arm,coresight-stm", "arm,primecell";
353 reg = <0 0x10006000 0 354 reg = <0 0x10006000 0 0x1000>,
354 <0 0x01000000 0 355 <0 0x01000000 0 0x180000>;
355 reg-names = "stm-base" 356 reg-names = "stm-base", "stm-stimulus-base";
356 clocks = <&ext_26m>; 357 clocks = <&ext_26m>;
357 clock-names = "apb_pcl 358 clock-names = "apb_pclk";
358 out-ports { !! 359 port {
359 port { !! 360 stm_out_port: endpoint {
360 stm_ou !! 361 remote-endpoint =
361 !! 362 <&soc_funnel_in_port1>;
362 <<
363 }; <<
364 }; 363 };
365 }; 364 };
366 }; 365 };
367 366
368 funnel@11001000 { /* Cluster0 367 funnel@11001000 { /* Cluster0 Funnel */
369 compatible = "arm,core !! 368 compatible = "arm,coresight-funnel", "arm,primecell";
370 reg = <0 0x11001000 0 369 reg = <0 0x11001000 0 0x1000>;
371 clocks = <&ext_26m>; 370 clocks = <&ext_26m>;
372 clock-names = "apb_pcl 371 clock-names = "apb_pclk";
373 out-ports { !! 372 ports {
374 port { !! 373 #address-cells = <1>;
>> 374 #size-cells = <0>;
>> 375
>> 376 port@0 {
>> 377 reg = <0>;
375 cluste 378 cluster0_funnel_out_port: endpoint {
376 379 remote-endpoint =
377 380 <&cluster0_etf_in>;
378 }; 381 };
379 }; 382 };
380 }; <<
381 <<
382 in-ports { <<
383 #address-cells <<
384 #size-cells = <<
385 383
386 port@0 { !! 384 port@1 {
387 reg = 385 reg = <0>;
388 cluste 386 cluster0_funnel_in_port0: endpoint {
>> 387 slave-mode;
389 388 remote-endpoint = <&etm0_out>;
390 }; 389 };
391 }; 390 };
392 391
393 port@1 { !! 392 port@2 {
394 reg = 393 reg = <1>;
395 cluste 394 cluster0_funnel_in_port1: endpoint {
>> 395 slave-mode;
396 396 remote-endpoint = <&etm1_out>;
397 }; 397 };
398 }; 398 };
399 399
400 port@2 { !! 400 port@3 {
401 reg = 401 reg = <2>;
402 cluste 402 cluster0_funnel_in_port2: endpoint {
>> 403 slave-mode;
403 404 remote-endpoint = <&etm2_out>;
404 }; 405 };
405 }; 406 };
406 407
407 port@4 { 408 port@4 {
408 reg = 409 reg = <4>;
409 cluste 410 cluster0_funnel_in_port3: endpoint {
>> 411 slave-mode;
410 412 remote-endpoint = <&etm3_out>;
411 }; 413 };
412 }; 414 };
413 }; 415 };
414 }; 416 };
415 417
416 funnel@11002000 { /* Cluster1 418 funnel@11002000 { /* Cluster1 Funnel */
417 compatible = "arm,core !! 419 compatible = "arm,coresight-funnel", "arm,primecell";
418 reg = <0 0x11002000 0 420 reg = <0 0x11002000 0 0x1000>;
419 clocks = <&ext_26m>; 421 clocks = <&ext_26m>;
420 clock-names = "apb_pcl 422 clock-names = "apb_pclk";
421 out-ports { !! 423 ports {
422 port { !! 424 #address-cells = <1>;
>> 425 #size-cells = <0>;
>> 426
>> 427 port@0 {
>> 428 reg = <0>;
423 cluste 429 cluster1_funnel_out_port: endpoint {
424 430 remote-endpoint =
425 431 <&cluster1_etf_in>;
426 }; 432 };
427 }; 433 };
428 }; <<
429 434
430 in-ports { !! 435 port@1 {
431 #address-cells <<
432 #size-cells = <<
433 <<
434 port@0 { <<
435 reg = 436 reg = <0>;
436 cluste 437 cluster1_funnel_in_port0: endpoint {
>> 438 slave-mode;
437 439 remote-endpoint = <&etm4_out>;
438 }; 440 };
439 }; 441 };
440 442
441 port@1 { !! 443 port@2 {
442 reg = 444 reg = <1>;
443 cluste 445 cluster1_funnel_in_port1: endpoint {
>> 446 slave-mode;
444 447 remote-endpoint = <&etm5_out>;
445 }; 448 };
446 }; 449 };
447 450
448 port@2 { !! 451 port@3 {
449 reg = 452 reg = <2>;
450 cluste 453 cluster1_funnel_in_port2: endpoint {
>> 454 slave-mode;
451 455 remote-endpoint = <&etm6_out>;
452 }; 456 };
453 }; 457 };
454 458
455 port@3 { !! 459 port@4 {
456 reg = 460 reg = <3>;
457 cluste 461 cluster1_funnel_in_port3: endpoint {
>> 462 slave-mode;
458 463 remote-endpoint = <&etm7_out>;
459 }; 464 };
460 }; 465 };
461 }; 466 };
462 }; 467 };
463 468
464 etf@11003000 { /* ETF on Clus 469 etf@11003000 { /* ETF on Cluster0 */
465 compatible = "arm,core 470 compatible = "arm,coresight-tmc", "arm,primecell";
466 reg = <0 0x11003000 0 471 reg = <0 0x11003000 0 0x1000>;
467 clocks = <&ext_26m>; 472 clocks = <&ext_26m>;
468 clock-names = "apb_pcl 473 clock-names = "apb_pclk";
469 474
470 out-ports { !! 475 ports {
471 port { !! 476 #address-cells = <1>;
>> 477 #size-cells = <0>;
>> 478
>> 479 port@0 {
>> 480 reg = <0>;
472 cluste 481 cluster0_etf_out: endpoint {
473 482 remote-endpoint =
474 483 <&main_funnel_in_port0>;
475 }; 484 };
476 }; 485 };
477 }; <<
478 486
479 in-ports { !! 487 port@1 {
480 port { !! 488 reg = <0>;
481 cluste 489 cluster0_etf_in: endpoint {
>> 490 slave-mode;
482 491 remote-endpoint =
483 492 <&cluster0_funnel_out_port>;
484 }; 493 };
485 }; 494 };
486 }; 495 };
487 }; 496 };
488 497
489 etf@11004000 { /* ETF on Clust 498 etf@11004000 { /* ETF on Cluster1 */
490 compatible = "arm,core 499 compatible = "arm,coresight-tmc", "arm,primecell";
491 reg = <0 0x11004000 0 500 reg = <0 0x11004000 0 0x1000>;
492 clocks = <&ext_26m>; 501 clocks = <&ext_26m>;
493 clock-names = "apb_pcl 502 clock-names = "apb_pclk";
494 503
495 out-ports { !! 504 ports {
496 port { !! 505 #address-cells = <1>;
>> 506 #size-cells = <0>;
>> 507
>> 508 port@0 {
>> 509 reg = <0>;
497 cluste 510 cluster1_etf_out: endpoint {
498 511 remote-endpoint =
499 512 <&main_funnel_in_port1>;
500 }; 513 };
501 }; 514 };
502 }; <<
503 515
504 in-ports { !! 516 port@1 {
505 port { !! 517 reg = <0>;
506 cluste 518 cluster1_etf_in: endpoint {
>> 519 slave-mode;
507 520 remote-endpoint =
508 521 <&cluster1_funnel_out_port>;
509 }; 522 };
510 }; 523 };
511 }; 524 };
512 }; 525 };
513 526
514 funnel@11005000 { /* Main Funn 527 funnel@11005000 { /* Main Funnel */
515 compatible = "arm,core !! 528 compatible = "arm,coresight-funnel", "arm,primecell";
516 reg = <0 0x11005000 0 529 reg = <0 0x11005000 0 0x1000>;
517 clocks = <&ext_26m>; 530 clocks = <&ext_26m>;
518 clock-names = "apb_pcl 531 clock-names = "apb_pclk";
519 532
520 out-ports { !! 533 ports {
521 port { !! 534 #address-cells = <1>;
>> 535 #size-cells = <0>;
>> 536
>> 537 port@0 {
>> 538 reg = <0>;
522 main_f 539 main_funnel_out_port: endpoint {
523 540 remote-endpoint =
524 541 <&soc_funnel_in_port0>;
525 }; 542 };
526 }; 543 };
527 }; <<
528 <<
529 in-ports { <<
530 #address-cells <<
531 #size-cells = <<
532 544
533 port@0 { !! 545 port@1 {
534 reg = 546 reg = <0>;
535 main_f 547 main_funnel_in_port0: endpoint {
>> 548 slave-mode;
536 549 remote-endpoint =
537 550 <&cluster0_etf_out>;
538 }; 551 };
539 }; 552 };
540 553
541 port@1 { !! 554 port@2 {
542 reg = 555 reg = <1>;
543 main_f 556 main_funnel_in_port1: endpoint {
>> 557 slave-mode;
544 558 remote-endpoint =
545 559 <&cluster1_etf_out>;
546 }; 560 };
547 }; 561 };
548 }; 562 };
549 }; 563 };
550 564
551 etm@11440000 { 565 etm@11440000 {
552 compatible = "arm,core 566 compatible = "arm,coresight-etm4x", "arm,primecell";
553 reg = <0 0x11440000 0 567 reg = <0 0x11440000 0 0x1000>;
554 cpu = <&CPU0>; 568 cpu = <&CPU0>;
555 clocks = <&ext_26m>; 569 clocks = <&ext_26m>;
556 clock-names = "apb_pcl 570 clock-names = "apb_pclk";
557 571
558 out-ports { !! 572 port {
559 port { !! 573 etm0_out: endpoint {
560 etm0_o !! 574 remote-endpoint =
561 !! 575 <&cluster0_funnel_in_port0>;
562 <<
563 }; <<
564 }; 576 };
565 }; 577 };
566 }; 578 };
567 579
568 etm@11540000 { 580 etm@11540000 {
569 compatible = "arm,core 581 compatible = "arm,coresight-etm4x", "arm,primecell";
570 reg = <0 0x11540000 0 582 reg = <0 0x11540000 0 0x1000>;
571 cpu = <&CPU1>; 583 cpu = <&CPU1>;
572 clocks = <&ext_26m>; 584 clocks = <&ext_26m>;
573 clock-names = "apb_pcl 585 clock-names = "apb_pclk";
574 586
575 out-ports { !! 587 port {
576 port { !! 588 etm1_out: endpoint {
577 etm1_o !! 589 remote-endpoint =
578 !! 590 <&cluster0_funnel_in_port1>;
579 <<
580 }; <<
581 }; 591 };
582 }; 592 };
583 }; 593 };
584 594
585 etm@11640000 { 595 etm@11640000 {
586 compatible = "arm,core 596 compatible = "arm,coresight-etm4x", "arm,primecell";
587 reg = <0 0x11640000 0 597 reg = <0 0x11640000 0 0x1000>;
588 cpu = <&CPU2>; 598 cpu = <&CPU2>;
589 clocks = <&ext_26m>; 599 clocks = <&ext_26m>;
590 clock-names = "apb_pcl 600 clock-names = "apb_pclk";
591 601
592 out-ports { !! 602 port {
593 port { !! 603 etm2_out: endpoint {
594 etm2_o !! 604 remote-endpoint =
595 !! 605 <&cluster0_funnel_in_port2>;
596 <<
597 }; <<
598 }; 606 };
599 }; 607 };
600 }; 608 };
601 609
602 etm@11740000 { 610 etm@11740000 {
603 compatible = "arm,core 611 compatible = "arm,coresight-etm4x", "arm,primecell";
604 reg = <0 0x11740000 0 612 reg = <0 0x11740000 0 0x1000>;
605 cpu = <&CPU3>; 613 cpu = <&CPU3>;
606 clocks = <&ext_26m>; 614 clocks = <&ext_26m>;
607 clock-names = "apb_pcl 615 clock-names = "apb_pclk";
608 616
609 out-ports { !! 617 port {
610 port { !! 618 etm3_out: endpoint {
611 etm3_o !! 619 remote-endpoint =
612 !! 620 <&cluster0_funnel_in_port3>;
613 <<
614 }; <<
615 }; 621 };
616 }; 622 };
617 }; 623 };
618 624
619 etm@11840000 { 625 etm@11840000 {
620 compatible = "arm,core 626 compatible = "arm,coresight-etm4x", "arm,primecell";
621 reg = <0 0x11840000 0 627 reg = <0 0x11840000 0 0x1000>;
622 cpu = <&CPU4>; 628 cpu = <&CPU4>;
623 clocks = <&ext_26m>; 629 clocks = <&ext_26m>;
624 clock-names = "apb_pcl 630 clock-names = "apb_pclk";
625 631
626 out-ports { !! 632 port {
627 port { !! 633 etm4_out: endpoint {
628 etm4_o !! 634 remote-endpoint =
629 !! 635 <&cluster1_funnel_in_port0>;
630 <<
631 }; <<
632 }; 636 };
633 }; 637 };
634 }; 638 };
635 639
636 etm@11940000 { 640 etm@11940000 {
637 compatible = "arm,core 641 compatible = "arm,coresight-etm4x", "arm,primecell";
638 reg = <0 0x11940000 0 642 reg = <0 0x11940000 0 0x1000>;
639 cpu = <&CPU5>; 643 cpu = <&CPU5>;
640 clocks = <&ext_26m>; 644 clocks = <&ext_26m>;
641 clock-names = "apb_pcl 645 clock-names = "apb_pclk";
642 646
643 out-ports { !! 647 port {
644 port { !! 648 etm5_out: endpoint {
645 etm5_o !! 649 remote-endpoint =
646 !! 650 <&cluster1_funnel_in_port1>;
647 <<
648 }; <<
649 }; 651 };
650 }; 652 };
651 }; 653 };
652 654
653 etm@11a40000 { 655 etm@11a40000 {
654 compatible = "arm,core 656 compatible = "arm,coresight-etm4x", "arm,primecell";
655 reg = <0 0x11a40000 0 657 reg = <0 0x11a40000 0 0x1000>;
656 cpu = <&CPU6>; 658 cpu = <&CPU6>;
657 clocks = <&ext_26m>; 659 clocks = <&ext_26m>;
658 clock-names = "apb_pcl 660 clock-names = "apb_pclk";
659 661
660 out-ports { !! 662 port {
661 port { !! 663 etm6_out: endpoint {
662 etm6_o !! 664 remote-endpoint =
663 !! 665 <&cluster1_funnel_in_port2>;
664 <<
665 }; <<
666 }; 666 };
667 }; 667 };
668 }; 668 };
669 669
670 etm@11b40000 { 670 etm@11b40000 {
671 compatible = "arm,core 671 compatible = "arm,coresight-etm4x", "arm,primecell";
672 reg = <0 0x11b40000 0 672 reg = <0 0x11b40000 0 0x1000>;
673 cpu = <&CPU7>; 673 cpu = <&CPU7>;
674 clocks = <&ext_26m>; 674 clocks = <&ext_26m>;
675 clock-names = "apb_pcl 675 clock-names = "apb_pclk";
676 676
677 out-ports { !! 677 port {
678 port { !! 678 etm7_out: endpoint {
679 etm7_o !! 679 remote-endpoint =
680 !! 680 <&cluster1_funnel_in_port3>;
681 <<
682 }; <<
683 }; 681 };
>> 682 };
>> 683 };
>> 684
>> 685 gpio-keys {
>> 686 compatible = "gpio-keys";
>> 687
>> 688 key-volumedown {
>> 689 label = "Volume Down Key";
>> 690 linux,code = <KEY_VOLUMEDOWN>;
>> 691 gpios = <&eic_debounce 2 GPIO_ACTIVE_LOW>;
>> 692 debounce-interval = <2>;
>> 693 wakeup-source;
>> 694 };
>> 695
>> 696 key-volumeup {
>> 697 label = "Volume Up Key";
>> 698 linux,code = <KEY_VOLUMEUP>;
>> 699 gpios = <&pmic_eic 10 GPIO_ACTIVE_HIGH>;
>> 700 debounce-interval = <2>;
>> 701 wakeup-source;
>> 702 };
>> 703
>> 704 key-power {
>> 705 label = "Power Key";
>> 706 linux,code = <KEY_POWER>;
>> 707 gpios = <&pmic_eic 1 GPIO_ACTIVE_HIGH>;
>> 708 debounce-interval = <2>;
>> 709 wakeup-source;
684 }; 710 };
685 }; 711 };
686 }; 712 };
687 }; 713 };
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