1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /*
3 * Spreadtrum SC9860 SoC
4 *
5 * Copyright (C) 2016, Spreadtrum Communicatio
6 */
7
8 #include <dt-bindings/interrupt-controller/arm
9 #include <dt-bindings/input/input.h>
10 #include <dt-bindings/gpio/gpio.h>
11 #include "whale2.dtsi"
12
13 / {
14 cpus {
15 #address-cells = <2>;
16 #size-cells = <0>;
17
18 cpu-map {
19 cluster0 {
20 core0 {
21 cpu =
22 };
23 core1 {
24 cpu =
25 };
26 core2 {
27 cpu =
28 };
29 core3 {
30 cpu =
31 };
32 };
33
34 cluster1 {
35 core0 {
36 cpu =
37 };
38 core1 {
39 cpu =
40 };
41 core2 {
42 cpu =
43 };
44 core3 {
45 cpu =
46 };
47 };
48 };
49
50 CPU0: cpu@530000 {
51 device_type = "cpu";
52 compatible = "arm,cort
53 reg = <0x0 0x530000>;
54 enable-method = "psci"
55 cpu-idle-states = <&CO
56 };
57
58 CPU1: cpu@530001 {
59 device_type = "cpu";
60 compatible = "arm,cort
61 reg = <0x0 0x530001>;
62 enable-method = "psci"
63 cpu-idle-states = <&CO
64 };
65
66 CPU2: cpu@530002 {
67 device_type = "cpu";
68 compatible = "arm,cort
69 reg = <0x0 0x530002>;
70 enable-method = "psci"
71 cpu-idle-states = <&CO
72 };
73
74 CPU3: cpu@530003 {
75 device_type = "cpu";
76 compatible = "arm,cort
77 reg = <0x0 0x530003>;
78 enable-method = "psci"
79 cpu-idle-states = <&CO
80 };
81
82 CPU4: cpu@530100 {
83 device_type = "cpu";
84 compatible = "arm,cort
85 reg = <0x0 0x530100>;
86 enable-method = "psci"
87 cpu-idle-states = <&CO
88 };
89
90 CPU5: cpu@530101 {
91 device_type = "cpu";
92 compatible = "arm,cort
93 reg = <0x0 0x530101>;
94 enable-method = "psci"
95 cpu-idle-states = <&CO
96 };
97
98 CPU6: cpu@530102 {
99 device_type = "cpu";
100 compatible = "arm,cort
101 reg = <0x0 0x530102>;
102 enable-method = "psci"
103 cpu-idle-states = <&CO
104 };
105
106 CPU7: cpu@530103 {
107 device_type = "cpu";
108 compatible = "arm,cort
109 reg = <0x0 0x530103>;
110 enable-method = "psci"
111 cpu-idle-states = <&CO
112 };
113 };
114
115 idle-states {
116 entry-method = "psci";
117
118 CORE_PD: core_pd {
119 compatible = "arm,idle
120 entry-latency-us = <10
121 exit-latency-us = <700
122 min-residency-us = <25
123 local-timer-stop;
124 arm,psci-suspend-param
125 };
126
127 CLUSTER_PD: cluster_pd {
128 compatible = "arm,idle
129 entry-latency-us = <10
130 exit-latency-us = <100
131 min-residency-us = <30
132 local-timer-stop;
133 arm,psci-suspend-param
134 };
135 };
136
137 psci {
138 compatible = "arm,psci-0.2";
139 method = "smc";
140 };
141
142 timer {
143 compatible = "arm,armv8-timer"
144 interrupts = <GIC_PPI 13 (GIC_
145 | IRQ
146 <GIC_PPI 14 (GIC_
147 | IRQ
148 <GIC_PPI 11 (GIC_
149 | IRQ
150 <GIC_PPI 10 (GIC_
151 | IRQ
152 };
153
154 pmu {
155 compatible = "arm,cortex-a53-p
156 interrupts = <GIC_SPI 122 IRQ_
157 <GIC_SPI 123 IRQ_
158 <GIC_SPI 124 IRQ_
159 <GIC_SPI 125 IRQ_
160 <GIC_SPI 154 IRQ_
161 <GIC_SPI 155 IRQ_
162 <GIC_SPI 156 IRQ_
163 <GIC_SPI 157 IRQ_
164 interrupt-affinity = <&CPU0>,
165 <&CPU1>,
166 <&CPU2>,
167 <&CPU3>,
168 <&CPU4>,
169 <&CPU5>,
170 <&CPU6>,
171 <&CPU7>;
172 };
173
174 soc {
175 gic: interrupt-controller@1200
176 compatible = "arm,gic-
177 reg = <0 0x12001000 0
178 <0 0x12002000 0
179 <0 0x12004000 0
180 <0 0x12006000 0
181 #interrupt-cells = <3>
182 interrupt-controller;
183 interrupts = <GIC_PPI
184
185 };
186
187 pmu_gate: pmu-gate {
188 compatible = "sprd,sc9
189 sprd,syscon = <&pmu_re
190 clocks = <&ext_26m>;
191 #clock-cells = <1>;
192 };
193
194 pll: pll {
195 compatible = "sprd,sc9
196 sprd,syscon = <&ana_re
197 clocks = <&pmu_gate 0>
198 #clock-cells = <1>;
199 };
200
201 ap_clk: clock-controller@20000
202 compatible = "sprd,sc9
203 reg = <0 0x20000000 0
204 clocks = <&ext_26m>, <
205 <&pmu_gate 0>
206 #clock-cells = <1>;
207 };
208
209 aon_prediv: aon-prediv@402d000
210 compatible = "sprd,sc9
211 reg = <0 0x402d0000 0
212 clocks = <&ext_26m>, <
213 <&pmu_gate 0>
214 #clock-cells = <1>;
215 };
216
217 apahb_gate: apahb-gate {
218 compatible = "sprd,sc9
219 sprd,syscon = <&ap_ahb
220 clocks = <&aon_prediv
221 #clock-cells = <1>;
222 };
223
224 aon_gate: aon-gate {
225 compatible = "sprd,sc9
226 sprd,syscon = <&aon_re
227 clocks = <&aon_prediv
228 #clock-cells = <1>;
229 };
230
231 aonsecure_clk: clock-controlle
232 compatible = "sprd,sc9
233 reg = <0 0x40880000 0
234 clocks = <&ext_26m>, <
235 #clock-cells = <1>;
236 };
237
238 agcp_gate: agcp-gate {
239 compatible = "sprd,sc9
240 sprd,syscon = <&agcp_r
241 clocks = <&aon_prediv
242 #clock-cells = <1>;
243 };
244
245 gpu_clk: clock-controller@6020
246 compatible = "sprd,sc9
247 reg = <0 0x60200000 0
248 clocks = <&pll 0>;
249 #clock-cells = <1>;
250 };
251
252 vsp_clk: clock-controller@6100
253 compatible = "sprd,sc9
254 reg = <0 0x61000000 0
255 clocks = <&ext_26m>, <
256 #clock-cells = <1>;
257 };
258
259 vsp_gate: vsp-gate {
260 compatible = "sprd,sc9
261 sprd,syscon = <&vsp_re
262 clocks = <&vsp_clk 0>;
263 #clock-cells = <1>;
264 };
265
266 cam_clk: clock-controller@6200
267 compatible = "sprd,sc9
268 reg = <0 0x62000000 0
269 clocks = <&ext_26m>, <
270 #clock-cells = <1>;
271 };
272
273 cam_gate: cam-gate {
274 compatible = "sprd,sc9
275 sprd,syscon = <&cam_re
276 clocks = <&cam_clk 0>;
277 #clock-cells = <1>;
278 };
279
280 disp_clk: clock-controller@630
281 compatible = "sprd,sc9
282 reg = <0 0x63000000 0
283 clocks = <&ext_26m>, <
284 #clock-cells = <1>;
285 };
286
287 disp_gate: disp-gate {
288 compatible = "sprd,sc9
289 sprd,syscon = <&disp_r
290 clocks = <&disp_clk 0>
291 #clock-cells = <1>;
292 };
293
294 apapb_gate: apapb-gate {
295 compatible = "sprd,sc9
296 sprd,syscon = <&ap_apb
297 clocks = <&ap_clk 0>;
298 #clock-cells = <1>;
299 };
300
301 funnel@10001000 { /* SoC Funne
302 compatible = "arm,core
303 reg = <0 0x10001000 0
304 clocks = <&ext_26m>;
305 clock-names = "apb_pcl
306 out-ports {
307 port {
308 soc_fu
309
310 };
311 };
312 };
313
314 in-ports {
315 #address-cells
316 #size-cells =
317
318 port@0 {
319 reg =
320 soc_fu
321
322
323 };
324 };
325
326 port@4 {
327 reg =
328 soc_fu
329
330
331 };
332 };
333 };
334 };
335
336 etb@10003000 {
337 compatible = "arm,core
338 reg = <0 0x10003000 0
339 clocks = <&ext_26m>;
340 clock-names = "apb_pcl
341 out-ports {
342 port {
343 etb_in
344
345
346 };
347 };
348 };
349 };
350
351 stm@10006000 {
352 compatible = "arm,core
353 reg = <0 0x10006000 0
354 <0 0x01000000 0
355 reg-names = "stm-base"
356 clocks = <&ext_26m>;
357 clock-names = "apb_pcl
358 out-ports {
359 port {
360 stm_ou
361
362
363 };
364 };
365 };
366 };
367
368 funnel@11001000 { /* Cluster0
369 compatible = "arm,core
370 reg = <0 0x11001000 0
371 clocks = <&ext_26m>;
372 clock-names = "apb_pcl
373 out-ports {
374 port {
375 cluste
376
377
378 };
379 };
380 };
381
382 in-ports {
383 #address-cells
384 #size-cells =
385
386 port@0 {
387 reg =
388 cluste
389
390 };
391 };
392
393 port@1 {
394 reg =
395 cluste
396
397 };
398 };
399
400 port@2 {
401 reg =
402 cluste
403
404 };
405 };
406
407 port@4 {
408 reg =
409 cluste
410
411 };
412 };
413 };
414 };
415
416 funnel@11002000 { /* Cluster1
417 compatible = "arm,core
418 reg = <0 0x11002000 0
419 clocks = <&ext_26m>;
420 clock-names = "apb_pcl
421 out-ports {
422 port {
423 cluste
424
425
426 };
427 };
428 };
429
430 in-ports {
431 #address-cells
432 #size-cells =
433
434 port@0 {
435 reg =
436 cluste
437
438 };
439 };
440
441 port@1 {
442 reg =
443 cluste
444
445 };
446 };
447
448 port@2 {
449 reg =
450 cluste
451
452 };
453 };
454
455 port@3 {
456 reg =
457 cluste
458
459 };
460 };
461 };
462 };
463
464 etf@11003000 { /* ETF on Clus
465 compatible = "arm,core
466 reg = <0 0x11003000 0
467 clocks = <&ext_26m>;
468 clock-names = "apb_pcl
469
470 out-ports {
471 port {
472 cluste
473
474
475 };
476 };
477 };
478
479 in-ports {
480 port {
481 cluste
482
483
484 };
485 };
486 };
487 };
488
489 etf@11004000 { /* ETF on Clust
490 compatible = "arm,core
491 reg = <0 0x11004000 0
492 clocks = <&ext_26m>;
493 clock-names = "apb_pcl
494
495 out-ports {
496 port {
497 cluste
498
499
500 };
501 };
502 };
503
504 in-ports {
505 port {
506 cluste
507
508
509 };
510 };
511 };
512 };
513
514 funnel@11005000 { /* Main Funn
515 compatible = "arm,core
516 reg = <0 0x11005000 0
517 clocks = <&ext_26m>;
518 clock-names = "apb_pcl
519
520 out-ports {
521 port {
522 main_f
523
524
525 };
526 };
527 };
528
529 in-ports {
530 #address-cells
531 #size-cells =
532
533 port@0 {
534 reg =
535 main_f
536
537
538 };
539 };
540
541 port@1 {
542 reg =
543 main_f
544
545
546 };
547 };
548 };
549 };
550
551 etm@11440000 {
552 compatible = "arm,core
553 reg = <0 0x11440000 0
554 cpu = <&CPU0>;
555 clocks = <&ext_26m>;
556 clock-names = "apb_pcl
557
558 out-ports {
559 port {
560 etm0_o
561
562
563 };
564 };
565 };
566 };
567
568 etm@11540000 {
569 compatible = "arm,core
570 reg = <0 0x11540000 0
571 cpu = <&CPU1>;
572 clocks = <&ext_26m>;
573 clock-names = "apb_pcl
574
575 out-ports {
576 port {
577 etm1_o
578
579
580 };
581 };
582 };
583 };
584
585 etm@11640000 {
586 compatible = "arm,core
587 reg = <0 0x11640000 0
588 cpu = <&CPU2>;
589 clocks = <&ext_26m>;
590 clock-names = "apb_pcl
591
592 out-ports {
593 port {
594 etm2_o
595
596
597 };
598 };
599 };
600 };
601
602 etm@11740000 {
603 compatible = "arm,core
604 reg = <0 0x11740000 0
605 cpu = <&CPU3>;
606 clocks = <&ext_26m>;
607 clock-names = "apb_pcl
608
609 out-ports {
610 port {
611 etm3_o
612
613
614 };
615 };
616 };
617 };
618
619 etm@11840000 {
620 compatible = "arm,core
621 reg = <0 0x11840000 0
622 cpu = <&CPU4>;
623 clocks = <&ext_26m>;
624 clock-names = "apb_pcl
625
626 out-ports {
627 port {
628 etm4_o
629
630
631 };
632 };
633 };
634 };
635
636 etm@11940000 {
637 compatible = "arm,core
638 reg = <0 0x11940000 0
639 cpu = <&CPU5>;
640 clocks = <&ext_26m>;
641 clock-names = "apb_pcl
642
643 out-ports {
644 port {
645 etm5_o
646
647
648 };
649 };
650 };
651 };
652
653 etm@11a40000 {
654 compatible = "arm,core
655 reg = <0 0x11a40000 0
656 cpu = <&CPU6>;
657 clocks = <&ext_26m>;
658 clock-names = "apb_pcl
659
660 out-ports {
661 port {
662 etm6_o
663
664
665 };
666 };
667 };
668 };
669
670 etm@11b40000 {
671 compatible = "arm,core
672 reg = <0 0x11b40000 0
673 cpu = <&CPU7>;
674 clocks = <&ext_26m>;
675 clock-names = "apb_pcl
676
677 out-ports {
678 port {
679 etm7_o
680
681
682 };
683 };
684 };
685 };
686 };
687 };
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