1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) <<
2 /* 1 /*
3 * Spreadtrum SC9860 SoC 2 * Spreadtrum SC9860 SoC
4 * 3 *
5 * Copyright (C) 2016, Spreadtrum Communicatio 4 * Copyright (C) 2016, Spreadtrum Communications Inc.
>> 5 *
>> 6 * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 */ 7 */
7 8
8 #include <dt-bindings/interrupt-controller/arm 9 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/input/input.h> 10 #include <dt-bindings/input/input.h>
10 #include <dt-bindings/gpio/gpio.h> 11 #include <dt-bindings/gpio/gpio.h>
11 #include "whale2.dtsi" 12 #include "whale2.dtsi"
12 13
13 / { 14 / {
14 cpus { 15 cpus {
15 #address-cells = <2>; 16 #address-cells = <2>;
16 #size-cells = <0>; 17 #size-cells = <0>;
17 18
18 cpu-map { 19 cpu-map {
19 cluster0 { 20 cluster0 {
20 core0 { 21 core0 {
21 cpu = 22 cpu = <&CPU0>;
22 }; 23 };
23 core1 { 24 core1 {
24 cpu = 25 cpu = <&CPU1>;
25 }; 26 };
26 core2 { 27 core2 {
27 cpu = 28 cpu = <&CPU2>;
28 }; 29 };
29 core3 { 30 core3 {
30 cpu = 31 cpu = <&CPU3>;
31 }; 32 };
32 }; 33 };
33 34
34 cluster1 { 35 cluster1 {
35 core0 { 36 core0 {
36 cpu = 37 cpu = <&CPU4>;
37 }; 38 };
38 core1 { 39 core1 {
39 cpu = 40 cpu = <&CPU5>;
40 }; 41 };
41 core2 { 42 core2 {
42 cpu = 43 cpu = <&CPU6>;
43 }; 44 };
44 core3 { 45 core3 {
45 cpu = 46 cpu = <&CPU7>;
46 }; 47 };
47 }; 48 };
48 }; 49 };
49 50
50 CPU0: cpu@530000 { 51 CPU0: cpu@530000 {
51 device_type = "cpu"; 52 device_type = "cpu";
52 compatible = "arm,cort 53 compatible = "arm,cortex-a53";
53 reg = <0x0 0x530000>; 54 reg = <0x0 0x530000>;
54 enable-method = "psci" 55 enable-method = "psci";
55 cpu-idle-states = <&CO 56 cpu-idle-states = <&CORE_PD &CLUSTER_PD>;
56 }; 57 };
57 58
58 CPU1: cpu@530001 { 59 CPU1: cpu@530001 {
59 device_type = "cpu"; 60 device_type = "cpu";
60 compatible = "arm,cort 61 compatible = "arm,cortex-a53";
61 reg = <0x0 0x530001>; 62 reg = <0x0 0x530001>;
62 enable-method = "psci" 63 enable-method = "psci";
63 cpu-idle-states = <&CO 64 cpu-idle-states = <&CORE_PD &CLUSTER_PD>;
64 }; 65 };
65 66
66 CPU2: cpu@530002 { 67 CPU2: cpu@530002 {
67 device_type = "cpu"; 68 device_type = "cpu";
68 compatible = "arm,cort 69 compatible = "arm,cortex-a53";
69 reg = <0x0 0x530002>; 70 reg = <0x0 0x530002>;
70 enable-method = "psci" 71 enable-method = "psci";
71 cpu-idle-states = <&CO 72 cpu-idle-states = <&CORE_PD &CLUSTER_PD>;
72 }; 73 };
73 74
74 CPU3: cpu@530003 { 75 CPU3: cpu@530003 {
75 device_type = "cpu"; 76 device_type = "cpu";
76 compatible = "arm,cort 77 compatible = "arm,cortex-a53";
77 reg = <0x0 0x530003>; 78 reg = <0x0 0x530003>;
78 enable-method = "psci" 79 enable-method = "psci";
79 cpu-idle-states = <&CO 80 cpu-idle-states = <&CORE_PD &CLUSTER_PD>;
80 }; 81 };
81 82
82 CPU4: cpu@530100 { 83 CPU4: cpu@530100 {
83 device_type = "cpu"; 84 device_type = "cpu";
84 compatible = "arm,cort 85 compatible = "arm,cortex-a53";
85 reg = <0x0 0x530100>; 86 reg = <0x0 0x530100>;
86 enable-method = "psci" 87 enable-method = "psci";
87 cpu-idle-states = <&CO 88 cpu-idle-states = <&CORE_PD &CLUSTER_PD>;
88 }; 89 };
89 90
90 CPU5: cpu@530101 { 91 CPU5: cpu@530101 {
91 device_type = "cpu"; 92 device_type = "cpu";
92 compatible = "arm,cort 93 compatible = "arm,cortex-a53";
93 reg = <0x0 0x530101>; 94 reg = <0x0 0x530101>;
94 enable-method = "psci" 95 enable-method = "psci";
95 cpu-idle-states = <&CO 96 cpu-idle-states = <&CORE_PD &CLUSTER_PD>;
96 }; 97 };
97 98
98 CPU6: cpu@530102 { 99 CPU6: cpu@530102 {
99 device_type = "cpu"; 100 device_type = "cpu";
100 compatible = "arm,cort 101 compatible = "arm,cortex-a53";
101 reg = <0x0 0x530102>; 102 reg = <0x0 0x530102>;
102 enable-method = "psci" 103 enable-method = "psci";
103 cpu-idle-states = <&CO 104 cpu-idle-states = <&CORE_PD &CLUSTER_PD>;
104 }; 105 };
105 106
106 CPU7: cpu@530103 { 107 CPU7: cpu@530103 {
107 device_type = "cpu"; 108 device_type = "cpu";
108 compatible = "arm,cort 109 compatible = "arm,cortex-a53";
109 reg = <0x0 0x530103>; 110 reg = <0x0 0x530103>;
110 enable-method = "psci" 111 enable-method = "psci";
111 cpu-idle-states = <&CO 112 cpu-idle-states = <&CORE_PD &CLUSTER_PD>;
112 }; 113 };
113 }; 114 };
114 115
115 idle-states { !! 116 idle-states{
116 entry-method = "psci"; 117 entry-method = "psci";
117 118
118 CORE_PD: core_pd { 119 CORE_PD: core_pd {
119 compatible = "arm,idle 120 compatible = "arm,idle-state";
120 entry-latency-us = <10 121 entry-latency-us = <1000>;
121 exit-latency-us = <700 122 exit-latency-us = <700>;
122 min-residency-us = <25 123 min-residency-us = <2500>;
123 local-timer-stop; 124 local-timer-stop;
124 arm,psci-suspend-param 125 arm,psci-suspend-param = <0x00010002>;
125 }; 126 };
126 127
127 CLUSTER_PD: cluster_pd { 128 CLUSTER_PD: cluster_pd {
128 compatible = "arm,idle 129 compatible = "arm,idle-state";
129 entry-latency-us = <10 130 entry-latency-us = <1000>;
130 exit-latency-us = <100 131 exit-latency-us = <1000>;
131 min-residency-us = <30 132 min-residency-us = <3000>;
132 local-timer-stop; 133 local-timer-stop;
133 arm,psci-suspend-param 134 arm,psci-suspend-param = <0x01010003>;
134 }; 135 };
135 }; 136 };
136 137
>> 138 gic: interrupt-controller@12001000 {
>> 139 compatible = "arm,gic-400";
>> 140 reg = <0 0x12001000 0 0x1000>,
>> 141 <0 0x12002000 0 0x2000>,
>> 142 <0 0x12004000 0 0x2000>,
>> 143 <0 0x12006000 0 0x2000>;
>> 144 #interrupt-cells = <3>;
>> 145 interrupt-controller;
>> 146 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8)
>> 147 | IRQ_TYPE_LEVEL_HIGH)>;
>> 148 };
>> 149
137 psci { 150 psci {
138 compatible = "arm,psci-0.2"; 151 compatible = "arm,psci-0.2";
139 method = "smc"; 152 method = "smc";
140 }; 153 };
141 154
142 timer { 155 timer {
143 compatible = "arm,armv8-timer" 156 compatible = "arm,armv8-timer";
144 interrupts = <GIC_PPI 13 (GIC_ 157 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8)
145 | IRQ 158 | IRQ_TYPE_LEVEL_LOW)>,
146 <GIC_PPI 14 (GIC_ 159 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8)
147 | IRQ 160 | IRQ_TYPE_LEVEL_LOW)>,
148 <GIC_PPI 11 (GIC_ 161 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8)
149 | IRQ 162 | IRQ_TYPE_LEVEL_LOW)>,
150 <GIC_PPI 10 (GIC_ 163 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8)
151 | IRQ 164 | IRQ_TYPE_LEVEL_LOW)>;
152 }; 165 };
153 166
154 pmu { 167 pmu {
155 compatible = "arm,cortex-a53-p !! 168 compatible = "arm,cortex-a53-pmu", "arm,armv8-pmuv3";
156 interrupts = <GIC_SPI 122 IRQ_ 169 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
157 <GIC_SPI 123 IRQ_ 170 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
158 <GIC_SPI 124 IRQ_ 171 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
159 <GIC_SPI 125 IRQ_ 172 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
160 <GIC_SPI 154 IRQ_ 173 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
161 <GIC_SPI 155 IRQ_ 174 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
162 <GIC_SPI 156 IRQ_ 175 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>,
163 <GIC_SPI 157 IRQ_ 176 <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
164 interrupt-affinity = <&CPU0>, 177 interrupt-affinity = <&CPU0>,
165 <&CPU1>, 178 <&CPU1>,
166 <&CPU2>, 179 <&CPU2>,
167 <&CPU3>, 180 <&CPU3>,
168 <&CPU4>, 181 <&CPU4>,
169 <&CPU5>, 182 <&CPU5>,
170 <&CPU6>, 183 <&CPU6>,
171 <&CPU7>; 184 <&CPU7>;
172 }; 185 };
173 186
174 soc { 187 soc {
175 gic: interrupt-controller@1200 <<
176 compatible = "arm,gic- <<
177 reg = <0 0x12001000 0 <<
178 <0 0x12002000 0 <<
179 <0 0x12004000 0 <<
180 <0 0x12006000 0 <<
181 #interrupt-cells = <3> <<
182 interrupt-controller; <<
183 interrupts = <GIC_PPI <<
184 <<
185 }; <<
186 <<
187 pmu_gate: pmu-gate { 188 pmu_gate: pmu-gate {
188 compatible = "sprd,sc9 189 compatible = "sprd,sc9860-pmu-gate";
189 sprd,syscon = <&pmu_re 190 sprd,syscon = <&pmu_regs>; /* 0x402b0000 */
190 clocks = <&ext_26m>; 191 clocks = <&ext_26m>;
191 #clock-cells = <1>; 192 #clock-cells = <1>;
192 }; 193 };
193 194
194 pll: pll { 195 pll: pll {
195 compatible = "sprd,sc9 196 compatible = "sprd,sc9860-pll";
196 sprd,syscon = <&ana_re 197 sprd,syscon = <&ana_regs>; /* 0x40400000 */
197 clocks = <&pmu_gate 0> 198 clocks = <&pmu_gate 0>;
198 #clock-cells = <1>; 199 #clock-cells = <1>;
199 }; 200 };
200 201
201 ap_clk: clock-controller@20000 202 ap_clk: clock-controller@20000000 {
202 compatible = "sprd,sc9 203 compatible = "sprd,sc9860-ap-clk";
203 reg = <0 0x20000000 0 204 reg = <0 0x20000000 0 0x400>;
204 clocks = <&ext_26m>, < 205 clocks = <&ext_26m>, <&pll 0>,
205 <&pmu_gate 0> 206 <&pmu_gate 0>;
206 #clock-cells = <1>; 207 #clock-cells = <1>;
207 }; 208 };
208 209
209 aon_prediv: aon-prediv@402d000 !! 210 aon_prediv: aon-prediv {
210 compatible = "sprd,sc9 211 compatible = "sprd,sc9860-aon-prediv";
211 reg = <0 0x402d0000 0 212 reg = <0 0x402d0000 0 0x400>;
212 clocks = <&ext_26m>, < 213 clocks = <&ext_26m>, <&pll 0>,
213 <&pmu_gate 0> 214 <&pmu_gate 0>;
214 #clock-cells = <1>; 215 #clock-cells = <1>;
215 }; 216 };
216 217
217 apahb_gate: apahb-gate { 218 apahb_gate: apahb-gate {
218 compatible = "sprd,sc9 219 compatible = "sprd,sc9860-apahb-gate";
219 sprd,syscon = <&ap_ahb 220 sprd,syscon = <&ap_ahb_regs>; /* 0x20210000 */
220 clocks = <&aon_prediv 221 clocks = <&aon_prediv 0>;
221 #clock-cells = <1>; 222 #clock-cells = <1>;
222 }; 223 };
223 224
224 aon_gate: aon-gate { 225 aon_gate: aon-gate {
225 compatible = "sprd,sc9 226 compatible = "sprd,sc9860-aon-gate";
226 sprd,syscon = <&aon_re 227 sprd,syscon = <&aon_regs>; /* 0x402e0000 */
227 clocks = <&aon_prediv 228 clocks = <&aon_prediv 0>;
228 #clock-cells = <1>; 229 #clock-cells = <1>;
229 }; 230 };
230 231
231 aonsecure_clk: clock-controlle 232 aonsecure_clk: clock-controller@40880000 {
232 compatible = "sprd,sc9 233 compatible = "sprd,sc9860-aonsecure-clk";
233 reg = <0 0x40880000 0 234 reg = <0 0x40880000 0 0x400>;
234 clocks = <&ext_26m>, < 235 clocks = <&ext_26m>, <&pll 0>;
235 #clock-cells = <1>; 236 #clock-cells = <1>;
236 }; 237 };
237 238
238 agcp_gate: agcp-gate { 239 agcp_gate: agcp-gate {
239 compatible = "sprd,sc9 240 compatible = "sprd,sc9860-agcp-gate";
240 sprd,syscon = <&agcp_r 241 sprd,syscon = <&agcp_regs>; /* 0x415e0000 */
241 clocks = <&aon_prediv 242 clocks = <&aon_prediv 0>;
242 #clock-cells = <1>; 243 #clock-cells = <1>;
243 }; 244 };
244 245
245 gpu_clk: clock-controller@6020 246 gpu_clk: clock-controller@60200000 {
246 compatible = "sprd,sc9 247 compatible = "sprd,sc9860-gpu-clk";
247 reg = <0 0x60200000 0 248 reg = <0 0x60200000 0 0x400>;
248 clocks = <&pll 0>; 249 clocks = <&pll 0>;
249 #clock-cells = <1>; 250 #clock-cells = <1>;
250 }; 251 };
251 252
252 vsp_clk: clock-controller@6100 253 vsp_clk: clock-controller@61000000 {
253 compatible = "sprd,sc9 254 compatible = "sprd,sc9860-vsp-clk";
254 reg = <0 0x61000000 0 255 reg = <0 0x61000000 0 0x400>;
255 clocks = <&ext_26m>, < 256 clocks = <&ext_26m>, <&pll 0>;
256 #clock-cells = <1>; 257 #clock-cells = <1>;
257 }; 258 };
258 259
259 vsp_gate: vsp-gate { 260 vsp_gate: vsp-gate {
260 compatible = "sprd,sc9 261 compatible = "sprd,sc9860-vsp-gate";
261 sprd,syscon = <&vsp_re 262 sprd,syscon = <&vsp_regs>; /* 0x61100000 */
262 clocks = <&vsp_clk 0>; 263 clocks = <&vsp_clk 0>;
263 #clock-cells = <1>; 264 #clock-cells = <1>;
264 }; 265 };
265 266
266 cam_clk: clock-controller@6200 267 cam_clk: clock-controller@62000000 {
267 compatible = "sprd,sc9 268 compatible = "sprd,sc9860-cam-clk";
268 reg = <0 0x62000000 0 269 reg = <0 0x62000000 0 0x4000>;
269 clocks = <&ext_26m>, < 270 clocks = <&ext_26m>, <&pll 0>;
270 #clock-cells = <1>; 271 #clock-cells = <1>;
271 }; 272 };
272 273
273 cam_gate: cam-gate { 274 cam_gate: cam-gate {
274 compatible = "sprd,sc9 275 compatible = "sprd,sc9860-cam-gate";
275 sprd,syscon = <&cam_re 276 sprd,syscon = <&cam_regs>; /* 0x62100000 */
276 clocks = <&cam_clk 0>; 277 clocks = <&cam_clk 0>;
277 #clock-cells = <1>; 278 #clock-cells = <1>;
278 }; 279 };
279 280
280 disp_clk: clock-controller@630 281 disp_clk: clock-controller@63000000 {
281 compatible = "sprd,sc9 282 compatible = "sprd,sc9860-disp-clk";
282 reg = <0 0x63000000 0 283 reg = <0 0x63000000 0 0x400>;
283 clocks = <&ext_26m>, < 284 clocks = <&ext_26m>, <&pll 0>;
284 #clock-cells = <1>; 285 #clock-cells = <1>;
285 }; 286 };
286 287
287 disp_gate: disp-gate { 288 disp_gate: disp-gate {
288 compatible = "sprd,sc9 289 compatible = "sprd,sc9860-disp-gate";
289 sprd,syscon = <&disp_r 290 sprd,syscon = <&disp_regs>; /* 0x63100000 */
290 clocks = <&disp_clk 0> 291 clocks = <&disp_clk 0>;
291 #clock-cells = <1>; 292 #clock-cells = <1>;
292 }; 293 };
293 294
294 apapb_gate: apapb-gate { 295 apapb_gate: apapb-gate {
295 compatible = "sprd,sc9 296 compatible = "sprd,sc9860-apapb-gate";
296 sprd,syscon = <&ap_apb 297 sprd,syscon = <&ap_apb_regs>; /* 0x70b00000 */
297 clocks = <&ap_clk 0>; 298 clocks = <&ap_clk 0>;
298 #clock-cells = <1>; 299 #clock-cells = <1>;
299 }; 300 };
300 301
301 funnel@10001000 { /* SoC Funne 302 funnel@10001000 { /* SoC Funnel */
302 compatible = "arm,core 303 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
303 reg = <0 0x10001000 0 304 reg = <0 0x10001000 0 0x1000>;
304 clocks = <&ext_26m>; 305 clocks = <&ext_26m>;
305 clock-names = "apb_pcl 306 clock-names = "apb_pclk";
306 out-ports { 307 out-ports {
307 port { 308 port {
308 soc_fu 309 soc_funnel_out_port: endpoint {
309 310 remote-endpoint = <&etb_in>;
310 }; 311 };
311 }; 312 };
312 }; 313 };
313 314
314 in-ports { 315 in-ports {
315 #address-cells 316 #address-cells = <1>;
316 #size-cells = 317 #size-cells = <0>;
317 318
318 port@0 { 319 port@0 {
319 reg = 320 reg = <0>;
320 soc_fu 321 soc_funnel_in_port0: endpoint {
321 322 remote-endpoint =
322 323 <&main_funnel_out_port>;
323 }; 324 };
324 }; 325 };
325 326
326 port@4 { 327 port@4 {
327 reg = 328 reg = <4>;
328 soc_fu 329 soc_funnel_in_port1: endpoint {
329 330 remote-endpoint =
330 331 <&stm_out_port>;
331 }; 332 };
332 }; 333 };
333 }; 334 };
334 }; 335 };
335 336
336 etb@10003000 { 337 etb@10003000 {
337 compatible = "arm,core 338 compatible = "arm,coresight-tmc", "arm,primecell";
338 reg = <0 0x10003000 0 339 reg = <0 0x10003000 0 0x1000>;
339 clocks = <&ext_26m>; 340 clocks = <&ext_26m>;
340 clock-names = "apb_pcl 341 clock-names = "apb_pclk";
341 out-ports { 342 out-ports {
342 port { 343 port {
343 etb_in 344 etb_in: endpoint {
344 345 remote-endpoint =
345 346 <&soc_funnel_out_port>;
346 }; 347 };
347 }; 348 };
348 }; 349 };
349 }; 350 };
350 351
351 stm@10006000 { 352 stm@10006000 {
352 compatible = "arm,core 353 compatible = "arm,coresight-stm", "arm,primecell";
353 reg = <0 0x10006000 0 354 reg = <0 0x10006000 0 0x1000>,
354 <0 0x01000000 0 355 <0 0x01000000 0 0x180000>;
355 reg-names = "stm-base" 356 reg-names = "stm-base", "stm-stimulus-base";
356 clocks = <&ext_26m>; 357 clocks = <&ext_26m>;
357 clock-names = "apb_pcl 358 clock-names = "apb_pclk";
358 out-ports { 359 out-ports {
359 port { 360 port {
360 stm_ou 361 stm_out_port: endpoint {
361 362 remote-endpoint =
362 363 <&soc_funnel_in_port1>;
363 }; 364 };
364 }; 365 };
365 }; 366 };
366 }; 367 };
367 368
368 funnel@11001000 { /* Cluster0 369 funnel@11001000 { /* Cluster0 Funnel */
369 compatible = "arm,core 370 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
370 reg = <0 0x11001000 0 371 reg = <0 0x11001000 0 0x1000>;
371 clocks = <&ext_26m>; 372 clocks = <&ext_26m>;
372 clock-names = "apb_pcl 373 clock-names = "apb_pclk";
373 out-ports { 374 out-ports {
374 port { 375 port {
375 cluste 376 cluster0_funnel_out_port: endpoint {
376 377 remote-endpoint =
377 378 <&cluster0_etf_in>;
378 }; 379 };
379 }; 380 };
380 }; 381 };
381 382
382 in-ports { 383 in-ports {
383 #address-cells 384 #address-cells = <1>;
384 #size-cells = 385 #size-cells = <0>;
385 386
386 port@0 { 387 port@0 {
387 reg = 388 reg = <0>;
388 cluste 389 cluster0_funnel_in_port0: endpoint {
389 390 remote-endpoint = <&etm0_out>;
390 }; 391 };
391 }; 392 };
392 393
393 port@1 { 394 port@1 {
394 reg = 395 reg = <1>;
395 cluste 396 cluster0_funnel_in_port1: endpoint {
396 397 remote-endpoint = <&etm1_out>;
397 }; 398 };
398 }; 399 };
399 400
400 port@2 { 401 port@2 {
401 reg = 402 reg = <2>;
402 cluste 403 cluster0_funnel_in_port2: endpoint {
403 404 remote-endpoint = <&etm2_out>;
404 }; 405 };
405 }; 406 };
406 407
407 port@4 { 408 port@4 {
408 reg = 409 reg = <4>;
409 cluste 410 cluster0_funnel_in_port3: endpoint {
410 411 remote-endpoint = <&etm3_out>;
411 }; 412 };
412 }; 413 };
413 }; 414 };
414 }; 415 };
415 416
416 funnel@11002000 { /* Cluster1 417 funnel@11002000 { /* Cluster1 Funnel */
417 compatible = "arm,core 418 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
418 reg = <0 0x11002000 0 419 reg = <0 0x11002000 0 0x1000>;
419 clocks = <&ext_26m>; 420 clocks = <&ext_26m>;
420 clock-names = "apb_pcl 421 clock-names = "apb_pclk";
421 out-ports { 422 out-ports {
422 port { 423 port {
423 cluste 424 cluster1_funnel_out_port: endpoint {
424 425 remote-endpoint =
425 426 <&cluster1_etf_in>;
426 }; 427 };
427 }; 428 };
428 }; 429 };
429 430
430 in-ports { 431 in-ports {
431 #address-cells 432 #address-cells = <1>;
432 #size-cells = 433 #size-cells = <0>;
433 434
434 port@0 { 435 port@0 {
435 reg = 436 reg = <0>;
436 cluste 437 cluster1_funnel_in_port0: endpoint {
437 438 remote-endpoint = <&etm4_out>;
438 }; 439 };
439 }; 440 };
440 441
441 port@1 { 442 port@1 {
442 reg = 443 reg = <1>;
443 cluste 444 cluster1_funnel_in_port1: endpoint {
444 445 remote-endpoint = <&etm5_out>;
445 }; 446 };
446 }; 447 };
447 448
448 port@2 { 449 port@2 {
449 reg = 450 reg = <2>;
450 cluste 451 cluster1_funnel_in_port2: endpoint {
451 452 remote-endpoint = <&etm6_out>;
452 }; 453 };
453 }; 454 };
454 455
455 port@3 { 456 port@3 {
456 reg = 457 reg = <3>;
457 cluste 458 cluster1_funnel_in_port3: endpoint {
458 459 remote-endpoint = <&etm7_out>;
459 }; 460 };
460 }; 461 };
461 }; 462 };
462 }; 463 };
463 464
464 etf@11003000 { /* ETF on Clus 465 etf@11003000 { /* ETF on Cluster0 */
465 compatible = "arm,core 466 compatible = "arm,coresight-tmc", "arm,primecell";
466 reg = <0 0x11003000 0 467 reg = <0 0x11003000 0 0x1000>;
467 clocks = <&ext_26m>; 468 clocks = <&ext_26m>;
468 clock-names = "apb_pcl 469 clock-names = "apb_pclk";
469 470
470 out-ports { 471 out-ports {
471 port { 472 port {
472 cluste 473 cluster0_etf_out: endpoint {
473 474 remote-endpoint =
474 475 <&main_funnel_in_port0>;
475 }; 476 };
476 }; 477 };
477 }; 478 };
478 479
479 in-ports { 480 in-ports {
480 port { 481 port {
481 cluste 482 cluster0_etf_in: endpoint {
482 483 remote-endpoint =
483 484 <&cluster0_funnel_out_port>;
484 }; 485 };
485 }; 486 };
486 }; 487 };
487 }; 488 };
488 489
489 etf@11004000 { /* ETF on Clust 490 etf@11004000 { /* ETF on Cluster1 */
490 compatible = "arm,core 491 compatible = "arm,coresight-tmc", "arm,primecell";
491 reg = <0 0x11004000 0 492 reg = <0 0x11004000 0 0x1000>;
492 clocks = <&ext_26m>; 493 clocks = <&ext_26m>;
493 clock-names = "apb_pcl 494 clock-names = "apb_pclk";
494 495
495 out-ports { 496 out-ports {
496 port { 497 port {
497 cluste 498 cluster1_etf_out: endpoint {
498 499 remote-endpoint =
499 500 <&main_funnel_in_port1>;
500 }; 501 };
501 }; 502 };
502 }; 503 };
503 504
504 in-ports { 505 in-ports {
505 port { 506 port {
506 cluste 507 cluster1_etf_in: endpoint {
507 508 remote-endpoint =
508 509 <&cluster1_funnel_out_port>;
509 }; 510 };
510 }; 511 };
511 }; 512 };
512 }; 513 };
513 514
514 funnel@11005000 { /* Main Funn 515 funnel@11005000 { /* Main Funnel */
515 compatible = "arm,core 516 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
516 reg = <0 0x11005000 0 517 reg = <0 0x11005000 0 0x1000>;
517 clocks = <&ext_26m>; 518 clocks = <&ext_26m>;
518 clock-names = "apb_pcl 519 clock-names = "apb_pclk";
519 520
520 out-ports { 521 out-ports {
521 port { 522 port {
522 main_f 523 main_funnel_out_port: endpoint {
523 524 remote-endpoint =
524 525 <&soc_funnel_in_port0>;
525 }; 526 };
526 }; 527 };
527 }; 528 };
528 529
529 in-ports { 530 in-ports {
530 #address-cells 531 #address-cells = <1>;
531 #size-cells = 532 #size-cells = <0>;
532 533
533 port@0 { 534 port@0 {
534 reg = 535 reg = <0>;
535 main_f 536 main_funnel_in_port0: endpoint {
536 537 remote-endpoint =
537 538 <&cluster0_etf_out>;
538 }; 539 };
539 }; 540 };
540 541
541 port@1 { 542 port@1 {
542 reg = 543 reg = <1>;
543 main_f 544 main_funnel_in_port1: endpoint {
544 545 remote-endpoint =
545 546 <&cluster1_etf_out>;
546 }; 547 };
547 }; 548 };
548 }; 549 };
549 }; 550 };
550 551
551 etm@11440000 { 552 etm@11440000 {
552 compatible = "arm,core 553 compatible = "arm,coresight-etm4x", "arm,primecell";
553 reg = <0 0x11440000 0 554 reg = <0 0x11440000 0 0x1000>;
554 cpu = <&CPU0>; 555 cpu = <&CPU0>;
555 clocks = <&ext_26m>; 556 clocks = <&ext_26m>;
556 clock-names = "apb_pcl 557 clock-names = "apb_pclk";
557 558
558 out-ports { 559 out-ports {
559 port { 560 port {
560 etm0_o 561 etm0_out: endpoint {
561 562 remote-endpoint =
562 563 <&cluster0_funnel_in_port0>;
563 }; 564 };
564 }; 565 };
565 }; 566 };
566 }; 567 };
567 568
568 etm@11540000 { 569 etm@11540000 {
569 compatible = "arm,core 570 compatible = "arm,coresight-etm4x", "arm,primecell";
570 reg = <0 0x11540000 0 571 reg = <0 0x11540000 0 0x1000>;
571 cpu = <&CPU1>; 572 cpu = <&CPU1>;
572 clocks = <&ext_26m>; 573 clocks = <&ext_26m>;
573 clock-names = "apb_pcl 574 clock-names = "apb_pclk";
574 575
575 out-ports { 576 out-ports {
576 port { 577 port {
577 etm1_o 578 etm1_out: endpoint {
578 579 remote-endpoint =
579 580 <&cluster0_funnel_in_port1>;
580 }; 581 };
581 }; 582 };
582 }; 583 };
583 }; 584 };
584 585
585 etm@11640000 { 586 etm@11640000 {
586 compatible = "arm,core 587 compatible = "arm,coresight-etm4x", "arm,primecell";
587 reg = <0 0x11640000 0 588 reg = <0 0x11640000 0 0x1000>;
588 cpu = <&CPU2>; 589 cpu = <&CPU2>;
589 clocks = <&ext_26m>; 590 clocks = <&ext_26m>;
590 clock-names = "apb_pcl 591 clock-names = "apb_pclk";
591 592
592 out-ports { 593 out-ports {
593 port { 594 port {
594 etm2_o 595 etm2_out: endpoint {
595 596 remote-endpoint =
596 597 <&cluster0_funnel_in_port2>;
597 }; 598 };
598 }; 599 };
599 }; 600 };
600 }; 601 };
601 602
602 etm@11740000 { 603 etm@11740000 {
603 compatible = "arm,core 604 compatible = "arm,coresight-etm4x", "arm,primecell";
604 reg = <0 0x11740000 0 605 reg = <0 0x11740000 0 0x1000>;
605 cpu = <&CPU3>; 606 cpu = <&CPU3>;
606 clocks = <&ext_26m>; 607 clocks = <&ext_26m>;
607 clock-names = "apb_pcl 608 clock-names = "apb_pclk";
608 609
609 out-ports { 610 out-ports {
610 port { 611 port {
611 etm3_o 612 etm3_out: endpoint {
612 613 remote-endpoint =
613 614 <&cluster0_funnel_in_port3>;
614 }; 615 };
615 }; 616 };
616 }; 617 };
617 }; 618 };
618 619
619 etm@11840000 { 620 etm@11840000 {
620 compatible = "arm,core 621 compatible = "arm,coresight-etm4x", "arm,primecell";
621 reg = <0 0x11840000 0 622 reg = <0 0x11840000 0 0x1000>;
622 cpu = <&CPU4>; 623 cpu = <&CPU4>;
623 clocks = <&ext_26m>; 624 clocks = <&ext_26m>;
624 clock-names = "apb_pcl 625 clock-names = "apb_pclk";
625 626
626 out-ports { 627 out-ports {
627 port { 628 port {
628 etm4_o 629 etm4_out: endpoint {
629 630 remote-endpoint =
630 631 <&cluster1_funnel_in_port0>;
631 }; 632 };
632 }; 633 };
633 }; 634 };
634 }; 635 };
635 636
636 etm@11940000 { 637 etm@11940000 {
637 compatible = "arm,core 638 compatible = "arm,coresight-etm4x", "arm,primecell";
638 reg = <0 0x11940000 0 639 reg = <0 0x11940000 0 0x1000>;
639 cpu = <&CPU5>; 640 cpu = <&CPU5>;
640 clocks = <&ext_26m>; 641 clocks = <&ext_26m>;
641 clock-names = "apb_pcl 642 clock-names = "apb_pclk";
642 643
643 out-ports { 644 out-ports {
644 port { 645 port {
645 etm5_o 646 etm5_out: endpoint {
646 647 remote-endpoint =
647 648 <&cluster1_funnel_in_port1>;
648 }; 649 };
649 }; 650 };
650 }; 651 };
651 }; 652 };
652 653
653 etm@11a40000 { 654 etm@11a40000 {
654 compatible = "arm,core 655 compatible = "arm,coresight-etm4x", "arm,primecell";
655 reg = <0 0x11a40000 0 656 reg = <0 0x11a40000 0 0x1000>;
656 cpu = <&CPU6>; 657 cpu = <&CPU6>;
657 clocks = <&ext_26m>; 658 clocks = <&ext_26m>;
658 clock-names = "apb_pcl 659 clock-names = "apb_pclk";
659 660
660 out-ports { 661 out-ports {
661 port { 662 port {
662 etm6_o 663 etm6_out: endpoint {
663 664 remote-endpoint =
664 665 <&cluster1_funnel_in_port2>;
665 }; 666 };
666 }; 667 };
667 }; 668 };
668 }; 669 };
669 670
670 etm@11b40000 { 671 etm@11b40000 {
671 compatible = "arm,core 672 compatible = "arm,coresight-etm4x", "arm,primecell";
672 reg = <0 0x11b40000 0 673 reg = <0 0x11b40000 0 0x1000>;
673 cpu = <&CPU7>; 674 cpu = <&CPU7>;
674 clocks = <&ext_26m>; 675 clocks = <&ext_26m>;
675 clock-names = "apb_pcl 676 clock-names = "apb_pclk";
676 677
677 out-ports { 678 out-ports {
678 port { 679 port {
679 etm7_o 680 etm7_out: endpoint {
680 681 remote-endpoint =
681 682 <&cluster1_funnel_in_port3>;
682 }; 683 };
683 }; 684 };
>> 685 };
>> 686 };
>> 687
>> 688 gpio-keys {
>> 689 compatible = "gpio-keys";
>> 690
>> 691 key-volumedown {
>> 692 label = "Volume Down Key";
>> 693 linux,code = <KEY_VOLUMEDOWN>;
>> 694 gpios = <&eic_debounce 2 GPIO_ACTIVE_LOW>;
>> 695 debounce-interval = <2>;
>> 696 wakeup-source;
>> 697 };
>> 698
>> 699 key-volumeup {
>> 700 label = "Volume Up Key";
>> 701 linux,code = <KEY_VOLUMEUP>;
>> 702 gpios = <&pmic_eic 10 GPIO_ACTIVE_HIGH>;
>> 703 debounce-interval = <2>;
>> 704 wakeup-source;
>> 705 };
>> 706
>> 707 key-power {
>> 708 label = "Power Key";
>> 709 linux,code = <KEY_POWER>;
>> 710 gpios = <&pmic_eic 1 GPIO_ACTIVE_HIGH>;
>> 711 debounce-interval = <2>;
>> 712 wakeup-source;
684 }; 713 };
685 }; 714 };
686 }; 715 };
687 }; 716 };
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