1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Unisoc SC9863A SoC DTS file
4 *
5 * Copyright (C) 2019, Unisoc Inc.
6 */
7
8 #include <dt-bindings/clock/sprd,sc9863a-clk.h
9 #include <dt-bindings/interrupt-controller/arm
10 #include "sharkl3.dtsi"
11
12 / {
13 cpus {
14 #address-cells = <2>;
15 #size-cells = <0>;
16
17 cpu-map {
18 cluster0 {
19 core0 {
20 cpu =
21 };
22 core1 {
23 cpu =
24 };
25 core2 {
26 cpu =
27 };
28 core3 {
29 cpu =
30 };
31 core4 {
32 cpu =
33 };
34 core5 {
35 cpu =
36 };
37 core6 {
38 cpu =
39 };
40 core7 {
41 cpu =
42 };
43 };
44 };
45
46 CPU0: cpu@0 {
47 device_type = "cpu";
48 compatible = "arm,cort
49 reg = <0x0 0x0>;
50 enable-method = "psci"
51 cpu-idle-states = <&CO
52 };
53
54 CPU1: cpu@100 {
55 device_type = "cpu";
56 compatible = "arm,cort
57 reg = <0x0 0x100>;
58 enable-method = "psci"
59 cpu-idle-states = <&CO
60 };
61
62 CPU2: cpu@200 {
63 device_type = "cpu";
64 compatible = "arm,cort
65 reg = <0x0 0x200>;
66 enable-method = "psci"
67 cpu-idle-states = <&CO
68 };
69
70 CPU3: cpu@300 {
71 device_type = "cpu";
72 compatible = "arm,cort
73 reg = <0x0 0x300>;
74 enable-method = "psci"
75 cpu-idle-states = <&CO
76 };
77
78 CPU4: cpu@400 {
79 device_type = "cpu";
80 compatible = "arm,cort
81 reg = <0x0 0x400>;
82 enable-method = "psci"
83 cpu-idle-states = <&CO
84 };
85
86 CPU5: cpu@500 {
87 device_type = "cpu";
88 compatible = "arm,cort
89 reg = <0x0 0x500>;
90 enable-method = "psci"
91 cpu-idle-states = <&CO
92 };
93
94 CPU6: cpu@600 {
95 device_type = "cpu";
96 compatible = "arm,cort
97 reg = <0x0 0x600>;
98 enable-method = "psci"
99 cpu-idle-states = <&CO
100 };
101
102 CPU7: cpu@700 {
103 device_type = "cpu";
104 compatible = "arm,cort
105 reg = <0x0 0x700>;
106 enable-method = "psci"
107 cpu-idle-states = <&CO
108 };
109 };
110
111 idle-states {
112 entry-method = "psci";
113 CORE_PD: core-pd {
114 compatible = "arm,idle
115 entry-latency-us = <40
116 exit-latency-us = <400
117 min-residency-us = <10
118 local-timer-stop;
119 arm,psci-suspend-param
120 };
121 };
122
123 psci {
124 compatible = "arm,psci-0.2";
125 method = "smc";
126 };
127
128 timer {
129 compatible = "arm,armv8-timer"
130 interrupts = <GIC_PPI 13 IRQ_T
131 <GIC_PPI 14 IRQ_T
132 <GIC_PPI 11 IRQ_T
133 <GIC_PPI 10 IRQ_T
134 };
135
136 pmu {
137 compatible = "arm,cortex-a55-p
138 interrupts = <GIC_SPI 144 IRQ_
139 <GIC_SPI 145 IRQ_
140 <GIC_SPI 146 IRQ_
141 <GIC_SPI 147 IRQ_
142 <GIC_SPI 148 IRQ_
143 <GIC_SPI 149 IRQ_
144 <GIC_SPI 150 IRQ_
145 <GIC_SPI 151 IRQ_
146 };
147
148 soc {
149 gic: interrupt-controller@1400
150 compatible = "arm,gic-
151 #interrupt-cells = <3>
152 #address-cells = <2>;
153 #size-cells = <2>;
154 ranges;
155 redistributor-stride =
156 #redistributor-regions
157 interrupt-controller;
158 reg = <0x0 0x14000000
159 <0x0 0x14040000
160 interrupts = <GIC_PPI
161 };
162
163 ap_clk: clock-controller@21500
164 compatible = "sprd,sc9
165 reg = <0 0x21500000 0
166 clocks = <&ext_32k>, <
167 clock-names = "ext-32k
168 #clock-cells = <1>;
169 };
170
171 aon_clk: clock-controller@402d
172 compatible = "sprd,sc9
173 reg = <0 0x402d0000 0
174 clocks = <&ext_26m>, <
175 <&ext_32k>, <
176 clock-names = "ext-26m
177 "ext-32k
178 #clock-cells = <1>;
179 };
180
181 mm_clk: clock-controller@60900
182 compatible = "sprd,sc9
183 reg = <0 0x60900000 0
184 #clock-cells = <1>;
185 };
186
187 funnel@10001000 {
188 compatible = "arm,core
189 reg = <0 0x10001000 0
190 clocks = <&ext_26m>;
191 clock-names = "apb_pcl
192
193 out-ports {
194 port {
195 funnel
196
197 };
198 };
199 };
200
201 in-ports {
202 port {
203 funnel
204
205
206 };
207 };
208 };
209 };
210
211 etb@10003000 {
212 compatible = "arm,core
213 reg = <0 0x10003000 0
214 clocks = <&ext_26m>;
215 clock-names = "apb_pcl
216
217 in-ports {
218 port {
219 etb_in
220
221
222 };
223 };
224 };
225 };
226
227 funnel@12001000 {
228 compatible = "arm,core
229 reg = <0 0x12001000 0
230 clocks = <&ext_26m>;
231 clock-names = "apb_pcl
232
233 out-ports {
234 port {
235 funnel
236
237
238 };
239 };
240 };
241
242 in-ports {
243 #address-cells
244 #size-cells =
245
246 port@0 {
247 reg =
248 funnel
249
250 };
251 };
252
253 port@1 {
254 reg =
255 funnel
256
257 };
258 };
259
260 port@2 {
261 reg =
262 funnel
263
264 };
265 };
266
267 port@3 {
268 reg =
269 funnel
270
271 };
272 };
273 };
274 };
275
276 etf@12002000 {
277 compatible = "arm,core
278 reg = <0 0x12002000 0
279 clocks = <&ext_26m>;
280 clock-names = "apb_pcl
281
282 out-ports {
283 port {
284 etf_li
285
286
287 };
288 };
289 };
290
291 in-port {
292 port {
293 etf_li
294
295
296 };
297 };
298 };
299 };
300
301 etf@12003000 {
302 compatible = "arm,core
303 reg = <0 0x12003000 0
304 clocks = <&ext_26m>;
305 clock-names = "apb_pcl
306
307 out-ports {
308 port {
309 etf_bi
310
311
312 };
313 };
314 };
315
316 in-ports {
317 port {
318 etf_bi
319
320
321 };
322 };
323 };
324 };
325
326 funnel@12004000 {
327 compatible = "arm,core
328 reg = <0 0x12004000 0
329 clocks = <&ext_26m>;
330 clock-names = "apb_pcl
331
332 out-ports {
333 port {
334 funnel
335
336
337 };
338 };
339 };
340
341 in-ports {
342 #address-cells
343 #size-cells =
344
345 port@0 {
346 reg =
347 funnel
348
349
350 };
351 };
352
353 port@1 {
354 reg =
355 funnel
356
357
358 };
359 };
360 };
361 };
362
363 funnel@12005000 {
364 compatible = "arm,core
365 reg = <0 0x12005000 0
366 clocks = <&ext_26m>;
367 clock-names = "apb_pcl
368
369 out-ports {
370 port {
371 funnel
372
373
374 };
375 };
376 };
377
378 in-ports {
379 #address-cells
380 #size-cells =
381
382 port@0 {
383 reg =
384 funnel
385
386 };
387 };
388
389 port@1 {
390 reg =
391 funnel
392
393 };
394 };
395
396 port@2 {
397 reg =
398 funnel
399
400 };
401 };
402
403 port@3 {
404 reg =
405 funnel
406
407 };
408 };
409 };
410 };
411
412 etm@13040000 {
413 compatible = "arm,core
414 reg = <0 0x13040000 0
415 cpu = <&CPU0>;
416 clocks = <&ext_26m>;
417 clock-names = "apb_pcl
418
419 out-ports {
420 port {
421 etm0_o
422
423
424 };
425 };
426 };
427 };
428
429 etm@13140000 {
430 compatible = "arm,core
431 reg = <0 0x13140000 0
432 cpu = <&CPU1>;
433 clocks = <&ext_26m>;
434 clock-names = "apb_pcl
435
436 out-ports {
437 port {
438 etm1_o
439
440
441 };
442 };
443 };
444 };
445
446 etm@13240000 {
447 compatible = "arm,core
448 reg = <0 0x13240000 0
449 cpu = <&CPU2>;
450 clocks = <&ext_26m>;
451 clock-names = "apb_pcl
452
453 out-ports {
454 port {
455 etm2_o
456
457
458 };
459 };
460 };
461 };
462
463 etm@13340000 {
464 compatible = "arm,core
465 reg = <0 0x13340000 0
466 cpu = <&CPU3>;
467 clocks = <&ext_26m>;
468 clock-names = "apb_pcl
469
470 out-ports {
471 port {
472 etm3_o
473
474
475 };
476 };
477 };
478 };
479
480 etm@13440000 {
481 compatible = "arm,core
482 reg = <0 0x13440000 0
483 cpu = <&CPU4>;
484 clocks = <&ext_26m>;
485 clock-names = "apb_pcl
486
487 out-ports {
488 port {
489 etm4_o
490
491
492 };
493 };
494 };
495 };
496
497 etm@13540000 {
498 compatible = "arm,core
499 reg = <0 0x13540000 0
500 cpu = <&CPU5>;
501 clocks = <&ext_26m>;
502 clock-names = "apb_pcl
503
504 out-ports {
505 port {
506 etm5_o
507
508
509 };
510 };
511 };
512 };
513
514 etm@13640000 {
515 compatible = "arm,core
516 reg = <0 0x13640000 0
517 cpu = <&CPU6>;
518 clocks = <&ext_26m>;
519 clock-names = "apb_pcl
520
521 out-ports {
522 port {
523 etm6_o
524
525
526 };
527 };
528 };
529 };
530
531 etm@13740000 {
532 compatible = "arm,core
533 reg = <0 0x13740000 0
534 cpu = <&CPU7>;
535 clocks = <&ext_26m>;
536 clock-names = "apb_pcl
537
538 out-ports {
539 port {
540 etm7_o
541
542
543 };
544 };
545 };
546 };
547
548 ap-ahb {
549 compatible = "simple-b
550 #address-cells = <2>;
551 #size-cells = <2>;
552 ranges;
553
554 sdio0: mmc@20300000 {
555 compatible = "
556 reg = <0 0x203
557 interrupts = <
558
559 clocks = <&aon
560 <&apa
561 clock-names =
562 assigned-clock
563 assigned-clock
564
565 bus-width = <4
566 no-sdio;
567 no-mmc;
568 };
569
570 sdio3: mmc@20600000 {
571 compatible = "
572 reg = <0 0x206
573 interrupts = <
574
575 clocks = <&aon
576 <&apa
577 clock-names =
578 assigned-clock
579 assigned-clock
580
581 bus-width = <8
582 non-removable;
583 no-sdio;
584 no-sd;
585 cap-mmc-hw-res
586 };
587 };
588 };
589 };
Linux® is a registered trademark of Linus Torvalds in the United States and other countries.
TOMOYO® is a registered trademark of NTT DATA CORPORATION.