1 // SPDX-License-Identifier: GPL-2.0-only 1 // SPDX-License-Identifier: GPL-2.0-only
2 /* 2 /*
3 * Unisoc SC9863A SoC DTS file 3 * Unisoc SC9863A SoC DTS file
4 * 4 *
5 * Copyright (C) 2019, Unisoc Inc. 5 * Copyright (C) 2019, Unisoc Inc.
6 */ 6 */
7 7
8 #include <dt-bindings/clock/sprd,sc9863a-clk.h <<
9 #include <dt-bindings/interrupt-controller/arm 8 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include "sharkl3.dtsi" 9 #include "sharkl3.dtsi"
11 10
12 / { 11 / {
13 cpus { 12 cpus {
14 #address-cells = <2>; 13 #address-cells = <2>;
15 #size-cells = <0>; 14 #size-cells = <0>;
16 15
17 cpu-map { 16 cpu-map {
18 cluster0 { 17 cluster0 {
19 core0 { 18 core0 {
20 cpu = 19 cpu = <&CPU0>;
21 }; 20 };
22 core1 { 21 core1 {
23 cpu = 22 cpu = <&CPU1>;
24 }; 23 };
25 core2 { 24 core2 {
26 cpu = 25 cpu = <&CPU2>;
27 }; 26 };
28 core3 { 27 core3 {
29 cpu = 28 cpu = <&CPU3>;
30 }; 29 };
31 core4 { 30 core4 {
32 cpu = 31 cpu = <&CPU4>;
33 }; 32 };
34 core5 { 33 core5 {
35 cpu = 34 cpu = <&CPU5>;
36 }; 35 };
37 core6 { 36 core6 {
38 cpu = 37 cpu = <&CPU6>;
39 }; 38 };
40 core7 { 39 core7 {
41 cpu = 40 cpu = <&CPU7>;
42 }; 41 };
43 }; 42 };
44 }; 43 };
45 44
46 CPU0: cpu@0 { 45 CPU0: cpu@0 {
47 device_type = "cpu"; 46 device_type = "cpu";
48 compatible = "arm,cort 47 compatible = "arm,cortex-a55";
49 reg = <0x0 0x0>; 48 reg = <0x0 0x0>;
50 enable-method = "psci" 49 enable-method = "psci";
51 cpu-idle-states = <&CO 50 cpu-idle-states = <&CORE_PD>;
52 }; 51 };
53 52
54 CPU1: cpu@100 { 53 CPU1: cpu@100 {
55 device_type = "cpu"; 54 device_type = "cpu";
56 compatible = "arm,cort 55 compatible = "arm,cortex-a55";
57 reg = <0x0 0x100>; 56 reg = <0x0 0x100>;
58 enable-method = "psci" 57 enable-method = "psci";
59 cpu-idle-states = <&CO 58 cpu-idle-states = <&CORE_PD>;
60 }; 59 };
61 60
62 CPU2: cpu@200 { 61 CPU2: cpu@200 {
63 device_type = "cpu"; 62 device_type = "cpu";
64 compatible = "arm,cort 63 compatible = "arm,cortex-a55";
65 reg = <0x0 0x200>; 64 reg = <0x0 0x200>;
66 enable-method = "psci" 65 enable-method = "psci";
67 cpu-idle-states = <&CO 66 cpu-idle-states = <&CORE_PD>;
68 }; 67 };
69 68
70 CPU3: cpu@300 { 69 CPU3: cpu@300 {
71 device_type = "cpu"; 70 device_type = "cpu";
72 compatible = "arm,cort 71 compatible = "arm,cortex-a55";
73 reg = <0x0 0x300>; 72 reg = <0x0 0x300>;
74 enable-method = "psci" 73 enable-method = "psci";
75 cpu-idle-states = <&CO 74 cpu-idle-states = <&CORE_PD>;
76 }; 75 };
77 76
78 CPU4: cpu@400 { 77 CPU4: cpu@400 {
79 device_type = "cpu"; 78 device_type = "cpu";
80 compatible = "arm,cort 79 compatible = "arm,cortex-a55";
81 reg = <0x0 0x400>; 80 reg = <0x0 0x400>;
82 enable-method = "psci" 81 enable-method = "psci";
83 cpu-idle-states = <&CO 82 cpu-idle-states = <&CORE_PD>;
84 }; 83 };
85 84
86 CPU5: cpu@500 { 85 CPU5: cpu@500 {
87 device_type = "cpu"; 86 device_type = "cpu";
88 compatible = "arm,cort 87 compatible = "arm,cortex-a55";
89 reg = <0x0 0x500>; 88 reg = <0x0 0x500>;
90 enable-method = "psci" 89 enable-method = "psci";
91 cpu-idle-states = <&CO 90 cpu-idle-states = <&CORE_PD>;
92 }; 91 };
93 92
94 CPU6: cpu@600 { 93 CPU6: cpu@600 {
95 device_type = "cpu"; 94 device_type = "cpu";
96 compatible = "arm,cort 95 compatible = "arm,cortex-a55";
97 reg = <0x0 0x600>; 96 reg = <0x0 0x600>;
98 enable-method = "psci" 97 enable-method = "psci";
99 cpu-idle-states = <&CO 98 cpu-idle-states = <&CORE_PD>;
100 }; 99 };
101 100
102 CPU7: cpu@700 { 101 CPU7: cpu@700 {
103 device_type = "cpu"; 102 device_type = "cpu";
104 compatible = "arm,cort 103 compatible = "arm,cortex-a55";
105 reg = <0x0 0x700>; 104 reg = <0x0 0x700>;
106 enable-method = "psci" 105 enable-method = "psci";
107 cpu-idle-states = <&CO 106 cpu-idle-states = <&CORE_PD>;
108 }; 107 };
109 }; 108 };
110 109
111 idle-states { 110 idle-states {
112 entry-method = "psci"; 111 entry-method = "psci";
113 CORE_PD: core-pd { 112 CORE_PD: core-pd {
114 compatible = "arm,idle 113 compatible = "arm,idle-state";
115 entry-latency-us = <40 114 entry-latency-us = <4000>;
116 exit-latency-us = <400 115 exit-latency-us = <4000>;
117 min-residency-us = <10 116 min-residency-us = <10000>;
118 local-timer-stop; 117 local-timer-stop;
119 arm,psci-suspend-param 118 arm,psci-suspend-param = <0x00010000>;
120 }; 119 };
121 }; 120 };
122 121
123 psci { 122 psci {
124 compatible = "arm,psci-0.2"; 123 compatible = "arm,psci-0.2";
125 method = "smc"; 124 method = "smc";
126 }; 125 };
127 126
128 timer { 127 timer {
129 compatible = "arm,armv8-timer" 128 compatible = "arm,armv8-timer";
130 interrupts = <GIC_PPI 13 IRQ_T 129 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>, /* Physical Secure PPI */
131 <GIC_PPI 14 IRQ_T 130 <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>, /* Physical Non-Secure PPI */
132 <GIC_PPI 11 IRQ_T 131 <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>, /* Virtual PPI */
133 <GIC_PPI 10 IRQ_T 132 <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>; /* Hipervisor PPI */
134 }; 133 };
135 134
136 pmu { 135 pmu {
137 compatible = "arm,cortex-a55-p !! 136 compatible = "arm,armv8-pmuv3";
138 interrupts = <GIC_SPI 144 IRQ_ 137 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
139 <GIC_SPI 145 IRQ_ 138 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
140 <GIC_SPI 146 IRQ_ 139 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
141 <GIC_SPI 147 IRQ_ 140 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
142 <GIC_SPI 148 IRQ_ 141 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
143 <GIC_SPI 149 IRQ_ 142 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
144 <GIC_SPI 150 IRQ_ 143 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
145 <GIC_SPI 151 IRQ_ 144 <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
146 }; 145 };
147 146
148 soc { 147 soc {
149 gic: interrupt-controller@1400 148 gic: interrupt-controller@14000000 {
150 compatible = "arm,gic- 149 compatible = "arm,gic-v3";
151 #interrupt-cells = <3> 150 #interrupt-cells = <3>;
152 #address-cells = <2>; 151 #address-cells = <2>;
153 #size-cells = <2>; 152 #size-cells = <2>;
154 ranges; 153 ranges;
155 redistributor-stride = 154 redistributor-stride = <0x0 0x20000>; /* 128KB stride */
156 #redistributor-regions 155 #redistributor-regions = <1>;
157 interrupt-controller; 156 interrupt-controller;
158 reg = <0x0 0x14000000 157 reg = <0x0 0x14000000 0 0x20000>, /* GICD */
159 <0x0 0x14040000 158 <0x0 0x14040000 0 0x100000>; /* GICR */
160 interrupts = <GIC_PPI 159 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
161 }; 160 };
162 161
163 ap_clk: clock-controller@21500 <<
164 compatible = "sprd,sc9 <<
165 reg = <0 0x21500000 0 <<
166 clocks = <&ext_32k>, < <<
167 clock-names = "ext-32k <<
168 #clock-cells = <1>; <<
169 }; <<
170 <<
171 aon_clk: clock-controller@402d <<
172 compatible = "sprd,sc9 <<
173 reg = <0 0x402d0000 0 <<
174 clocks = <&ext_26m>, < <<
175 <&ext_32k>, < <<
176 clock-names = "ext-26m <<
177 "ext-32k <<
178 #clock-cells = <1>; <<
179 }; <<
180 <<
181 mm_clk: clock-controller@60900 <<
182 compatible = "sprd,sc9 <<
183 reg = <0 0x60900000 0 <<
184 #clock-cells = <1>; <<
185 }; <<
186 <<
187 funnel@10001000 { 162 funnel@10001000 {
188 compatible = "arm,core 163 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
189 reg = <0 0x10001000 0 164 reg = <0 0x10001000 0 0x1000>;
190 clocks = <&ext_26m>; 165 clocks = <&ext_26m>;
191 clock-names = "apb_pcl 166 clock-names = "apb_pclk";
192 167
193 out-ports { 168 out-ports {
194 port { 169 port {
195 funnel 170 funnel_soc_out_port: endpoint {
196 171 remote-endpoint = <&etb_in>;
197 }; 172 };
198 }; 173 };
199 }; 174 };
200 175
201 in-ports { 176 in-ports {
202 port { 177 port {
203 funnel 178 funnel_soc_in_port: endpoint {
204 179 remote-endpoint =
205 180 <&funnel_ca55_out_port>;
206 }; 181 };
207 }; 182 };
208 }; 183 };
209 }; 184 };
210 185
211 etb@10003000 { 186 etb@10003000 {
212 compatible = "arm,core 187 compatible = "arm,coresight-tmc", "arm,primecell";
213 reg = <0 0x10003000 0 188 reg = <0 0x10003000 0 0x1000>;
214 clocks = <&ext_26m>; 189 clocks = <&ext_26m>;
215 clock-names = "apb_pcl 190 clock-names = "apb_pclk";
216 191
217 in-ports { 192 in-ports {
218 port { 193 port {
219 etb_in 194 etb_in: endpoint {
220 195 remote-endpoint =
221 196 <&funnel_soc_out_port>;
222 }; 197 };
223 }; 198 };
224 }; 199 };
225 }; 200 };
226 201
227 funnel@12001000 { 202 funnel@12001000 {
228 compatible = "arm,core 203 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
229 reg = <0 0x12001000 0 204 reg = <0 0x12001000 0 0x1000>;
230 clocks = <&ext_26m>; 205 clocks = <&ext_26m>;
231 clock-names = "apb_pcl 206 clock-names = "apb_pclk";
232 207
233 out-ports { 208 out-ports {
234 port { 209 port {
235 funnel 210 funnel_little_out_port: endpoint {
236 211 remote-endpoint =
237 212 <&etf_little_in>;
238 }; 213 };
239 }; 214 };
240 }; 215 };
241 216
242 in-ports { 217 in-ports {
243 #address-cells 218 #address-cells = <1>;
244 #size-cells = 219 #size-cells = <0>;
245 220
246 port@0 { 221 port@0 {
247 reg = 222 reg = <0>;
248 funnel 223 funnel_little_in_port0: endpoint {
249 224 remote-endpoint = <&etm0_out>;
250 }; 225 };
251 }; 226 };
252 227
253 port@1 { 228 port@1 {
254 reg = 229 reg = <1>;
255 funnel 230 funnel_little_in_port1: endpoint {
256 231 remote-endpoint = <&etm1_out>;
257 }; 232 };
258 }; 233 };
259 234
260 port@2 { 235 port@2 {
261 reg = 236 reg = <2>;
262 funnel 237 funnel_little_in_port2: endpoint {
263 238 remote-endpoint = <&etm2_out>;
264 }; 239 };
265 }; 240 };
266 241
267 port@3 { 242 port@3 {
268 reg = 243 reg = <3>;
269 funnel 244 funnel_little_in_port3: endpoint {
270 245 remote-endpoint = <&etm3_out>;
271 }; 246 };
272 }; 247 };
273 }; 248 };
274 }; 249 };
275 250
276 etf@12002000 { 251 etf@12002000 {
277 compatible = "arm,core 252 compatible = "arm,coresight-tmc", "arm,primecell";
278 reg = <0 0x12002000 0 253 reg = <0 0x12002000 0 0x1000>;
279 clocks = <&ext_26m>; 254 clocks = <&ext_26m>;
280 clock-names = "apb_pcl 255 clock-names = "apb_pclk";
281 256
282 out-ports { 257 out-ports {
283 port { 258 port {
284 etf_li 259 etf_little_out: endpoint {
285 260 remote-endpoint =
286 261 <&funnel_ca55_in_port0>;
287 }; 262 };
288 }; 263 };
289 }; 264 };
290 265
291 in-port { 266 in-port {
292 port { 267 port {
293 etf_li 268 etf_little_in: endpoint {
294 269 remote-endpoint =
295 270 <&funnel_little_out_port>;
296 }; 271 };
297 }; 272 };
298 }; 273 };
299 }; 274 };
300 275
301 etf@12003000 { 276 etf@12003000 {
302 compatible = "arm,core 277 compatible = "arm,coresight-tmc", "arm,primecell";
303 reg = <0 0x12003000 0 278 reg = <0 0x12003000 0 0x1000>;
304 clocks = <&ext_26m>; 279 clocks = <&ext_26m>;
305 clock-names = "apb_pcl 280 clock-names = "apb_pclk";
306 281
307 out-ports { 282 out-ports {
308 port { 283 port {
309 etf_bi 284 etf_big_out: endpoint {
310 285 remote-endpoint =
311 286 <&funnel_ca55_in_port1>;
312 }; 287 };
313 }; 288 };
314 }; 289 };
315 290
316 in-ports { 291 in-ports {
317 port { 292 port {
318 etf_bi 293 etf_big_in: endpoint {
319 294 remote-endpoint =
320 295 <&funnel_big_out_port>;
321 }; 296 };
322 }; 297 };
323 }; 298 };
324 }; 299 };
325 300
326 funnel@12004000 { 301 funnel@12004000 {
327 compatible = "arm,core 302 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
328 reg = <0 0x12004000 0 303 reg = <0 0x12004000 0 0x1000>;
329 clocks = <&ext_26m>; 304 clocks = <&ext_26m>;
330 clock-names = "apb_pcl 305 clock-names = "apb_pclk";
331 306
332 out-ports { 307 out-ports {
333 port { 308 port {
334 funnel 309 funnel_ca55_out_port: endpoint {
335 310 remote-endpoint =
336 311 <&funnel_soc_in_port>;
337 }; 312 };
338 }; 313 };
339 }; 314 };
340 315
341 in-ports { 316 in-ports {
342 #address-cells 317 #address-cells = <1>;
343 #size-cells = 318 #size-cells = <0>;
344 319
345 port@0 { 320 port@0 {
346 reg = 321 reg = <0>;
347 funnel 322 funnel_ca55_in_port0: endpoint {
348 323 remote-endpoint =
349 324 <&etf_little_out>;
350 }; 325 };
351 }; 326 };
352 327
353 port@1 { 328 port@1 {
354 reg = 329 reg = <1>;
355 funnel 330 funnel_ca55_in_port1: endpoint {
356 331 remote-endpoint =
357 332 <&etf_big_out>;
358 }; 333 };
359 }; 334 };
360 }; 335 };
361 }; 336 };
362 337
363 funnel@12005000 { 338 funnel@12005000 {
364 compatible = "arm,core 339 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
365 reg = <0 0x12005000 0 340 reg = <0 0x12005000 0 0x1000>;
366 clocks = <&ext_26m>; 341 clocks = <&ext_26m>;
367 clock-names = "apb_pcl 342 clock-names = "apb_pclk";
368 343
369 out-ports { 344 out-ports {
370 port { 345 port {
371 funnel 346 funnel_big_out_port: endpoint {
372 347 remote-endpoint =
373 348 <&etf_big_in>;
374 }; 349 };
375 }; 350 };
376 }; 351 };
377 352
378 in-ports { 353 in-ports {
379 #address-cells 354 #address-cells = <1>;
380 #size-cells = 355 #size-cells = <0>;
381 356
382 port@0 { 357 port@0 {
383 reg = 358 reg = <0>;
384 funnel 359 funnel_big_in_port0: endpoint {
385 360 remote-endpoint = <&etm4_out>;
386 }; 361 };
387 }; 362 };
388 363
389 port@1 { 364 port@1 {
390 reg = 365 reg = <1>;
391 funnel 366 funnel_big_in_port1: endpoint {
392 367 remote-endpoint = <&etm5_out>;
393 }; 368 };
394 }; 369 };
395 370
396 port@2 { 371 port@2 {
397 reg = 372 reg = <2>;
398 funnel 373 funnel_big_in_port2: endpoint {
399 374 remote-endpoint = <&etm6_out>;
400 }; 375 };
401 }; 376 };
402 377
403 port@3 { 378 port@3 {
404 reg = 379 reg = <3>;
405 funnel 380 funnel_big_in_port3: endpoint {
406 381 remote-endpoint = <&etm7_out>;
407 }; 382 };
408 }; 383 };
409 }; 384 };
410 }; 385 };
411 386
412 etm@13040000 { 387 etm@13040000 {
413 compatible = "arm,core 388 compatible = "arm,coresight-etm4x", "arm,primecell";
414 reg = <0 0x13040000 0 389 reg = <0 0x13040000 0 0x1000>;
415 cpu = <&CPU0>; 390 cpu = <&CPU0>;
416 clocks = <&ext_26m>; 391 clocks = <&ext_26m>;
417 clock-names = "apb_pcl 392 clock-names = "apb_pclk";
418 393
419 out-ports { 394 out-ports {
420 port { 395 port {
421 etm0_o 396 etm0_out: endpoint {
422 397 remote-endpoint =
423 398 <&funnel_little_in_port0>;
424 }; 399 };
425 }; 400 };
426 }; 401 };
427 }; 402 };
428 403
429 etm@13140000 { 404 etm@13140000 {
430 compatible = "arm,core 405 compatible = "arm,coresight-etm4x", "arm,primecell";
431 reg = <0 0x13140000 0 406 reg = <0 0x13140000 0 0x1000>;
432 cpu = <&CPU1>; 407 cpu = <&CPU1>;
433 clocks = <&ext_26m>; 408 clocks = <&ext_26m>;
434 clock-names = "apb_pcl 409 clock-names = "apb_pclk";
435 410
436 out-ports { 411 out-ports {
437 port { 412 port {
438 etm1_o 413 etm1_out: endpoint {
439 414 remote-endpoint =
440 415 <&funnel_little_in_port1>;
441 }; 416 };
442 }; 417 };
443 }; 418 };
444 }; 419 };
445 420
446 etm@13240000 { 421 etm@13240000 {
447 compatible = "arm,core 422 compatible = "arm,coresight-etm4x", "arm,primecell";
448 reg = <0 0x13240000 0 423 reg = <0 0x13240000 0 0x1000>;
449 cpu = <&CPU2>; 424 cpu = <&CPU2>;
450 clocks = <&ext_26m>; 425 clocks = <&ext_26m>;
451 clock-names = "apb_pcl 426 clock-names = "apb_pclk";
452 427
453 out-ports { 428 out-ports {
454 port { 429 port {
455 etm2_o 430 etm2_out: endpoint {
456 431 remote-endpoint =
457 432 <&funnel_little_in_port2>;
458 }; 433 };
459 }; 434 };
460 }; 435 };
461 }; 436 };
462 437
463 etm@13340000 { 438 etm@13340000 {
464 compatible = "arm,core 439 compatible = "arm,coresight-etm4x", "arm,primecell";
465 reg = <0 0x13340000 0 440 reg = <0 0x13340000 0 0x1000>;
466 cpu = <&CPU3>; 441 cpu = <&CPU3>;
467 clocks = <&ext_26m>; 442 clocks = <&ext_26m>;
468 clock-names = "apb_pcl 443 clock-names = "apb_pclk";
469 444
470 out-ports { 445 out-ports {
471 port { 446 port {
472 etm3_o 447 etm3_out: endpoint {
473 448 remote-endpoint =
474 449 <&funnel_little_in_port3>;
475 }; 450 };
476 }; 451 };
477 }; 452 };
478 }; 453 };
479 454
480 etm@13440000 { 455 etm@13440000 {
481 compatible = "arm,core 456 compatible = "arm,coresight-etm4x", "arm,primecell";
482 reg = <0 0x13440000 0 457 reg = <0 0x13440000 0 0x1000>;
483 cpu = <&CPU4>; 458 cpu = <&CPU4>;
484 clocks = <&ext_26m>; 459 clocks = <&ext_26m>;
485 clock-names = "apb_pcl 460 clock-names = "apb_pclk";
486 461
487 out-ports { 462 out-ports {
488 port { 463 port {
489 etm4_o 464 etm4_out: endpoint {
490 465 remote-endpoint =
491 466 <&funnel_big_in_port0>;
492 }; 467 };
493 }; 468 };
494 }; 469 };
495 }; 470 };
496 471
497 etm@13540000 { 472 etm@13540000 {
498 compatible = "arm,core 473 compatible = "arm,coresight-etm4x", "arm,primecell";
499 reg = <0 0x13540000 0 474 reg = <0 0x13540000 0 0x1000>;
500 cpu = <&CPU5>; 475 cpu = <&CPU5>;
501 clocks = <&ext_26m>; 476 clocks = <&ext_26m>;
502 clock-names = "apb_pcl 477 clock-names = "apb_pclk";
503 478
504 out-ports { 479 out-ports {
505 port { 480 port {
506 etm5_o 481 etm5_out: endpoint {
507 482 remote-endpoint =
508 483 <&funnel_big_in_port1>;
509 }; 484 };
510 }; 485 };
511 }; 486 };
512 }; 487 };
513 488
514 etm@13640000 { 489 etm@13640000 {
515 compatible = "arm,core 490 compatible = "arm,coresight-etm4x", "arm,primecell";
516 reg = <0 0x13640000 0 491 reg = <0 0x13640000 0 0x1000>;
517 cpu = <&CPU6>; 492 cpu = <&CPU6>;
518 clocks = <&ext_26m>; 493 clocks = <&ext_26m>;
519 clock-names = "apb_pcl 494 clock-names = "apb_pclk";
520 495
521 out-ports { 496 out-ports {
522 port { 497 port {
523 etm6_o 498 etm6_out: endpoint {
524 499 remote-endpoint =
525 500 <&funnel_big_in_port2>;
526 }; 501 };
527 }; 502 };
528 }; 503 };
529 }; 504 };
530 505
531 etm@13740000 { 506 etm@13740000 {
532 compatible = "arm,core 507 compatible = "arm,coresight-etm4x", "arm,primecell";
533 reg = <0 0x13740000 0 508 reg = <0 0x13740000 0 0x1000>;
534 cpu = <&CPU7>; 509 cpu = <&CPU7>;
535 clocks = <&ext_26m>; 510 clocks = <&ext_26m>;
536 clock-names = "apb_pcl 511 clock-names = "apb_pclk";
537 512
538 out-ports { 513 out-ports {
539 port { 514 port {
540 etm7_o 515 etm7_out: endpoint {
541 516 remote-endpoint =
542 517 <&funnel_big_in_port3>;
543 }; 518 };
544 }; 519 };
545 }; <<
546 }; <<
547 <<
548 ap-ahb { <<
549 compatible = "simple-b <<
550 #address-cells = <2>; <<
551 #size-cells = <2>; <<
552 ranges; <<
553 <<
554 sdio0: mmc@20300000 { <<
555 compatible = " <<
556 reg = <0 0x203 <<
557 interrupts = < <<
558 <<
559 clocks = <&aon <<
560 <&apa <<
561 clock-names = <<
562 assigned-clock <<
563 assigned-clock <<
564 <<
565 bus-width = <4 <<
566 no-sdio; <<
567 no-mmc; <<
568 }; <<
569 <<
570 sdio3: mmc@20600000 { <<
571 compatible = " <<
572 reg = <0 0x206 <<
573 interrupts = < <<
574 <<
575 clocks = <&aon <<
576 <&apa <<
577 clock-names = <<
578 assigned-clock <<
579 assigned-clock <<
580 <<
581 bus-width = <8 <<
582 non-removable; <<
583 no-sdio; <<
584 no-sd; <<
585 cap-mmc-hw-res <<
586 }; 520 };
587 }; 521 };
588 }; 522 };
589 }; 523 };
Linux® is a registered trademark of Linus Torvalds in the United States and other countries.
TOMOYO® is a registered trademark of NTT DATA CORPORATION.