1 // SPDX-License-Identifier: GPL-2.0-only 1 // SPDX-License-Identifier: GPL-2.0-only
2 /* 2 /*
3 * Unisoc SC9863A SoC DTS file 3 * Unisoc SC9863A SoC DTS file
4 * 4 *
5 * Copyright (C) 2019, Unisoc Inc. 5 * Copyright (C) 2019, Unisoc Inc.
6 */ 6 */
7 7
8 #include <dt-bindings/clock/sprd,sc9863a-clk.h 8 #include <dt-bindings/clock/sprd,sc9863a-clk.h>
9 #include <dt-bindings/interrupt-controller/arm 9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include "sharkl3.dtsi" 10 #include "sharkl3.dtsi"
11 11
12 / { 12 / {
13 cpus { 13 cpus {
14 #address-cells = <2>; 14 #address-cells = <2>;
15 #size-cells = <0>; 15 #size-cells = <0>;
16 16
17 cpu-map { 17 cpu-map {
18 cluster0 { 18 cluster0 {
19 core0 { 19 core0 {
20 cpu = 20 cpu = <&CPU0>;
21 }; 21 };
22 core1 { 22 core1 {
23 cpu = 23 cpu = <&CPU1>;
24 }; 24 };
25 core2 { 25 core2 {
26 cpu = 26 cpu = <&CPU2>;
27 }; 27 };
28 core3 { 28 core3 {
29 cpu = 29 cpu = <&CPU3>;
30 }; 30 };
31 core4 { 31 core4 {
32 cpu = 32 cpu = <&CPU4>;
33 }; 33 };
34 core5 { 34 core5 {
35 cpu = 35 cpu = <&CPU5>;
36 }; 36 };
37 core6 { 37 core6 {
38 cpu = 38 cpu = <&CPU6>;
39 }; 39 };
40 core7 { 40 core7 {
41 cpu = 41 cpu = <&CPU7>;
42 }; 42 };
43 }; 43 };
44 }; 44 };
45 45
46 CPU0: cpu@0 { 46 CPU0: cpu@0 {
47 device_type = "cpu"; 47 device_type = "cpu";
48 compatible = "arm,cort 48 compatible = "arm,cortex-a55";
49 reg = <0x0 0x0>; 49 reg = <0x0 0x0>;
50 enable-method = "psci" 50 enable-method = "psci";
51 cpu-idle-states = <&CO 51 cpu-idle-states = <&CORE_PD>;
52 }; 52 };
53 53
54 CPU1: cpu@100 { 54 CPU1: cpu@100 {
55 device_type = "cpu"; 55 device_type = "cpu";
56 compatible = "arm,cort 56 compatible = "arm,cortex-a55";
57 reg = <0x0 0x100>; 57 reg = <0x0 0x100>;
58 enable-method = "psci" 58 enable-method = "psci";
59 cpu-idle-states = <&CO 59 cpu-idle-states = <&CORE_PD>;
60 }; 60 };
61 61
62 CPU2: cpu@200 { 62 CPU2: cpu@200 {
63 device_type = "cpu"; 63 device_type = "cpu";
64 compatible = "arm,cort 64 compatible = "arm,cortex-a55";
65 reg = <0x0 0x200>; 65 reg = <0x0 0x200>;
66 enable-method = "psci" 66 enable-method = "psci";
67 cpu-idle-states = <&CO 67 cpu-idle-states = <&CORE_PD>;
68 }; 68 };
69 69
70 CPU3: cpu@300 { 70 CPU3: cpu@300 {
71 device_type = "cpu"; 71 device_type = "cpu";
72 compatible = "arm,cort 72 compatible = "arm,cortex-a55";
73 reg = <0x0 0x300>; 73 reg = <0x0 0x300>;
74 enable-method = "psci" 74 enable-method = "psci";
75 cpu-idle-states = <&CO 75 cpu-idle-states = <&CORE_PD>;
76 }; 76 };
77 77
78 CPU4: cpu@400 { 78 CPU4: cpu@400 {
79 device_type = "cpu"; 79 device_type = "cpu";
80 compatible = "arm,cort 80 compatible = "arm,cortex-a55";
81 reg = <0x0 0x400>; 81 reg = <0x0 0x400>;
82 enable-method = "psci" 82 enable-method = "psci";
83 cpu-idle-states = <&CO 83 cpu-idle-states = <&CORE_PD>;
84 }; 84 };
85 85
86 CPU5: cpu@500 { 86 CPU5: cpu@500 {
87 device_type = "cpu"; 87 device_type = "cpu";
88 compatible = "arm,cort 88 compatible = "arm,cortex-a55";
89 reg = <0x0 0x500>; 89 reg = <0x0 0x500>;
90 enable-method = "psci" 90 enable-method = "psci";
91 cpu-idle-states = <&CO 91 cpu-idle-states = <&CORE_PD>;
92 }; 92 };
93 93
94 CPU6: cpu@600 { 94 CPU6: cpu@600 {
95 device_type = "cpu"; 95 device_type = "cpu";
96 compatible = "arm,cort 96 compatible = "arm,cortex-a55";
97 reg = <0x0 0x600>; 97 reg = <0x0 0x600>;
98 enable-method = "psci" 98 enable-method = "psci";
99 cpu-idle-states = <&CO 99 cpu-idle-states = <&CORE_PD>;
100 }; 100 };
101 101
102 CPU7: cpu@700 { 102 CPU7: cpu@700 {
103 device_type = "cpu"; 103 device_type = "cpu";
104 compatible = "arm,cort 104 compatible = "arm,cortex-a55";
105 reg = <0x0 0x700>; 105 reg = <0x0 0x700>;
106 enable-method = "psci" 106 enable-method = "psci";
107 cpu-idle-states = <&CO 107 cpu-idle-states = <&CORE_PD>;
108 }; 108 };
109 }; 109 };
110 110
111 idle-states { 111 idle-states {
112 entry-method = "psci"; 112 entry-method = "psci";
113 CORE_PD: core-pd { 113 CORE_PD: core-pd {
114 compatible = "arm,idle 114 compatible = "arm,idle-state";
115 entry-latency-us = <40 115 entry-latency-us = <4000>;
116 exit-latency-us = <400 116 exit-latency-us = <4000>;
117 min-residency-us = <10 117 min-residency-us = <10000>;
118 local-timer-stop; 118 local-timer-stop;
119 arm,psci-suspend-param 119 arm,psci-suspend-param = <0x00010000>;
120 }; 120 };
121 }; 121 };
122 122
123 psci { 123 psci {
124 compatible = "arm,psci-0.2"; 124 compatible = "arm,psci-0.2";
125 method = "smc"; 125 method = "smc";
126 }; 126 };
127 127
128 timer { 128 timer {
129 compatible = "arm,armv8-timer" 129 compatible = "arm,armv8-timer";
130 interrupts = <GIC_PPI 13 IRQ_T 130 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>, /* Physical Secure PPI */
131 <GIC_PPI 14 IRQ_T 131 <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>, /* Physical Non-Secure PPI */
132 <GIC_PPI 11 IRQ_T 132 <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>, /* Virtual PPI */
133 <GIC_PPI 10 IRQ_T 133 <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>; /* Hipervisor PPI */
134 }; 134 };
135 135
136 pmu { 136 pmu {
137 compatible = "arm,cortex-a55-p !! 137 compatible = "arm,armv8-pmuv3";
138 interrupts = <GIC_SPI 144 IRQ_ 138 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
139 <GIC_SPI 145 IRQ_ 139 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
140 <GIC_SPI 146 IRQ_ 140 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
141 <GIC_SPI 147 IRQ_ 141 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
142 <GIC_SPI 148 IRQ_ 142 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
143 <GIC_SPI 149 IRQ_ 143 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
144 <GIC_SPI 150 IRQ_ 144 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
145 <GIC_SPI 151 IRQ_ 145 <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
146 }; 146 };
147 147
148 soc { 148 soc {
149 gic: interrupt-controller@1400 149 gic: interrupt-controller@14000000 {
150 compatible = "arm,gic- 150 compatible = "arm,gic-v3";
151 #interrupt-cells = <3> 151 #interrupt-cells = <3>;
152 #address-cells = <2>; 152 #address-cells = <2>;
153 #size-cells = <2>; 153 #size-cells = <2>;
154 ranges; 154 ranges;
155 redistributor-stride = 155 redistributor-stride = <0x0 0x20000>; /* 128KB stride */
156 #redistributor-regions 156 #redistributor-regions = <1>;
157 interrupt-controller; 157 interrupt-controller;
158 reg = <0x0 0x14000000 158 reg = <0x0 0x14000000 0 0x20000>, /* GICD */
159 <0x0 0x14040000 159 <0x0 0x14040000 0 0x100000>; /* GICR */
160 interrupts = <GIC_PPI 160 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
161 }; 161 };
162 162
163 ap_clk: clock-controller@21500 163 ap_clk: clock-controller@21500000 {
164 compatible = "sprd,sc9 164 compatible = "sprd,sc9863a-ap-clk";
165 reg = <0 0x21500000 0 165 reg = <0 0x21500000 0 0x1000>;
166 clocks = <&ext_32k>, < 166 clocks = <&ext_32k>, <&ext_26m>;
167 clock-names = "ext-32k 167 clock-names = "ext-32k", "ext-26m";
168 #clock-cells = <1>; 168 #clock-cells = <1>;
169 }; 169 };
170 170
171 aon_clk: clock-controller@402d 171 aon_clk: clock-controller@402d0000 {
172 compatible = "sprd,sc9 172 compatible = "sprd,sc9863a-aon-clk";
173 reg = <0 0x402d0000 0 173 reg = <0 0x402d0000 0 0x1000>;
174 clocks = <&ext_26m>, < 174 clocks = <&ext_26m>, <&rco_100m>,
175 <&ext_32k>, < 175 <&ext_32k>, <&ext_4m>;
176 clock-names = "ext-26m 176 clock-names = "ext-26m", "rco-100m",
177 "ext-32k 177 "ext-32k", "ext-4m";
178 #clock-cells = <1>; 178 #clock-cells = <1>;
179 }; 179 };
180 180
181 mm_clk: clock-controller@60900 181 mm_clk: clock-controller@60900000 {
182 compatible = "sprd,sc9 182 compatible = "sprd,sc9863a-mm-clk";
183 reg = <0 0x60900000 0 183 reg = <0 0x60900000 0 0x1000>;
184 #clock-cells = <1>; 184 #clock-cells = <1>;
185 }; 185 };
186 186
187 funnel@10001000 { 187 funnel@10001000 {
188 compatible = "arm,core 188 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
189 reg = <0 0x10001000 0 189 reg = <0 0x10001000 0 0x1000>;
190 clocks = <&ext_26m>; 190 clocks = <&ext_26m>;
191 clock-names = "apb_pcl 191 clock-names = "apb_pclk";
192 192
193 out-ports { 193 out-ports {
194 port { 194 port {
195 funnel 195 funnel_soc_out_port: endpoint {
196 196 remote-endpoint = <&etb_in>;
197 }; 197 };
198 }; 198 };
199 }; 199 };
200 200
201 in-ports { 201 in-ports {
202 port { 202 port {
203 funnel 203 funnel_soc_in_port: endpoint {
204 204 remote-endpoint =
205 205 <&funnel_ca55_out_port>;
206 }; 206 };
207 }; 207 };
208 }; 208 };
209 }; 209 };
210 210
211 etb@10003000 { 211 etb@10003000 {
212 compatible = "arm,core 212 compatible = "arm,coresight-tmc", "arm,primecell";
213 reg = <0 0x10003000 0 213 reg = <0 0x10003000 0 0x1000>;
214 clocks = <&ext_26m>; 214 clocks = <&ext_26m>;
215 clock-names = "apb_pcl 215 clock-names = "apb_pclk";
216 216
217 in-ports { 217 in-ports {
218 port { 218 port {
219 etb_in 219 etb_in: endpoint {
220 220 remote-endpoint =
221 221 <&funnel_soc_out_port>;
222 }; 222 };
223 }; 223 };
224 }; 224 };
225 }; 225 };
226 226
227 funnel@12001000 { 227 funnel@12001000 {
228 compatible = "arm,core 228 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
229 reg = <0 0x12001000 0 229 reg = <0 0x12001000 0 0x1000>;
230 clocks = <&ext_26m>; 230 clocks = <&ext_26m>;
231 clock-names = "apb_pcl 231 clock-names = "apb_pclk";
232 232
233 out-ports { 233 out-ports {
234 port { 234 port {
235 funnel 235 funnel_little_out_port: endpoint {
236 236 remote-endpoint =
237 237 <&etf_little_in>;
238 }; 238 };
239 }; 239 };
240 }; 240 };
241 241
242 in-ports { 242 in-ports {
243 #address-cells 243 #address-cells = <1>;
244 #size-cells = 244 #size-cells = <0>;
245 245
246 port@0 { 246 port@0 {
247 reg = 247 reg = <0>;
248 funnel 248 funnel_little_in_port0: endpoint {
249 249 remote-endpoint = <&etm0_out>;
250 }; 250 };
251 }; 251 };
252 252
253 port@1 { 253 port@1 {
254 reg = 254 reg = <1>;
255 funnel 255 funnel_little_in_port1: endpoint {
256 256 remote-endpoint = <&etm1_out>;
257 }; 257 };
258 }; 258 };
259 259
260 port@2 { 260 port@2 {
261 reg = 261 reg = <2>;
262 funnel 262 funnel_little_in_port2: endpoint {
263 263 remote-endpoint = <&etm2_out>;
264 }; 264 };
265 }; 265 };
266 266
267 port@3 { 267 port@3 {
268 reg = 268 reg = <3>;
269 funnel 269 funnel_little_in_port3: endpoint {
270 270 remote-endpoint = <&etm3_out>;
271 }; 271 };
272 }; 272 };
273 }; 273 };
274 }; 274 };
275 275
276 etf@12002000 { 276 etf@12002000 {
277 compatible = "arm,core 277 compatible = "arm,coresight-tmc", "arm,primecell";
278 reg = <0 0x12002000 0 278 reg = <0 0x12002000 0 0x1000>;
279 clocks = <&ext_26m>; 279 clocks = <&ext_26m>;
280 clock-names = "apb_pcl 280 clock-names = "apb_pclk";
281 281
282 out-ports { 282 out-ports {
283 port { 283 port {
284 etf_li 284 etf_little_out: endpoint {
285 285 remote-endpoint =
286 286 <&funnel_ca55_in_port0>;
287 }; 287 };
288 }; 288 };
289 }; 289 };
290 290
291 in-port { 291 in-port {
292 port { 292 port {
293 etf_li 293 etf_little_in: endpoint {
294 294 remote-endpoint =
295 295 <&funnel_little_out_port>;
296 }; 296 };
297 }; 297 };
298 }; 298 };
299 }; 299 };
300 300
301 etf@12003000 { 301 etf@12003000 {
302 compatible = "arm,core 302 compatible = "arm,coresight-tmc", "arm,primecell";
303 reg = <0 0x12003000 0 303 reg = <0 0x12003000 0 0x1000>;
304 clocks = <&ext_26m>; 304 clocks = <&ext_26m>;
305 clock-names = "apb_pcl 305 clock-names = "apb_pclk";
306 306
307 out-ports { 307 out-ports {
308 port { 308 port {
309 etf_bi 309 etf_big_out: endpoint {
310 310 remote-endpoint =
311 311 <&funnel_ca55_in_port1>;
312 }; 312 };
313 }; 313 };
314 }; 314 };
315 315
316 in-ports { 316 in-ports {
317 port { 317 port {
318 etf_bi 318 etf_big_in: endpoint {
319 319 remote-endpoint =
320 320 <&funnel_big_out_port>;
321 }; 321 };
322 }; 322 };
323 }; 323 };
324 }; 324 };
325 325
326 funnel@12004000 { 326 funnel@12004000 {
327 compatible = "arm,core 327 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
328 reg = <0 0x12004000 0 328 reg = <0 0x12004000 0 0x1000>;
329 clocks = <&ext_26m>; 329 clocks = <&ext_26m>;
330 clock-names = "apb_pcl 330 clock-names = "apb_pclk";
331 331
332 out-ports { 332 out-ports {
333 port { 333 port {
334 funnel 334 funnel_ca55_out_port: endpoint {
335 335 remote-endpoint =
336 336 <&funnel_soc_in_port>;
337 }; 337 };
338 }; 338 };
339 }; 339 };
340 340
341 in-ports { 341 in-ports {
342 #address-cells 342 #address-cells = <1>;
343 #size-cells = 343 #size-cells = <0>;
344 344
345 port@0 { 345 port@0 {
346 reg = 346 reg = <0>;
347 funnel 347 funnel_ca55_in_port0: endpoint {
348 348 remote-endpoint =
349 349 <&etf_little_out>;
350 }; 350 };
351 }; 351 };
352 352
353 port@1 { 353 port@1 {
354 reg = 354 reg = <1>;
355 funnel 355 funnel_ca55_in_port1: endpoint {
356 356 remote-endpoint =
357 357 <&etf_big_out>;
358 }; 358 };
359 }; 359 };
360 }; 360 };
361 }; 361 };
362 362
363 funnel@12005000 { 363 funnel@12005000 {
364 compatible = "arm,core 364 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
365 reg = <0 0x12005000 0 365 reg = <0 0x12005000 0 0x1000>;
366 clocks = <&ext_26m>; 366 clocks = <&ext_26m>;
367 clock-names = "apb_pcl 367 clock-names = "apb_pclk";
368 368
369 out-ports { 369 out-ports {
370 port { 370 port {
371 funnel 371 funnel_big_out_port: endpoint {
372 372 remote-endpoint =
373 373 <&etf_big_in>;
374 }; 374 };
375 }; 375 };
376 }; 376 };
377 377
378 in-ports { 378 in-ports {
379 #address-cells 379 #address-cells = <1>;
380 #size-cells = 380 #size-cells = <0>;
381 381
382 port@0 { 382 port@0 {
383 reg = 383 reg = <0>;
384 funnel 384 funnel_big_in_port0: endpoint {
385 385 remote-endpoint = <&etm4_out>;
386 }; 386 };
387 }; 387 };
388 388
389 port@1 { 389 port@1 {
390 reg = 390 reg = <1>;
391 funnel 391 funnel_big_in_port1: endpoint {
392 392 remote-endpoint = <&etm5_out>;
393 }; 393 };
394 }; 394 };
395 395
396 port@2 { 396 port@2 {
397 reg = 397 reg = <2>;
398 funnel 398 funnel_big_in_port2: endpoint {
399 399 remote-endpoint = <&etm6_out>;
400 }; 400 };
401 }; 401 };
402 402
403 port@3 { 403 port@3 {
404 reg = 404 reg = <3>;
405 funnel 405 funnel_big_in_port3: endpoint {
406 406 remote-endpoint = <&etm7_out>;
407 }; 407 };
408 }; 408 };
409 }; 409 };
410 }; 410 };
411 411
412 etm@13040000 { 412 etm@13040000 {
413 compatible = "arm,core 413 compatible = "arm,coresight-etm4x", "arm,primecell";
414 reg = <0 0x13040000 0 414 reg = <0 0x13040000 0 0x1000>;
415 cpu = <&CPU0>; 415 cpu = <&CPU0>;
416 clocks = <&ext_26m>; 416 clocks = <&ext_26m>;
417 clock-names = "apb_pcl 417 clock-names = "apb_pclk";
418 418
419 out-ports { 419 out-ports {
420 port { 420 port {
421 etm0_o 421 etm0_out: endpoint {
422 422 remote-endpoint =
423 423 <&funnel_little_in_port0>;
424 }; 424 };
425 }; 425 };
426 }; 426 };
427 }; 427 };
428 428
429 etm@13140000 { 429 etm@13140000 {
430 compatible = "arm,core 430 compatible = "arm,coresight-etm4x", "arm,primecell";
431 reg = <0 0x13140000 0 431 reg = <0 0x13140000 0 0x1000>;
432 cpu = <&CPU1>; 432 cpu = <&CPU1>;
433 clocks = <&ext_26m>; 433 clocks = <&ext_26m>;
434 clock-names = "apb_pcl 434 clock-names = "apb_pclk";
435 435
436 out-ports { 436 out-ports {
437 port { 437 port {
438 etm1_o 438 etm1_out: endpoint {
439 439 remote-endpoint =
440 440 <&funnel_little_in_port1>;
441 }; 441 };
442 }; 442 };
443 }; 443 };
444 }; 444 };
445 445
446 etm@13240000 { 446 etm@13240000 {
447 compatible = "arm,core 447 compatible = "arm,coresight-etm4x", "arm,primecell";
448 reg = <0 0x13240000 0 448 reg = <0 0x13240000 0 0x1000>;
449 cpu = <&CPU2>; 449 cpu = <&CPU2>;
450 clocks = <&ext_26m>; 450 clocks = <&ext_26m>;
451 clock-names = "apb_pcl 451 clock-names = "apb_pclk";
452 452
453 out-ports { 453 out-ports {
454 port { 454 port {
455 etm2_o 455 etm2_out: endpoint {
456 456 remote-endpoint =
457 457 <&funnel_little_in_port2>;
458 }; 458 };
459 }; 459 };
460 }; 460 };
461 }; 461 };
462 462
463 etm@13340000 { 463 etm@13340000 {
464 compatible = "arm,core 464 compatible = "arm,coresight-etm4x", "arm,primecell";
465 reg = <0 0x13340000 0 465 reg = <0 0x13340000 0 0x1000>;
466 cpu = <&CPU3>; 466 cpu = <&CPU3>;
467 clocks = <&ext_26m>; 467 clocks = <&ext_26m>;
468 clock-names = "apb_pcl 468 clock-names = "apb_pclk";
469 469
470 out-ports { 470 out-ports {
471 port { 471 port {
472 etm3_o 472 etm3_out: endpoint {
473 473 remote-endpoint =
474 474 <&funnel_little_in_port3>;
475 }; 475 };
476 }; 476 };
477 }; 477 };
478 }; 478 };
479 479
480 etm@13440000 { 480 etm@13440000 {
481 compatible = "arm,core 481 compatible = "arm,coresight-etm4x", "arm,primecell";
482 reg = <0 0x13440000 0 482 reg = <0 0x13440000 0 0x1000>;
483 cpu = <&CPU4>; 483 cpu = <&CPU4>;
484 clocks = <&ext_26m>; 484 clocks = <&ext_26m>;
485 clock-names = "apb_pcl 485 clock-names = "apb_pclk";
486 486
487 out-ports { 487 out-ports {
488 port { 488 port {
489 etm4_o 489 etm4_out: endpoint {
490 490 remote-endpoint =
491 491 <&funnel_big_in_port0>;
492 }; 492 };
493 }; 493 };
494 }; 494 };
495 }; 495 };
496 496
497 etm@13540000 { 497 etm@13540000 {
498 compatible = "arm,core 498 compatible = "arm,coresight-etm4x", "arm,primecell";
499 reg = <0 0x13540000 0 499 reg = <0 0x13540000 0 0x1000>;
500 cpu = <&CPU5>; 500 cpu = <&CPU5>;
501 clocks = <&ext_26m>; 501 clocks = <&ext_26m>;
502 clock-names = "apb_pcl 502 clock-names = "apb_pclk";
503 503
504 out-ports { 504 out-ports {
505 port { 505 port {
506 etm5_o 506 etm5_out: endpoint {
507 507 remote-endpoint =
508 508 <&funnel_big_in_port1>;
509 }; 509 };
510 }; 510 };
511 }; 511 };
512 }; 512 };
513 513
514 etm@13640000 { 514 etm@13640000 {
515 compatible = "arm,core 515 compatible = "arm,coresight-etm4x", "arm,primecell";
516 reg = <0 0x13640000 0 516 reg = <0 0x13640000 0 0x1000>;
517 cpu = <&CPU6>; 517 cpu = <&CPU6>;
518 clocks = <&ext_26m>; 518 clocks = <&ext_26m>;
519 clock-names = "apb_pcl 519 clock-names = "apb_pclk";
520 520
521 out-ports { 521 out-ports {
522 port { 522 port {
523 etm6_o 523 etm6_out: endpoint {
524 524 remote-endpoint =
525 525 <&funnel_big_in_port2>;
526 }; 526 };
527 }; 527 };
528 }; 528 };
529 }; 529 };
530 530
531 etm@13740000 { 531 etm@13740000 {
532 compatible = "arm,core 532 compatible = "arm,coresight-etm4x", "arm,primecell";
533 reg = <0 0x13740000 0 533 reg = <0 0x13740000 0 0x1000>;
534 cpu = <&CPU7>; 534 cpu = <&CPU7>;
535 clocks = <&ext_26m>; 535 clocks = <&ext_26m>;
536 clock-names = "apb_pcl 536 clock-names = "apb_pclk";
537 537
538 out-ports { 538 out-ports {
539 port { 539 port {
540 etm7_o 540 etm7_out: endpoint {
541 541 remote-endpoint =
542 542 <&funnel_big_in_port3>;
543 }; 543 };
544 }; 544 };
545 }; 545 };
546 }; 546 };
547 547
548 ap-ahb { 548 ap-ahb {
549 compatible = "simple-b 549 compatible = "simple-bus";
550 #address-cells = <2>; 550 #address-cells = <2>;
551 #size-cells = <2>; 551 #size-cells = <2>;
552 ranges; 552 ranges;
553 553
554 sdio0: mmc@20300000 { !! 554 sdio0: sdio@20300000 {
555 compatible = " 555 compatible = "sprd,sdhci-r11";
556 reg = <0 0x203 556 reg = <0 0x20300000 0 0x1000>;
557 interrupts = < 557 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
558 558
>> 559 clock-names = "sdio", "enable";
559 clocks = <&aon 560 clocks = <&aon_clk CLK_SDIO0_2X>,
560 <&apa 561 <&apahb_gate CLK_SDIO0_EB>;
561 clock-names = <<
562 assigned-clock 562 assigned-clocks = <&aon_clk CLK_SDIO0_2X>;
563 assigned-clock 563 assigned-clock-parents = <&rpll CLK_RPLL_390M>;
564 564
565 bus-width = <4 565 bus-width = <4>;
566 no-sdio; 566 no-sdio;
567 no-mmc; 567 no-mmc;
568 }; 568 };
569 569
570 sdio3: mmc@20600000 { !! 570 sdio3: sdio@20600000 {
571 compatible = " 571 compatible = "sprd,sdhci-r11";
572 reg = <0 0x206 572 reg = <0 0x20600000 0 0x1000>;
573 interrupts = < 573 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
574 574
>> 575 clock-names = "sdio", "enable";
575 clocks = <&aon 576 clocks = <&aon_clk CLK_EMMC_2X>,
576 <&apa 577 <&apahb_gate CLK_EMMC_EB>;
577 clock-names = <<
578 assigned-clock 578 assigned-clocks = <&aon_clk CLK_EMMC_2X>;
579 assigned-clock 579 assigned-clock-parents = <&rpll CLK_RPLL_390M>;
580 580
581 bus-width = <8 581 bus-width = <8>;
582 non-removable; 582 non-removable;
583 no-sdio; 583 no-sdio;
584 no-sd; 584 no-sd;
585 cap-mmc-hw-res 585 cap-mmc-hw-reset;
586 }; 586 };
587 }; 587 };
588 }; 588 };
589 }; 589 };
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