1 // SPDX-License-Identifier: (GPL-2.0-or-later 1 // SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
2 /* 2 /*
3 * Copyright (C) STMicroelectronics 2023 - All 3 * Copyright (C) STMicroelectronics 2023 - All Rights Reserved
4 * Author: Alexandre Torgue <alexandre.torgue@f 4 * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
5 */ 5 */
6 #include "stm32mp251.dtsi" 6 #include "stm32mp251.dtsi"
7 7
8 / { 8 / {
9 cpus { 9 cpus {
10 cpu1: cpu@1 { 10 cpu1: cpu@1 {
11 compatible = "arm,cort 11 compatible = "arm,cortex-a35";
12 device_type = "cpu"; 12 device_type = "cpu";
13 reg = <1>; 13 reg = <1>;
14 enable-method = "psci" 14 enable-method = "psci";
15 power-domains = <&CPU_ <<
16 power-domain-names = " <<
17 }; 15 };
18 }; 16 };
19 17
20 arm-pmu { 18 arm-pmu {
21 interrupts = <GIC_SPI 368 IRQ_ 19 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>,
22 <GIC_SPI 369 IRQ_ 20 <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>;
23 interrupt-affinity = <&cpu0>, 21 interrupt-affinity = <&cpu0>, <&cpu1>;
24 }; <<
25 <<
26 psci { <<
27 CPU_PD1: power-domain-cpu1 { <<
28 #power-domain-cells = <<
29 power-domains = <&CLUS <<
30 }; <<
31 }; <<
32 <<
33 timer { <<
34 interrupts = <GIC_PPI 13 (GIC_ <<
35 <GIC_PPI 14 (GIC_ <<
36 <GIC_PPI 11 (GIC_ <<
37 <GIC_PPI 10 (GIC_ <<
38 }; <<
39 }; <<
40 <<
41 &optee { <<
42 interrupts = <GIC_PPI 15 (GIC_CPU_MASK <<
43 }; <<
44 <<
45 &rifsc { <<
46 ethernet2: ethernet@482d0000 { <<
47 compatible = "st,stm32mp25-dwm <<
48 reg = <0x482d0000 0x4000>; <<
49 reg-names = "stmmaceth"; <<
50 interrupts-extended = <&intc G <<
51 interrupt-names = "macirq"; <<
52 clock-names = "stmmaceth", <<
53 "mac-clk-tx", <<
54 "mac-clk-rx", <<
55 "ptp_ref", <<
56 "ethstp", <<
57 "eth-ck"; <<
58 clocks = <&rcc CK_ETH2_MAC>, <<
59 <&rcc CK_ETH2_TX>, <<
60 <&rcc CK_ETH2_RX>, <<
61 <&rcc CK_KER_ETH2PTP> <<
62 <&rcc CK_ETH2_STP>, <<
63 <&rcc CK_KER_ETH2>; <<
64 snps,axi-config = <&stmmac_axi <<
65 snps,mixed-burst; <<
66 snps,mtl-rx-config = <&mtl_rx_ <<
67 snps,mtl-tx-config = <&mtl_tx_ <<
68 snps,pbl = <2>; <<
69 snps,tso; <<
70 st,syscon = <&syscfg 0x3400>; <<
71 access-controllers = <&rifsc 6 <<
72 status = "disabled"; <<
73 <<
74 mtl_rx_setup_2: rx-queues-conf <<
75 snps,rx-queues-to-use <<
76 queue0 {}; <<
77 queue1 {}; <<
78 }; <<
79 <<
80 mtl_tx_setup_2: tx-queues-conf <<
81 snps,tx-queues-to-use <<
82 queue0 {}; <<
83 queue1 {}; <<
84 queue2 {}; <<
85 queue3 {}; <<
86 }; <<
87 <<
88 stmmac_axi_config_2: stmmac-ax <<
89 snps,blen = <0 0 0 0 1 <<
90 snps,rd_osr_lmt = <0x7 <<
91 snps,wr_osr_lmt = <0x7 <<
92 }; <<
93 }; 22 };
94 }; 23 };
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