1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) 1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /* 2 /*
3 * Copyright (C) 2015 Marvell Technology Group 3 * Copyright (C) 2015 Marvell Technology Group Ltd.
4 * 4 *
5 * Author: Jisheng Zhang <jszhang@marvell.com> 5 * Author: Jisheng Zhang <jszhang@marvell.com>
6 */ 6 */
7 7
8 #include <dt-bindings/interrupt-controller/arm 8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 9
10 / { 10 / {
11 compatible = "marvell,berlin4ct", "mar 11 compatible = "marvell,berlin4ct", "marvell,berlin";
12 interrupt-parent = <&gic>; 12 interrupt-parent = <&gic>;
13 #address-cells = <2>; 13 #address-cells = <2>;
14 #size-cells = <2>; 14 #size-cells = <2>;
15 15
16 aliases { 16 aliases {
17 serial0 = &uart0; 17 serial0 = &uart0;
18 }; 18 };
19 19
20 psci { 20 psci {
21 compatible = "arm,psci-1.0", " 21 compatible = "arm,psci-1.0", "arm,psci-0.2";
22 method = "smc"; 22 method = "smc";
23 }; 23 };
24 24
25 cpus { 25 cpus {
26 #address-cells = <1>; 26 #address-cells = <1>;
27 #size-cells = <0>; 27 #size-cells = <0>;
28 28
29 cpu0: cpu@0 { 29 cpu0: cpu@0 {
30 compatible = "arm,cort 30 compatible = "arm,cortex-a53";
31 device_type = "cpu"; 31 device_type = "cpu";
32 reg = <0x0>; 32 reg = <0x0>;
33 enable-method = "psci" 33 enable-method = "psci";
34 next-level-cache = <&l 34 next-level-cache = <&l2>;
35 cpu-idle-states = <&CP 35 cpu-idle-states = <&CPU_SLEEP_0>;
36 }; 36 };
37 37
38 cpu1: cpu@1 { 38 cpu1: cpu@1 {
39 compatible = "arm,cort 39 compatible = "arm,cortex-a53";
40 device_type = "cpu"; 40 device_type = "cpu";
41 reg = <0x1>; 41 reg = <0x1>;
42 enable-method = "psci" 42 enable-method = "psci";
43 next-level-cache = <&l 43 next-level-cache = <&l2>;
44 cpu-idle-states = <&CP 44 cpu-idle-states = <&CPU_SLEEP_0>;
45 }; 45 };
46 46
47 cpu2: cpu@2 { 47 cpu2: cpu@2 {
48 compatible = "arm,cort 48 compatible = "arm,cortex-a53";
49 device_type = "cpu"; 49 device_type = "cpu";
50 reg = <0x2>; 50 reg = <0x2>;
51 enable-method = "psci" 51 enable-method = "psci";
52 next-level-cache = <&l 52 next-level-cache = <&l2>;
53 cpu-idle-states = <&CP 53 cpu-idle-states = <&CPU_SLEEP_0>;
54 }; 54 };
55 55
56 cpu3: cpu@3 { 56 cpu3: cpu@3 {
57 compatible = "arm,cort 57 compatible = "arm,cortex-a53";
58 device_type = "cpu"; 58 device_type = "cpu";
59 reg = <0x3>; 59 reg = <0x3>;
60 enable-method = "psci" 60 enable-method = "psci";
61 next-level-cache = <&l 61 next-level-cache = <&l2>;
62 cpu-idle-states = <&CP 62 cpu-idle-states = <&CPU_SLEEP_0>;
63 }; 63 };
64 64
65 l2: cache { 65 l2: cache {
66 compatible = "cache"; 66 compatible = "cache";
67 cache-level = <2>; <<
68 cache-unified; <<
69 }; 67 };
70 68
71 idle-states { 69 idle-states {
72 entry-method = "psci"; 70 entry-method = "psci";
73 CPU_SLEEP_0: cpu-sleep 71 CPU_SLEEP_0: cpu-sleep-0 {
74 compatible = " 72 compatible = "arm,idle-state";
75 local-timer-st 73 local-timer-stop;
76 arm,psci-suspe 74 arm,psci-suspend-param = <0x0010000>;
77 entry-latency- 75 entry-latency-us = <75>;
78 exit-latency-u 76 exit-latency-us = <155>;
79 min-residency- 77 min-residency-us = <1000>;
80 }; 78 };
81 }; 79 };
82 }; 80 };
83 81
84 osc: osc { 82 osc: osc {
85 compatible = "fixed-clock"; 83 compatible = "fixed-clock";
86 #clock-cells = <0>; 84 #clock-cells = <0>;
87 clock-frequency = <25000000>; 85 clock-frequency = <25000000>;
88 }; 86 };
89 87
90 pmu { 88 pmu {
91 compatible = "arm,cortex-a53-p !! 89 compatible = "arm,cortex-a53-pmu", "arm,armv8-pmuv3";
92 interrupts = <GIC_SPI 23 IRQ_T 90 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
93 <GIC_SPI 24 IRQ_T 91 <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
94 <GIC_SPI 25 IRQ_T 92 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
95 <GIC_SPI 26 IRQ_T 93 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
96 interrupt-affinity = <&cpu0>, 94 interrupt-affinity = <&cpu0>,
97 <&cpu1>, 95 <&cpu1>,
98 <&cpu2>, 96 <&cpu2>,
99 <&cpu3>; 97 <&cpu3>;
100 }; 98 };
101 99
102 timer { 100 timer {
103 compatible = "arm,armv8-timer" 101 compatible = "arm,armv8-timer";
104 interrupts = <GIC_PPI 13 (GIC_ 102 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
105 <GIC_PPI 14 (GIC_ 103 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
106 <GIC_PPI 11 (GIC_ 104 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
107 <GIC_PPI 10 (GIC_ 105 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
108 }; 106 };
109 107
110 soc@f7000000 { 108 soc@f7000000 {
111 compatible = "simple-bus"; 109 compatible = "simple-bus";
112 #address-cells = <1>; 110 #address-cells = <1>;
113 #size-cells = <1>; 111 #size-cells = <1>;
114 ranges = <0 0 0xf7000000 0x100 112 ranges = <0 0 0xf7000000 0x1000000>;
115 113
116 gic: interrupt-controller@9010 114 gic: interrupt-controller@901000 {
117 compatible = "arm,gic- 115 compatible = "arm,gic-400";
118 #interrupt-cells = <3> 116 #interrupt-cells = <3>;
119 interrupt-controller; 117 interrupt-controller;
120 reg = <0x901000 0x1000 118 reg = <0x901000 0x1000>,
121 <0x902000 0x2000 119 <0x902000 0x2000>,
122 <0x904000 0x2000 120 <0x904000 0x2000>,
123 <0x906000 0x2000 121 <0x906000 0x2000>;
124 interrupts = <GIC_PPI 122 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
125 }; 123 };
126 124
127 apb@e80000 { 125 apb@e80000 {
128 compatible = "simple-b 126 compatible = "simple-bus";
129 #address-cells = <1>; 127 #address-cells = <1>;
130 #size-cells = <1>; 128 #size-cells = <1>;
131 129
132 ranges = <0 0xe80000 0 130 ranges = <0 0xe80000 0x10000>;
133 interrupt-parent = <&a 131 interrupt-parent = <&aic>;
134 132
135 gpio0: gpio@400 { 133 gpio0: gpio@400 {
136 compatible = " 134 compatible = "snps,dw-apb-gpio";
137 reg = <0x0400 135 reg = <0x0400 0x400>;
138 #address-cells 136 #address-cells = <1>;
139 #size-cells = 137 #size-cells = <0>;
140 138
141 porta: gpio-po 139 porta: gpio-port@0 {
142 compat 140 compatible = "snps,dw-apb-gpio-port";
143 gpio-c 141 gpio-controller;
144 #gpio- 142 #gpio-cells = <2>;
145 ngpios !! 143 snps,nr-gpios = <32>;
146 reg = 144 reg = <0>;
147 interr 145 interrupt-controller;
148 #inter 146 #interrupt-cells = <2>;
149 interr 147 interrupts = <0>;
150 }; 148 };
151 }; 149 };
152 150
153 gpio1: gpio@800 { 151 gpio1: gpio@800 {
154 compatible = " 152 compatible = "snps,dw-apb-gpio";
155 reg = <0x0800 153 reg = <0x0800 0x400>;
156 #address-cells 154 #address-cells = <1>;
157 #size-cells = 155 #size-cells = <0>;
158 156
159 portb: gpio-po 157 portb: gpio-port@1 {
160 compat 158 compatible = "snps,dw-apb-gpio-port";
161 gpio-c 159 gpio-controller;
162 #gpio- 160 #gpio-cells = <2>;
163 ngpios !! 161 snps,nr-gpios = <32>;
164 reg = 162 reg = <0>;
165 interr 163 interrupt-controller;
166 #inter 164 #interrupt-cells = <2>;
167 interr 165 interrupts = <1>;
168 }; 166 };
169 }; 167 };
170 168
171 gpio2: gpio@c00 { 169 gpio2: gpio@c00 {
172 compatible = " 170 compatible = "snps,dw-apb-gpio";
173 reg = <0x0c00 171 reg = <0x0c00 0x400>;
174 #address-cells 172 #address-cells = <1>;
175 #size-cells = 173 #size-cells = <0>;
176 174
177 portc: gpio-po 175 portc: gpio-port@2 {
178 compat 176 compatible = "snps,dw-apb-gpio-port";
179 gpio-c 177 gpio-controller;
180 #gpio- 178 #gpio-cells = <2>;
181 ngpios !! 179 snps,nr-gpios = <32>;
182 reg = 180 reg = <0>;
183 interr 181 interrupt-controller;
184 #inter 182 #interrupt-cells = <2>;
185 interr 183 interrupts = <2>;
186 }; 184 };
187 }; 185 };
188 186
189 gpio3: gpio@1000 { 187 gpio3: gpio@1000 {
190 compatible = " 188 compatible = "snps,dw-apb-gpio";
191 reg = <0x1000 189 reg = <0x1000 0x400>;
192 #address-cells 190 #address-cells = <1>;
193 #size-cells = 191 #size-cells = <0>;
194 192
195 portd: gpio-po 193 portd: gpio-port@3 {
196 compat 194 compatible = "snps,dw-apb-gpio-port";
197 gpio-c 195 gpio-controller;
198 #gpio- 196 #gpio-cells = <2>;
199 ngpios !! 197 snps,nr-gpios = <32>;
200 reg = 198 reg = <0>;
201 interr 199 interrupt-controller;
202 #inter 200 #interrupt-cells = <2>;
203 interr 201 interrupts = <3>;
204 }; 202 };
205 }; 203 };
206 204
207 aic: interrupt-control 205 aic: interrupt-controller@3800 {
208 compatible = " 206 compatible = "snps,dw-apb-ictl";
209 reg = <0x3800 207 reg = <0x3800 0x30>;
210 interrupt-cont 208 interrupt-controller;
211 #interrupt-cel 209 #interrupt-cells = <1>;
212 interrupt-pare 210 interrupt-parent = <&gic>;
213 interrupts = < 211 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
214 }; 212 };
215 }; 213 };
216 214
217 soc_pinctrl: pin-controller@ea 215 soc_pinctrl: pin-controller@ea8000 {
218 compatible = "marvell, 216 compatible = "marvell,berlin4ct-soc-pinctrl";
219 reg = <0xea8000 0x14>; 217 reg = <0xea8000 0x14>;
220 }; 218 };
221 219
222 avio_pinctrl: pin-controller@e 220 avio_pinctrl: pin-controller@ea8400 {
223 compatible = "marvell, 221 compatible = "marvell,berlin4ct-avio-pinctrl";
224 reg = <0xea8400 0x8>; 222 reg = <0xea8400 0x8>;
225 }; 223 };
226 224
227 apb@fc0000 { 225 apb@fc0000 {
228 compatible = "simple-b 226 compatible = "simple-bus";
229 #address-cells = <1>; 227 #address-cells = <1>;
230 #size-cells = <1>; 228 #size-cells = <1>;
231 ranges = <0 0xfc0000 0 229 ranges = <0 0xfc0000 0x10000>;
232 interrupt-parent = <&s 230 interrupt-parent = <&sic>;
233 231
234 sic: interrupt-control 232 sic: interrupt-controller@1000 {
235 compatible = " 233 compatible = "snps,dw-apb-ictl";
236 reg = <0x1000 234 reg = <0x1000 0x30>;
237 interrupt-cont 235 interrupt-controller;
238 #interrupt-cel 236 #interrupt-cells = <1>;
239 interrupt-pare 237 interrupt-parent = <&gic>;
240 interrupts = < 238 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
241 }; 239 };
242 240
243 wdt0: watchdog@3000 { 241 wdt0: watchdog@3000 {
244 compatible = " 242 compatible = "snps,dw-wdt";
245 reg = <0x3000 243 reg = <0x3000 0x100>;
246 clocks = <&osc 244 clocks = <&osc>;
247 interrupts = < 245 interrupts = <0>;
248 }; 246 };
249 247
250 wdt1: watchdog@4000 { 248 wdt1: watchdog@4000 {
251 compatible = " 249 compatible = "snps,dw-wdt";
252 reg = <0x4000 250 reg = <0x4000 0x100>;
253 clocks = <&osc 251 clocks = <&osc>;
254 interrupts = < 252 interrupts = <1>;
255 }; 253 };
256 254
257 wdt2: watchdog@5000 { 255 wdt2: watchdog@5000 {
258 compatible = " 256 compatible = "snps,dw-wdt";
259 reg = <0x5000 257 reg = <0x5000 0x100>;
260 clocks = <&osc 258 clocks = <&osc>;
261 interrupts = < 259 interrupts = <2>;
262 }; 260 };
263 261
264 sm_gpio0: gpio@8000 { 262 sm_gpio0: gpio@8000 {
265 compatible = " 263 compatible = "snps,dw-apb-gpio";
266 reg = <0x8000 264 reg = <0x8000 0x400>;
267 #address-cells 265 #address-cells = <1>;
268 #size-cells = 266 #size-cells = <0>;
269 267
270 porte: gpio-po 268 porte: gpio-port@4 {
271 compat 269 compatible = "snps,dw-apb-gpio-port";
272 gpio-c 270 gpio-controller;
273 #gpio- 271 #gpio-cells = <2>;
274 ngpios !! 272 snps,nr-gpios = <32>;
275 reg = 273 reg = <0>;
276 }; 274 };
277 }; 275 };
278 276
279 sm_gpio1: gpio@9000 { 277 sm_gpio1: gpio@9000 {
280 compatible = " 278 compatible = "snps,dw-apb-gpio";
281 reg = <0x9000 279 reg = <0x9000 0x400>;
282 #address-cells 280 #address-cells = <1>;
283 #size-cells = 281 #size-cells = <0>;
284 282
285 portf: gpio-po 283 portf: gpio-port@5 {
286 compat 284 compatible = "snps,dw-apb-gpio-port";
287 gpio-c 285 gpio-controller;
288 #gpio- 286 #gpio-cells = <2>;
289 ngpios !! 287 snps,nr-gpios = <32>;
290 reg = 288 reg = <0>;
291 }; 289 };
292 }; 290 };
293 291
294 uart0: serial@d000 { !! 292 uart0: uart@d000 {
295 compatible = " 293 compatible = "snps,dw-apb-uart";
296 reg = <0xd000 294 reg = <0xd000 0x100>;
297 interrupts = < 295 interrupts = <8>;
298 clocks = <&osc 296 clocks = <&osc>;
299 reg-shift = <2 297 reg-shift = <2>;
300 status = "disa 298 status = "disabled";
301 pinctrl-0 = <& 299 pinctrl-0 = <&uart0_pmux>;
302 pinctrl-names 300 pinctrl-names = "default";
303 }; 301 };
304 }; 302 };
305 303
306 system_pinctrl: pin-controller 304 system_pinctrl: pin-controller@fe2200 {
307 compatible = "marvell, 305 compatible = "marvell,berlin4ct-system-pinctrl";
308 reg = <0xfe2200 0xc>; 306 reg = <0xfe2200 0xc>;
309 307
310 uart0_pmux: uart0-pmux 308 uart0_pmux: uart0-pmux {
311 groups = "SM_U 309 groups = "SM_URT0_TXD", "SM_URT0_RXD";
312 function = "ua 310 function = "uart0";
313 }; 311 };
314 }; 312 };
315 }; 313 };
316 }; 314 };
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