1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) 1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /* 2 /*
3 * Copyright (C) 2015 Marvell Technology Group 3 * Copyright (C) 2015 Marvell Technology Group Ltd.
4 * 4 *
5 * Author: Jisheng Zhang <jszhang@marvell.com> 5 * Author: Jisheng Zhang <jszhang@marvell.com>
6 */ 6 */
7 7
8 #include <dt-bindings/interrupt-controller/arm 8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 9
10 / { 10 / {
11 compatible = "marvell,berlin4ct", "mar 11 compatible = "marvell,berlin4ct", "marvell,berlin";
12 interrupt-parent = <&gic>; 12 interrupt-parent = <&gic>;
13 #address-cells = <2>; 13 #address-cells = <2>;
14 #size-cells = <2>; 14 #size-cells = <2>;
15 15
16 aliases { 16 aliases {
17 serial0 = &uart0; 17 serial0 = &uart0;
18 }; 18 };
19 19
20 psci { 20 psci {
21 compatible = "arm,psci-1.0", " 21 compatible = "arm,psci-1.0", "arm,psci-0.2";
22 method = "smc"; 22 method = "smc";
23 }; 23 };
24 24
25 cpus { 25 cpus {
26 #address-cells = <1>; 26 #address-cells = <1>;
27 #size-cells = <0>; 27 #size-cells = <0>;
28 28
29 cpu0: cpu@0 { 29 cpu0: cpu@0 {
30 compatible = "arm,cort 30 compatible = "arm,cortex-a53";
31 device_type = "cpu"; 31 device_type = "cpu";
32 reg = <0x0>; 32 reg = <0x0>;
33 enable-method = "psci" 33 enable-method = "psci";
34 next-level-cache = <&l 34 next-level-cache = <&l2>;
35 cpu-idle-states = <&CP 35 cpu-idle-states = <&CPU_SLEEP_0>;
36 }; 36 };
37 37
38 cpu1: cpu@1 { 38 cpu1: cpu@1 {
39 compatible = "arm,cort 39 compatible = "arm,cortex-a53";
40 device_type = "cpu"; 40 device_type = "cpu";
41 reg = <0x1>; 41 reg = <0x1>;
42 enable-method = "psci" 42 enable-method = "psci";
43 next-level-cache = <&l 43 next-level-cache = <&l2>;
44 cpu-idle-states = <&CP 44 cpu-idle-states = <&CPU_SLEEP_0>;
45 }; 45 };
46 46
47 cpu2: cpu@2 { 47 cpu2: cpu@2 {
48 compatible = "arm,cort 48 compatible = "arm,cortex-a53";
49 device_type = "cpu"; 49 device_type = "cpu";
50 reg = <0x2>; 50 reg = <0x2>;
51 enable-method = "psci" 51 enable-method = "psci";
52 next-level-cache = <&l 52 next-level-cache = <&l2>;
53 cpu-idle-states = <&CP 53 cpu-idle-states = <&CPU_SLEEP_0>;
54 }; 54 };
55 55
56 cpu3: cpu@3 { 56 cpu3: cpu@3 {
57 compatible = "arm,cort 57 compatible = "arm,cortex-a53";
58 device_type = "cpu"; 58 device_type = "cpu";
59 reg = <0x3>; 59 reg = <0x3>;
60 enable-method = "psci" 60 enable-method = "psci";
61 next-level-cache = <&l 61 next-level-cache = <&l2>;
62 cpu-idle-states = <&CP 62 cpu-idle-states = <&CPU_SLEEP_0>;
63 }; 63 };
64 64
65 l2: cache { 65 l2: cache {
66 compatible = "cache"; 66 compatible = "cache";
67 cache-level = <2>; 67 cache-level = <2>;
68 cache-unified; 68 cache-unified;
69 }; 69 };
70 70
71 idle-states { 71 idle-states {
72 entry-method = "psci"; 72 entry-method = "psci";
73 CPU_SLEEP_0: cpu-sleep 73 CPU_SLEEP_0: cpu-sleep-0 {
74 compatible = " 74 compatible = "arm,idle-state";
75 local-timer-st 75 local-timer-stop;
76 arm,psci-suspe 76 arm,psci-suspend-param = <0x0010000>;
77 entry-latency- 77 entry-latency-us = <75>;
78 exit-latency-u 78 exit-latency-us = <155>;
79 min-residency- 79 min-residency-us = <1000>;
80 }; 80 };
81 }; 81 };
82 }; 82 };
83 83
84 osc: osc { 84 osc: osc {
85 compatible = "fixed-clock"; 85 compatible = "fixed-clock";
86 #clock-cells = <0>; 86 #clock-cells = <0>;
87 clock-frequency = <25000000>; 87 clock-frequency = <25000000>;
88 }; 88 };
89 89
90 pmu { 90 pmu {
91 compatible = "arm,cortex-a53-p 91 compatible = "arm,cortex-a53-pmu";
92 interrupts = <GIC_SPI 23 IRQ_T 92 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
93 <GIC_SPI 24 IRQ_T 93 <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
94 <GIC_SPI 25 IRQ_T 94 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
95 <GIC_SPI 26 IRQ_T 95 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
96 interrupt-affinity = <&cpu0>, 96 interrupt-affinity = <&cpu0>,
97 <&cpu1>, 97 <&cpu1>,
98 <&cpu2>, 98 <&cpu2>,
99 <&cpu3>; 99 <&cpu3>;
100 }; 100 };
101 101
102 timer { 102 timer {
103 compatible = "arm,armv8-timer" 103 compatible = "arm,armv8-timer";
104 interrupts = <GIC_PPI 13 (GIC_ 104 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
105 <GIC_PPI 14 (GIC_ 105 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
106 <GIC_PPI 11 (GIC_ 106 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
107 <GIC_PPI 10 (GIC_ 107 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
108 }; 108 };
109 109
110 soc@f7000000 { 110 soc@f7000000 {
111 compatible = "simple-bus"; 111 compatible = "simple-bus";
112 #address-cells = <1>; 112 #address-cells = <1>;
113 #size-cells = <1>; 113 #size-cells = <1>;
114 ranges = <0 0 0xf7000000 0x100 114 ranges = <0 0 0xf7000000 0x1000000>;
115 115
116 gic: interrupt-controller@9010 116 gic: interrupt-controller@901000 {
117 compatible = "arm,gic- 117 compatible = "arm,gic-400";
118 #interrupt-cells = <3> 118 #interrupt-cells = <3>;
119 interrupt-controller; 119 interrupt-controller;
120 reg = <0x901000 0x1000 120 reg = <0x901000 0x1000>,
121 <0x902000 0x2000 121 <0x902000 0x2000>,
122 <0x904000 0x2000 122 <0x904000 0x2000>,
123 <0x906000 0x2000 123 <0x906000 0x2000>;
124 interrupts = <GIC_PPI 124 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
125 }; 125 };
126 126
127 apb@e80000 { 127 apb@e80000 {
128 compatible = "simple-b 128 compatible = "simple-bus";
129 #address-cells = <1>; 129 #address-cells = <1>;
130 #size-cells = <1>; 130 #size-cells = <1>;
131 131
132 ranges = <0 0xe80000 0 132 ranges = <0 0xe80000 0x10000>;
133 interrupt-parent = <&a 133 interrupt-parent = <&aic>;
134 134
135 gpio0: gpio@400 { 135 gpio0: gpio@400 {
136 compatible = " 136 compatible = "snps,dw-apb-gpio";
137 reg = <0x0400 137 reg = <0x0400 0x400>;
138 #address-cells 138 #address-cells = <1>;
139 #size-cells = 139 #size-cells = <0>;
140 140
141 porta: gpio-po 141 porta: gpio-port@0 {
142 compat 142 compatible = "snps,dw-apb-gpio-port";
143 gpio-c 143 gpio-controller;
144 #gpio- 144 #gpio-cells = <2>;
145 ngpios 145 ngpios = <32>;
146 reg = 146 reg = <0>;
147 interr 147 interrupt-controller;
148 #inter 148 #interrupt-cells = <2>;
149 interr 149 interrupts = <0>;
150 }; 150 };
151 }; 151 };
152 152
153 gpio1: gpio@800 { 153 gpio1: gpio@800 {
154 compatible = " 154 compatible = "snps,dw-apb-gpio";
155 reg = <0x0800 155 reg = <0x0800 0x400>;
156 #address-cells 156 #address-cells = <1>;
157 #size-cells = 157 #size-cells = <0>;
158 158
159 portb: gpio-po 159 portb: gpio-port@1 {
160 compat 160 compatible = "snps,dw-apb-gpio-port";
161 gpio-c 161 gpio-controller;
162 #gpio- 162 #gpio-cells = <2>;
163 ngpios 163 ngpios = <32>;
164 reg = 164 reg = <0>;
165 interr 165 interrupt-controller;
166 #inter 166 #interrupt-cells = <2>;
167 interr 167 interrupts = <1>;
168 }; 168 };
169 }; 169 };
170 170
171 gpio2: gpio@c00 { 171 gpio2: gpio@c00 {
172 compatible = " 172 compatible = "snps,dw-apb-gpio";
173 reg = <0x0c00 173 reg = <0x0c00 0x400>;
174 #address-cells 174 #address-cells = <1>;
175 #size-cells = 175 #size-cells = <0>;
176 176
177 portc: gpio-po 177 portc: gpio-port@2 {
178 compat 178 compatible = "snps,dw-apb-gpio-port";
179 gpio-c 179 gpio-controller;
180 #gpio- 180 #gpio-cells = <2>;
181 ngpios 181 ngpios = <32>;
182 reg = 182 reg = <0>;
183 interr 183 interrupt-controller;
184 #inter 184 #interrupt-cells = <2>;
185 interr 185 interrupts = <2>;
186 }; 186 };
187 }; 187 };
188 188
189 gpio3: gpio@1000 { 189 gpio3: gpio@1000 {
190 compatible = " 190 compatible = "snps,dw-apb-gpio";
191 reg = <0x1000 191 reg = <0x1000 0x400>;
192 #address-cells 192 #address-cells = <1>;
193 #size-cells = 193 #size-cells = <0>;
194 194
195 portd: gpio-po 195 portd: gpio-port@3 {
196 compat 196 compatible = "snps,dw-apb-gpio-port";
197 gpio-c 197 gpio-controller;
198 #gpio- 198 #gpio-cells = <2>;
199 ngpios 199 ngpios = <32>;
200 reg = 200 reg = <0>;
201 interr 201 interrupt-controller;
202 #inter 202 #interrupt-cells = <2>;
203 interr 203 interrupts = <3>;
204 }; 204 };
205 }; 205 };
206 206
207 aic: interrupt-control 207 aic: interrupt-controller@3800 {
208 compatible = " 208 compatible = "snps,dw-apb-ictl";
209 reg = <0x3800 209 reg = <0x3800 0x30>;
210 interrupt-cont 210 interrupt-controller;
211 #interrupt-cel 211 #interrupt-cells = <1>;
212 interrupt-pare 212 interrupt-parent = <&gic>;
213 interrupts = < 213 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
214 }; 214 };
215 }; 215 };
216 216
217 soc_pinctrl: pin-controller@ea 217 soc_pinctrl: pin-controller@ea8000 {
218 compatible = "marvell, 218 compatible = "marvell,berlin4ct-soc-pinctrl";
219 reg = <0xea8000 0x14>; 219 reg = <0xea8000 0x14>;
220 }; 220 };
221 221
222 avio_pinctrl: pin-controller@e 222 avio_pinctrl: pin-controller@ea8400 {
223 compatible = "marvell, 223 compatible = "marvell,berlin4ct-avio-pinctrl";
224 reg = <0xea8400 0x8>; 224 reg = <0xea8400 0x8>;
225 }; 225 };
226 226
227 apb@fc0000 { 227 apb@fc0000 {
228 compatible = "simple-b 228 compatible = "simple-bus";
229 #address-cells = <1>; 229 #address-cells = <1>;
230 #size-cells = <1>; 230 #size-cells = <1>;
231 ranges = <0 0xfc0000 0 231 ranges = <0 0xfc0000 0x10000>;
232 interrupt-parent = <&s 232 interrupt-parent = <&sic>;
233 233
234 sic: interrupt-control 234 sic: interrupt-controller@1000 {
235 compatible = " 235 compatible = "snps,dw-apb-ictl";
236 reg = <0x1000 236 reg = <0x1000 0x30>;
237 interrupt-cont 237 interrupt-controller;
238 #interrupt-cel 238 #interrupt-cells = <1>;
239 interrupt-pare 239 interrupt-parent = <&gic>;
240 interrupts = < 240 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
241 }; 241 };
242 242
243 wdt0: watchdog@3000 { 243 wdt0: watchdog@3000 {
244 compatible = " 244 compatible = "snps,dw-wdt";
245 reg = <0x3000 245 reg = <0x3000 0x100>;
246 clocks = <&osc 246 clocks = <&osc>;
247 interrupts = < 247 interrupts = <0>;
248 }; 248 };
249 249
250 wdt1: watchdog@4000 { 250 wdt1: watchdog@4000 {
251 compatible = " 251 compatible = "snps,dw-wdt";
252 reg = <0x4000 252 reg = <0x4000 0x100>;
253 clocks = <&osc 253 clocks = <&osc>;
254 interrupts = < 254 interrupts = <1>;
255 }; 255 };
256 256
257 wdt2: watchdog@5000 { 257 wdt2: watchdog@5000 {
258 compatible = " 258 compatible = "snps,dw-wdt";
259 reg = <0x5000 259 reg = <0x5000 0x100>;
260 clocks = <&osc 260 clocks = <&osc>;
261 interrupts = < 261 interrupts = <2>;
262 }; 262 };
263 263
264 sm_gpio0: gpio@8000 { 264 sm_gpio0: gpio@8000 {
265 compatible = " 265 compatible = "snps,dw-apb-gpio";
266 reg = <0x8000 266 reg = <0x8000 0x400>;
267 #address-cells 267 #address-cells = <1>;
268 #size-cells = 268 #size-cells = <0>;
269 269
270 porte: gpio-po 270 porte: gpio-port@4 {
271 compat 271 compatible = "snps,dw-apb-gpio-port";
272 gpio-c 272 gpio-controller;
273 #gpio- 273 #gpio-cells = <2>;
274 ngpios 274 ngpios = <32>;
275 reg = 275 reg = <0>;
276 }; 276 };
277 }; 277 };
278 278
279 sm_gpio1: gpio@9000 { 279 sm_gpio1: gpio@9000 {
280 compatible = " 280 compatible = "snps,dw-apb-gpio";
281 reg = <0x9000 281 reg = <0x9000 0x400>;
282 #address-cells 282 #address-cells = <1>;
283 #size-cells = 283 #size-cells = <0>;
284 284
285 portf: gpio-po 285 portf: gpio-port@5 {
286 compat 286 compatible = "snps,dw-apb-gpio-port";
287 gpio-c 287 gpio-controller;
288 #gpio- 288 #gpio-cells = <2>;
289 ngpios 289 ngpios = <32>;
290 reg = 290 reg = <0>;
291 }; 291 };
292 }; 292 };
293 293
294 uart0: serial@d000 { 294 uart0: serial@d000 {
295 compatible = " 295 compatible = "snps,dw-apb-uart";
296 reg = <0xd000 296 reg = <0xd000 0x100>;
297 interrupts = < 297 interrupts = <8>;
298 clocks = <&osc 298 clocks = <&osc>;
299 reg-shift = <2 299 reg-shift = <2>;
300 status = "disa 300 status = "disabled";
301 pinctrl-0 = <& 301 pinctrl-0 = <&uart0_pmux>;
302 pinctrl-names 302 pinctrl-names = "default";
303 }; 303 };
304 }; 304 };
305 305
306 system_pinctrl: pin-controller 306 system_pinctrl: pin-controller@fe2200 {
307 compatible = "marvell, 307 compatible = "marvell,berlin4ct-system-pinctrl";
308 reg = <0xfe2200 0xc>; 308 reg = <0xfe2200 0xc>;
309 309
310 uart0_pmux: uart0-pmux 310 uart0_pmux: uart0-pmux {
311 groups = "SM_U 311 groups = "SM_URT0_TXD", "SM_URT0_RXD";
312 function = "ua 312 function = "uart0";
313 }; 313 };
314 }; 314 };
315 }; 315 };
316 }; 316 };
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