1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /*
3 * Copyright (C) 2015 Marvell Technology Group
4 *
5 * Author: Jisheng Zhang <jszhang@marvell.com>
6 */
7
8 #include <dt-bindings/interrupt-controller/arm
9
10 / {
11 compatible = "marvell,berlin4ct", "mar
12 interrupt-parent = <&gic>;
13 #address-cells = <2>;
14 #size-cells = <2>;
15
16 aliases {
17 serial0 = &uart0;
18 };
19
20 psci {
21 compatible = "arm,psci-1.0", "
22 method = "smc";
23 };
24
25 cpus {
26 #address-cells = <1>;
27 #size-cells = <0>;
28
29 cpu0: cpu@0 {
30 compatible = "arm,cort
31 device_type = "cpu";
32 reg = <0x0>;
33 enable-method = "psci"
34 next-level-cache = <&l
35 cpu-idle-states = <&CP
36 };
37
38 cpu1: cpu@1 {
39 compatible = "arm,cort
40 device_type = "cpu";
41 reg = <0x1>;
42 enable-method = "psci"
43 next-level-cache = <&l
44 cpu-idle-states = <&CP
45 };
46
47 cpu2: cpu@2 {
48 compatible = "arm,cort
49 device_type = "cpu";
50 reg = <0x2>;
51 enable-method = "psci"
52 next-level-cache = <&l
53 cpu-idle-states = <&CP
54 };
55
56 cpu3: cpu@3 {
57 compatible = "arm,cort
58 device_type = "cpu";
59 reg = <0x3>;
60 enable-method = "psci"
61 next-level-cache = <&l
62 cpu-idle-states = <&CP
63 };
64
65 l2: cache {
66 compatible = "cache";
67 cache-level = <2>;
68 cache-unified;
69 };
70
71 idle-states {
72 entry-method = "psci";
73 CPU_SLEEP_0: cpu-sleep
74 compatible = "
75 local-timer-st
76 arm,psci-suspe
77 entry-latency-
78 exit-latency-u
79 min-residency-
80 };
81 };
82 };
83
84 osc: osc {
85 compatible = "fixed-clock";
86 #clock-cells = <0>;
87 clock-frequency = <25000000>;
88 };
89
90 pmu {
91 compatible = "arm,cortex-a53-p
92 interrupts = <GIC_SPI 23 IRQ_T
93 <GIC_SPI 24 IRQ_T
94 <GIC_SPI 25 IRQ_T
95 <GIC_SPI 26 IRQ_T
96 interrupt-affinity = <&cpu0>,
97 <&cpu1>,
98 <&cpu2>,
99 <&cpu3>;
100 };
101
102 timer {
103 compatible = "arm,armv8-timer"
104 interrupts = <GIC_PPI 13 (GIC_
105 <GIC_PPI 14 (GIC_
106 <GIC_PPI 11 (GIC_
107 <GIC_PPI 10 (GIC_
108 };
109
110 soc@f7000000 {
111 compatible = "simple-bus";
112 #address-cells = <1>;
113 #size-cells = <1>;
114 ranges = <0 0 0xf7000000 0x100
115
116 gic: interrupt-controller@9010
117 compatible = "arm,gic-
118 #interrupt-cells = <3>
119 interrupt-controller;
120 reg = <0x901000 0x1000
121 <0x902000 0x2000
122 <0x904000 0x2000
123 <0x906000 0x2000
124 interrupts = <GIC_PPI
125 };
126
127 apb@e80000 {
128 compatible = "simple-b
129 #address-cells = <1>;
130 #size-cells = <1>;
131
132 ranges = <0 0xe80000 0
133 interrupt-parent = <&a
134
135 gpio0: gpio@400 {
136 compatible = "
137 reg = <0x0400
138 #address-cells
139 #size-cells =
140
141 porta: gpio-po
142 compat
143 gpio-c
144 #gpio-
145 ngpios
146 reg =
147 interr
148 #inter
149 interr
150 };
151 };
152
153 gpio1: gpio@800 {
154 compatible = "
155 reg = <0x0800
156 #address-cells
157 #size-cells =
158
159 portb: gpio-po
160 compat
161 gpio-c
162 #gpio-
163 ngpios
164 reg =
165 interr
166 #inter
167 interr
168 };
169 };
170
171 gpio2: gpio@c00 {
172 compatible = "
173 reg = <0x0c00
174 #address-cells
175 #size-cells =
176
177 portc: gpio-po
178 compat
179 gpio-c
180 #gpio-
181 ngpios
182 reg =
183 interr
184 #inter
185 interr
186 };
187 };
188
189 gpio3: gpio@1000 {
190 compatible = "
191 reg = <0x1000
192 #address-cells
193 #size-cells =
194
195 portd: gpio-po
196 compat
197 gpio-c
198 #gpio-
199 ngpios
200 reg =
201 interr
202 #inter
203 interr
204 };
205 };
206
207 aic: interrupt-control
208 compatible = "
209 reg = <0x3800
210 interrupt-cont
211 #interrupt-cel
212 interrupt-pare
213 interrupts = <
214 };
215 };
216
217 soc_pinctrl: pin-controller@ea
218 compatible = "marvell,
219 reg = <0xea8000 0x14>;
220 };
221
222 avio_pinctrl: pin-controller@e
223 compatible = "marvell,
224 reg = <0xea8400 0x8>;
225 };
226
227 apb@fc0000 {
228 compatible = "simple-b
229 #address-cells = <1>;
230 #size-cells = <1>;
231 ranges = <0 0xfc0000 0
232 interrupt-parent = <&s
233
234 sic: interrupt-control
235 compatible = "
236 reg = <0x1000
237 interrupt-cont
238 #interrupt-cel
239 interrupt-pare
240 interrupts = <
241 };
242
243 wdt0: watchdog@3000 {
244 compatible = "
245 reg = <0x3000
246 clocks = <&osc
247 interrupts = <
248 };
249
250 wdt1: watchdog@4000 {
251 compatible = "
252 reg = <0x4000
253 clocks = <&osc
254 interrupts = <
255 };
256
257 wdt2: watchdog@5000 {
258 compatible = "
259 reg = <0x5000
260 clocks = <&osc
261 interrupts = <
262 };
263
264 sm_gpio0: gpio@8000 {
265 compatible = "
266 reg = <0x8000
267 #address-cells
268 #size-cells =
269
270 porte: gpio-po
271 compat
272 gpio-c
273 #gpio-
274 ngpios
275 reg =
276 };
277 };
278
279 sm_gpio1: gpio@9000 {
280 compatible = "
281 reg = <0x9000
282 #address-cells
283 #size-cells =
284
285 portf: gpio-po
286 compat
287 gpio-c
288 #gpio-
289 ngpios
290 reg =
291 };
292 };
293
294 uart0: serial@d000 {
295 compatible = "
296 reg = <0xd000
297 interrupts = <
298 clocks = <&osc
299 reg-shift = <2
300 status = "disa
301 pinctrl-0 = <&
302 pinctrl-names
303 };
304 };
305
306 system_pinctrl: pin-controller
307 compatible = "marvell,
308 reg = <0xfe2200 0xc>;
309
310 uart0_pmux: uart0-pmux
311 groups = "SM_U
312 function = "ua
313 };
314 };
315 };
316 };
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