1 // SPDX-License-Identifier: GPL-2.0-only OR MI !! 1 // SPDX-License-Identifier: GPL-2.0
2 /* 2 /*
3 * AM625 SK: https://www.ti.com/lit/zip/sprr44 3 * AM625 SK: https://www.ti.com/lit/zip/sprr448
4 * 4 *
5 * Copyright (C) 2021-2024 Texas Instruments I !! 5 * Copyright (C) 2021-2022 Texas Instruments Incorporated - https://www.ti.com/
6 */ 6 */
7 7
8 /dts-v1/; 8 /dts-v1/;
9 9
10 #include "k3-am62x-sk-common.dtsi" !! 10 #include <dt-bindings/leds/common.h>
>> 11 #include <dt-bindings/gpio/gpio.h>
>> 12 #include <dt-bindings/net/ti-dp83867.h>
>> 13 #include "k3-am625.dtsi"
11 14
12 / { 15 / {
13 compatible = "ti,am625-sk", "ti,am625" 16 compatible = "ti,am625-sk", "ti,am625";
14 model = "Texas Instruments AM625 SK"; 17 model = "Texas Instruments AM625 SK";
15 18
16 opp-table { !! 19 aliases {
17 /* Add 1.4GHz OPP for am625-sk !! 20 serial2 = &main_uart0;
18 opp-1400000000 { !! 21 mmc0 = &sdhci0;
19 opp-hz = /bits/ 64 <14 !! 22 mmc1 = &sdhci1;
20 opp-supported-hw = <0x !! 23 mmc2 = &sdhci2;
21 clock-latency-ns = <60 !! 24 spi0 = &ospi0;
22 }; !! 25 ethernet0 = &cpsw_port1;
>> 26 ethernet1 = &cpsw_port2;
>> 27 };
>> 28
>> 29 chosen {
>> 30 stdout-path = "serial2:115200n8";
>> 31 bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000";
23 }; 32 };
24 33
25 memory@80000000 { 34 memory@80000000 {
26 device_type = "memory"; 35 device_type = "memory";
27 /* 2G RAM */ 36 /* 2G RAM */
28 reg = <0x00000000 0x80000000 0 37 reg = <0x00000000 0x80000000 0x00000000 0x80000000>;
29 38
30 }; 39 };
31 40
>> 41 reserved-memory {
>> 42 #address-cells = <2>;
>> 43 #size-cells = <2>;
>> 44 ranges;
>> 45
>> 46 ramoops@9ca00000 {
>> 47 compatible = "ramoops";
>> 48 reg = <0x00 0x9ca00000 0x00 0x00100000>;
>> 49 record-size = <0x8000>;
>> 50 console-size = <0x8000>;
>> 51 ftrace-size = <0x00>;
>> 52 pmsg-size = <0x8000>;
>> 53 };
>> 54
>> 55 secure_tfa_ddr: tfa@9e780000 {
>> 56 reg = <0x00 0x9e780000 0x00 0x80000>;
>> 57 alignment = <0x1000>;
>> 58 no-map;
>> 59 };
>> 60
>> 61 secure_ddr: optee@9e800000 {
>> 62 reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */
>> 63 alignment = <0x1000>;
>> 64 no-map;
>> 65 };
>> 66
>> 67 wkup_r5fss0_core0_dma_memory_region: r5f-dma-memory@9db00000 {
>> 68 compatible = "shared-dma-pool";
>> 69 reg = <0x00 0x9db00000 0x00 0xc00000>;
>> 70 no-map;
>> 71 };
>> 72 };
>> 73
32 vmain_pd: regulator-0 { 74 vmain_pd: regulator-0 {
33 /* TPS65988 PD CONTROLLER OUTP 75 /* TPS65988 PD CONTROLLER OUTPUT */
34 bootph-all; <<
35 compatible = "regulator-fixed" 76 compatible = "regulator-fixed";
36 regulator-name = "vmain_pd"; 77 regulator-name = "vmain_pd";
37 regulator-min-microvolt = <500 78 regulator-min-microvolt = <5000000>;
38 regulator-max-microvolt = <500 79 regulator-max-microvolt = <5000000>;
39 regulator-always-on; 80 regulator-always-on;
40 regulator-boot-on; 81 regulator-boot-on;
41 }; 82 };
42 83
43 vcc_5v0: regulator-1 { 84 vcc_5v0: regulator-1 {
44 /* Output of LM34936 */ 85 /* Output of LM34936 */
45 bootph-all; <<
46 compatible = "regulator-fixed" 86 compatible = "regulator-fixed";
47 regulator-name = "vcc_5v0"; 87 regulator-name = "vcc_5v0";
48 regulator-min-microvolt = <500 88 regulator-min-microvolt = <5000000>;
49 regulator-max-microvolt = <500 89 regulator-max-microvolt = <5000000>;
50 vin-supply = <&vmain_pd>; 90 vin-supply = <&vmain_pd>;
51 regulator-always-on; 91 regulator-always-on;
52 regulator-boot-on; 92 regulator-boot-on;
53 }; 93 };
54 94
55 vcc_3v3_sys: regulator-2 { 95 vcc_3v3_sys: regulator-2 {
56 /* output of LM61460-Q1 */ 96 /* output of LM61460-Q1 */
57 bootph-all; <<
58 compatible = "regulator-fixed" 97 compatible = "regulator-fixed";
59 regulator-name = "vcc_3v3_sys" 98 regulator-name = "vcc_3v3_sys";
60 regulator-min-microvolt = <330 99 regulator-min-microvolt = <3300000>;
61 regulator-max-microvolt = <330 100 regulator-max-microvolt = <3300000>;
62 vin-supply = <&vmain_pd>; 101 vin-supply = <&vmain_pd>;
63 regulator-always-on; 102 regulator-always-on;
64 regulator-boot-on; 103 regulator-boot-on;
65 }; 104 };
66 105
67 vdd_mmc1: regulator-3 { 106 vdd_mmc1: regulator-3 {
68 /* TPS22918DBVR */ 107 /* TPS22918DBVR */
69 bootph-all; <<
70 compatible = "regulator-fixed" 108 compatible = "regulator-fixed";
71 regulator-name = "vdd_mmc1"; 109 regulator-name = "vdd_mmc1";
72 regulator-min-microvolt = <330 110 regulator-min-microvolt = <3300000>;
73 regulator-max-microvolt = <330 111 regulator-max-microvolt = <3300000>;
74 regulator-boot-on; 112 regulator-boot-on;
75 enable-active-high; 113 enable-active-high;
76 vin-supply = <&vcc_3v3_sys>; 114 vin-supply = <&vcc_3v3_sys>;
77 gpio = <&exp1 3 GPIO_ACTIVE_HI 115 gpio = <&exp1 3 GPIO_ACTIVE_HIGH>;
78 }; 116 };
79 117
80 vdd_sd_dv: regulator-4 { 118 vdd_sd_dv: regulator-4 {
81 /* Output of TLV71033 */ 119 /* Output of TLV71033 */
82 bootph-all; <<
83 compatible = "regulator-gpio"; 120 compatible = "regulator-gpio";
84 regulator-name = "tlv71033"; 121 regulator-name = "tlv71033";
85 pinctrl-names = "default"; 122 pinctrl-names = "default";
86 pinctrl-0 = <&vdd_sd_dv_pins_d 123 pinctrl-0 = <&vdd_sd_dv_pins_default>;
87 regulator-min-microvolt = <180 124 regulator-min-microvolt = <1800000>;
88 regulator-max-microvolt = <330 125 regulator-max-microvolt = <3300000>;
89 regulator-boot-on; 126 regulator-boot-on;
90 vin-supply = <&vcc_5v0>; 127 vin-supply = <&vcc_5v0>;
91 gpios = <&main_gpio0 31 GPIO_A 128 gpios = <&main_gpio0 31 GPIO_ACTIVE_HIGH>;
92 states = <1800000 0x0>, 129 states = <1800000 0x0>,
93 <3300000 0x1>; 130 <3300000 0x1>;
94 }; 131 };
95 132
96 vcc_1v8: regulator-5 { !! 133 leds {
97 /* output of TPS6282518DMQ */ !! 134 compatible = "gpio-leds";
98 compatible = "regulator-fixed" !! 135 pinctrl-names = "default";
99 regulator-name = "vcc_1v8"; !! 136 pinctrl-0 = <&usr_led_pins_default>;
100 regulator-min-microvolt = <180 !! 137
101 regulator-max-microvolt = <180 !! 138 led-0 {
102 vin-supply = <&vcc_3v3_sys>; !! 139 label = "am62-sk:green:heartbeat";
103 regulator-always-on; !! 140 gpios = <&main_gpio1 49 GPIO_ACTIVE_HIGH>;
104 regulator-boot-on; !! 141 linux,default-trigger = "heartbeat";
>> 142 function = LED_FUNCTION_HEARTBEAT;
>> 143 default-state = "off";
>> 144 };
105 }; 145 };
106 }; 146 };
107 147
108 &main_pmx0 { 148 &main_pmx0 {
109 main_rgmii2_pins_default: main-rgmii2- !! 149 main_uart0_pins_default: main-uart0-pins-default {
110 bootph-all; !! 150 pinctrl-single,pins = <
>> 151 AM62X_IOPAD(0x1c8, PIN_INPUT, 0) /* (D14) UART0_RXD */
>> 152 AM62X_IOPAD(0x1cc, PIN_OUTPUT, 0) /* (E14) UART0_TXD */
>> 153 >;
>> 154 };
>> 155
>> 156 main_i2c0_pins_default: main-i2c0-pins-default {
>> 157 pinctrl-single,pins = <
>> 158 AM62X_IOPAD(0x1e0, PIN_INPUT_PULLUP, 0) /* (B16) I2C0_SCL */
>> 159 AM62X_IOPAD(0x1e4, PIN_INPUT_PULLUP, 0) /* (A16) I2C0_SDA */
>> 160 >;
>> 161 };
>> 162
>> 163 main_i2c1_pins_default: main-i2c1-pins-default {
>> 164 pinctrl-single,pins = <
>> 165 AM62X_IOPAD(0x1e8, PIN_INPUT_PULLUP, 0) /* (B17) I2C1_SCL */
>> 166 AM62X_IOPAD(0x1ec, PIN_INPUT_PULLUP, 0) /* (A17) I2C1_SDA */
>> 167 >;
>> 168 };
>> 169
>> 170 main_i2c2_pins_default: main-i2c2-pins-default {
>> 171 pinctrl-single,pins = <
>> 172 AM62X_IOPAD(0x0b0, PIN_INPUT_PULLUP, 1) /* (K22) GPMC0_CSn2.I2C2_SCL */
>> 173 AM62X_IOPAD(0x0b4, PIN_INPUT_PULLUP, 1) /* (K24) GPMC0_CSn3.I2C2_SDA */
>> 174 >;
>> 175 };
>> 176
>> 177 main_mmc0_pins_default: main-mmc0-pins-default {
>> 178 pinctrl-single,pins = <
>> 179 AM62X_IOPAD(0x220, PIN_INPUT, 0) /* (Y3) MMC0_CMD */
>> 180 AM62X_IOPAD(0x218, PIN_INPUT, 0) /* (AB1) MMC0_CLK */
>> 181 AM62X_IOPAD(0x214, PIN_INPUT, 0) /* (AA2) MMC0_DAT0 */
>> 182 AM62X_IOPAD(0x210, PIN_INPUT, 0) /* (AA1) MMC0_DAT1 */
>> 183 AM62X_IOPAD(0x20c, PIN_INPUT, 0) /* (AA3) MMC0_DAT2 */
>> 184 AM62X_IOPAD(0x208, PIN_INPUT, 0) /* (Y4) MMC0_DAT3 */
>> 185 AM62X_IOPAD(0x204, PIN_INPUT, 0) /* (AB2) MMC0_DAT4 */
>> 186 AM62X_IOPAD(0x200, PIN_INPUT, 0) /* (AC1) MMC0_DAT5 */
>> 187 AM62X_IOPAD(0x1fc, PIN_INPUT, 0) /* (AD2) MMC0_DAT6 */
>> 188 AM62X_IOPAD(0x1f8, PIN_INPUT, 0) /* (AC2) MMC0_DAT7 */
>> 189 >;
>> 190 };
>> 191
>> 192 main_mmc1_pins_default: main-mmc1-pins-default {
>> 193 pinctrl-single,pins = <
>> 194 AM62X_IOPAD(0x23c, PIN_INPUT, 0) /* (A21) MMC1_CMD */
>> 195 AM62X_IOPAD(0x234, PIN_INPUT, 0) /* (B22) MMC1_CLK */
>> 196 AM62X_IOPAD(0x230, PIN_INPUT, 0) /* (A22) MMC1_DAT0 */
>> 197 AM62X_IOPAD(0x22c, PIN_INPUT, 0) /* (B21) MMC1_DAT1 */
>> 198 AM62X_IOPAD(0x228, PIN_INPUT, 0) /* (C21) MMC1_DAT2 */
>> 199 AM62X_IOPAD(0x224, PIN_INPUT, 0) /* (D22) MMC1_DAT3 */
>> 200 AM62X_IOPAD(0x240, PIN_INPUT, 0) /* (D17) MMC1_SDCD */
>> 201 >;
>> 202 };
>> 203
>> 204 usr_led_pins_default: usr-led-pins-default {
>> 205 pinctrl-single,pins = <
>> 206 AM62X_IOPAD(0x244, PIN_OUTPUT, 7) /* (C17) MMC1_SDWP.GPIO1_49 */
>> 207 >;
>> 208 };
>> 209
>> 210 main_mdio1_pins_default: main-mdio1-pins-default {
>> 211 pinctrl-single,pins = <
>> 212 AM62X_IOPAD(0x160, PIN_OUTPUT, 0) /* (AD24) MDIO0_MDC */
>> 213 AM62X_IOPAD(0x15c, PIN_INPUT, 0) /* (AB22) MDIO0_MDIO */
>> 214 >;
>> 215 };
>> 216
>> 217 main_rgmii1_pins_default: main-rgmii1-pins-default {
>> 218 pinctrl-single,pins = <
>> 219 AM62X_IOPAD(0x14c, PIN_INPUT, 0) /* (AB17) RGMII1_RD0 */
>> 220 AM62X_IOPAD(0x150, PIN_INPUT, 0) /* (AC17) RGMII1_RD1 */
>> 221 AM62X_IOPAD(0x154, PIN_INPUT, 0) /* (AB16) RGMII1_RD2 */
>> 222 AM62X_IOPAD(0x158, PIN_INPUT, 0) /* (AA15) RGMII1_RD3 */
>> 223 AM62X_IOPAD(0x148, PIN_INPUT, 0) /* (AD17) RGMII1_RXC */
>> 224 AM62X_IOPAD(0x144, PIN_INPUT, 0) /* (AE17) RGMII1_RX_CTL */
>> 225 AM62X_IOPAD(0x134, PIN_OUTPUT, 0) /* (AE20) RGMII1_TD0 */
>> 226 AM62X_IOPAD(0x138, PIN_OUTPUT, 0) /* (AD20) RGMII1_TD1 */
>> 227 AM62X_IOPAD(0x13c, PIN_OUTPUT, 0) /* (AE18) RGMII1_TD2 */
>> 228 AM62X_IOPAD(0x140, PIN_OUTPUT, 0) /* (AD18) RGMII1_TD3 */
>> 229 AM62X_IOPAD(0x130, PIN_OUTPUT, 0) /* (AE19) RGMII1_TXC */
>> 230 AM62X_IOPAD(0x12c, PIN_OUTPUT, 0) /* (AD19) RGMII1_TX_CTL */
>> 231 >;
>> 232 };
>> 233
>> 234 main_rgmii2_pins_default: main-rgmii2-pins-default {
111 pinctrl-single,pins = < 235 pinctrl-single,pins = <
112 AM62X_IOPAD(0x184, PIN 236 AM62X_IOPAD(0x184, PIN_INPUT, 0) /* (AE23) RGMII2_RD0 */
113 AM62X_IOPAD(0x188, PIN 237 AM62X_IOPAD(0x188, PIN_INPUT, 0) /* (AB20) RGMII2_RD1 */
114 AM62X_IOPAD(0x18c, PIN 238 AM62X_IOPAD(0x18c, PIN_INPUT, 0) /* (AC21) RGMII2_RD2 */
115 AM62X_IOPAD(0x190, PIN 239 AM62X_IOPAD(0x190, PIN_INPUT, 0) /* (AE22) RGMII2_RD3 */
116 AM62X_IOPAD(0x180, PIN 240 AM62X_IOPAD(0x180, PIN_INPUT, 0) /* (AD23) RGMII2_RXC */
117 AM62X_IOPAD(0x17c, PIN 241 AM62X_IOPAD(0x17c, PIN_INPUT, 0) /* (AD22) RGMII2_RX_CTL */
118 AM62X_IOPAD(0x16c, PIN 242 AM62X_IOPAD(0x16c, PIN_OUTPUT, 0) /* (Y18) RGMII2_TD0 */
119 AM62X_IOPAD(0x170, PIN 243 AM62X_IOPAD(0x170, PIN_OUTPUT, 0) /* (AA18) RGMII2_TD1 */
120 AM62X_IOPAD(0x174, PIN 244 AM62X_IOPAD(0x174, PIN_OUTPUT, 0) /* (AD21) RGMII2_TD2 */
121 AM62X_IOPAD(0x178, PIN 245 AM62X_IOPAD(0x178, PIN_OUTPUT, 0) /* (AC20) RGMII2_TD3 */
122 AM62X_IOPAD(0x168, PIN 246 AM62X_IOPAD(0x168, PIN_OUTPUT, 0) /* (AE21) RGMII2_TXC */
123 AM62X_IOPAD(0x164, PIN 247 AM62X_IOPAD(0x164, PIN_OUTPUT, 0) /* (AA19) RGMII2_TX_CTL */
124 >; 248 >;
125 }; 249 };
126 250
127 ospi0_pins_default: ospi0-default-pins !! 251 ospi0_pins_default: ospi0-pins-default {
128 bootph-all; <<
129 pinctrl-single,pins = < 252 pinctrl-single,pins = <
130 AM62X_IOPAD(0x000, PIN 253 AM62X_IOPAD(0x000, PIN_OUTPUT, 0) /* (H24) OSPI0_CLK */
131 AM62X_IOPAD(0x02c, PIN 254 AM62X_IOPAD(0x02c, PIN_OUTPUT, 0) /* (F23) OSPI0_CSn0 */
132 AM62X_IOPAD(0x00c, PIN 255 AM62X_IOPAD(0x00c, PIN_INPUT, 0) /* (E25) OSPI0_D0 */
133 AM62X_IOPAD(0x010, PIN 256 AM62X_IOPAD(0x010, PIN_INPUT, 0) /* (G24) OSPI0_D1 */
134 AM62X_IOPAD(0x014, PIN 257 AM62X_IOPAD(0x014, PIN_INPUT, 0) /* (F25) OSPI0_D2 */
135 AM62X_IOPAD(0x018, PIN 258 AM62X_IOPAD(0x018, PIN_INPUT, 0) /* (F24) OSPI0_D3 */
136 AM62X_IOPAD(0x01c, PIN 259 AM62X_IOPAD(0x01c, PIN_INPUT, 0) /* (J23) OSPI0_D4 */
137 AM62X_IOPAD(0x020, PIN 260 AM62X_IOPAD(0x020, PIN_INPUT, 0) /* (J25) OSPI0_D5 */
138 AM62X_IOPAD(0x024, PIN 261 AM62X_IOPAD(0x024, PIN_INPUT, 0) /* (H25) OSPI0_D6 */
139 AM62X_IOPAD(0x028, PIN 262 AM62X_IOPAD(0x028, PIN_INPUT, 0) /* (J22) OSPI0_D7 */
140 AM62X_IOPAD(0x008, PIN 263 AM62X_IOPAD(0x008, PIN_INPUT, 0) /* (J24) OSPI0_DQS */
141 >; 264 >;
142 }; 265 };
143 266
144 vdd_sd_dv_pins_default: vdd-sd-dv-defa !! 267 vdd_sd_dv_pins_default: vdd-sd-dv-pins-default {
145 bootph-all; <<
146 pinctrl-single,pins = < 268 pinctrl-single,pins = <
147 AM62X_IOPAD(0x07c, PIN 269 AM62X_IOPAD(0x07c, PIN_OUTPUT, 7) /* (P25) GPMC0_CLK.GPIO0_31 */
148 >; 270 >;
149 }; 271 };
150 272
151 main_gpio1_ioexp_intr_pins_default: ma !! 273 main_gpio1_ioexp_intr_pins_default: main-gpio1-ioexp-intr-pins-default {
152 bootph-all; <<
153 pinctrl-single,pins = < 274 pinctrl-single,pins = <
154 AM62X_IOPAD(0x01d4, PI 275 AM62X_IOPAD(0x01d4, PIN_INPUT, 7) /* (B15) UART0_RTSn.GPIO1_23 */
155 >; 276 >;
156 }; 277 };
157 }; 278 };
158 279
159 &main_gpio0 { !! 280 &wkup_uart0 {
160 bootph-all; !! 281 /* WKUP UART0 is used by DM firmware */
>> 282 status = "reserved";
>> 283 };
>> 284
>> 285 &mcu_uart0 {
>> 286 status = "disabled";
>> 287 };
>> 288
>> 289 &main_uart0 {
>> 290 pinctrl-names = "default";
>> 291 pinctrl-0 = <&main_uart0_pins_default>;
>> 292 };
>> 293
>> 294 &main_uart1 {
>> 295 /* Main UART1 is used by TIFS firmware */
>> 296 status = "reserved";
>> 297 };
>> 298
>> 299 &main_uart2 {
>> 300 status = "disabled";
>> 301 };
>> 302
>> 303 &main_uart3 {
>> 304 status = "disabled";
>> 305 };
>> 306
>> 307 &main_uart4 {
>> 308 status = "disabled";
161 }; 309 };
162 310
163 &main_gpio1 { !! 311 &main_uart5 {
164 bootph-all; !! 312 status = "disabled";
>> 313 };
>> 314
>> 315 &main_uart6 {
>> 316 status = "disabled";
>> 317 };
>> 318
>> 319 &mcu_i2c0 {
>> 320 status = "disabled";
>> 321 };
>> 322
>> 323 &wkup_i2c0 {
>> 324 status = "disabled";
>> 325 };
>> 326
>> 327 &main_i2c0 {
>> 328 pinctrl-names = "default";
>> 329 pinctrl-0 = <&main_i2c0_pins_default>;
>> 330 clock-frequency = <400000>;
165 }; 331 };
166 332
167 &main_i2c1 { 333 &main_i2c1 {
168 bootph-all; !! 334 pinctrl-names = "default";
>> 335 pinctrl-0 = <&main_i2c1_pins_default>;
>> 336 clock-frequency = <400000>;
>> 337
169 exp1: gpio@22 { 338 exp1: gpio@22 {
170 bootph-all; <<
171 compatible = "ti,tca6424"; 339 compatible = "ti,tca6424";
172 reg = <0x22>; 340 reg = <0x22>;
173 gpio-controller; 341 gpio-controller;
174 #gpio-cells = <2>; 342 #gpio-cells = <2>;
175 gpio-line-names = "GPIO_CPSW2_ 343 gpio-line-names = "GPIO_CPSW2_RST", "GPIO_CPSW1_RST",
176 "PRU_DETECT 344 "PRU_DETECT", "MMC1_SD_EN",
177 "VPP_LDO_EN 345 "VPP_LDO_EN", "EXP_PS_3V3_En",
178 "EXP_PS_5V0 346 "EXP_PS_5V0_En", "EXP_HAT_DETECT",
179 "GPIO_AUD_R 347 "GPIO_AUD_RSTn", "GPIO_eMMC_RSTn",
180 "UART1_FET_ 348 "UART1_FET_BUF_EN", "WL_LT_EN",
181 "GPIO_HDMI_ 349 "GPIO_HDMI_RSTn", "CSI_GPIO1",
182 "CSI_GPIO2" 350 "CSI_GPIO2", "PRU_3V3_EN",
183 "HDMI_INTn" !! 351 "HDMI_INTn", "TEST_GPIO2",
184 "MCASP1_FET 352 "MCASP1_FET_EN", "MCASP1_BUF_BT_EN",
185 "MCASP1_FET 353 "MCASP1_FET_SEL", "UART1_FET_SEL",
186 "TSINT#", " 354 "TSINT#", "IO_EXP_TEST_LED";
187 355
188 interrupt-parent = <&main_gpio 356 interrupt-parent = <&main_gpio1>;
189 interrupts = <23 IRQ_TYPE_EDGE 357 interrupts = <23 IRQ_TYPE_EDGE_FALLING>;
190 interrupt-controller; 358 interrupt-controller;
191 #interrupt-cells = <2>; 359 #interrupt-cells = <2>;
192 360
193 pinctrl-names = "default"; 361 pinctrl-names = "default";
194 pinctrl-0 = <&main_gpio1_ioexp 362 pinctrl-0 = <&main_gpio1_ioexp_intr_pins_default>;
195 }; 363 };
196 }; 364 };
197 365
>> 366 &main_i2c2 {
>> 367 status = "disabled";
>> 368 };
>> 369
>> 370 &main_i2c3 {
>> 371 status = "disabled";
>> 372 };
>> 373
>> 374 &sdhci0 {
>> 375 pinctrl-names = "default";
>> 376 pinctrl-0 = <&main_mmc0_pins_default>;
>> 377 ti,driver-strength-ohm = <50>;
>> 378 disable-wp;
>> 379 };
>> 380
198 &sdhci1 { 381 &sdhci1 {
>> 382 /* SD/MMC */
199 vmmc-supply = <&vdd_mmc1>; 383 vmmc-supply = <&vdd_mmc1>;
200 vqmmc-supply = <&vdd_sd_dv>; 384 vqmmc-supply = <&vdd_sd_dv>;
>> 385 pinctrl-names = "default";
>> 386 pinctrl-0 = <&main_mmc1_pins_default>;
>> 387 ti,driver-strength-ohm = <50>;
>> 388 disable-wp;
201 }; 389 };
202 390
203 &cpsw3g { 391 &cpsw3g {
204 pinctrl-names = "default"; 392 pinctrl-names = "default";
205 pinctrl-0 = <&main_rgmii1_pins_default !! 393 pinctrl-0 = <&main_mdio1_pins_default
>> 394 &main_rgmii1_pins_default
>> 395 &main_rgmii2_pins_default>;
>> 396 };
>> 397
>> 398 &cpsw_port1 {
>> 399 phy-mode = "rgmii-rxid";
>> 400 phy-handle = <&cpsw3g_phy0>;
206 }; 401 };
207 402
208 &cpsw_port2 { 403 &cpsw_port2 {
209 phy-mode = "rgmii-rxid"; 404 phy-mode = "rgmii-rxid";
210 phy-handle = <&cpsw3g_phy1>; 405 phy-handle = <&cpsw3g_phy1>;
211 }; 406 };
212 407
213 &cpsw3g_mdio { 408 &cpsw3g_mdio {
>> 409 cpsw3g_phy0: ethernet-phy@0 {
>> 410 reg = <0>;
>> 411 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
>> 412 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
>> 413 ti,min-output-impedance;
>> 414 };
>> 415
214 cpsw3g_phy1: ethernet-phy@1 { 416 cpsw3g_phy1: ethernet-phy@1 {
215 reg = <1>; 417 reg = <1>;
216 ti,rx-internal-delay = <DP8386 418 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
217 ti,fifo-depth = <DP83867_PHYCR 419 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
218 ti,min-output-impedance; 420 ti,min-output-impedance;
219 }; 421 };
220 }; 422 };
221 423
222 &mailbox0_cluster0 { 424 &mailbox0_cluster0 {
223 mbox_m4_0: mbox-m4-0 { 425 mbox_m4_0: mbox-m4-0 {
224 ti,mbox-rx = <0 0 0>; 426 ti,mbox-rx = <0 0 0>;
225 ti,mbox-tx = <1 0 0>; 427 ti,mbox-tx = <1 0 0>;
226 }; 428 };
227 }; 429 };
228 430
229 &fss { <<
230 bootph-all; <<
231 }; <<
232 <<
233 &ospi0 { 431 &ospi0 {
234 bootph-all; <<
235 status = "okay"; <<
236 pinctrl-names = "default"; 432 pinctrl-names = "default";
237 pinctrl-0 = <&ospi0_pins_default>; 433 pinctrl-0 = <&ospi0_pins_default>;
238 434
239 flash@0 { !! 435 flash@0{
240 bootph-all; <<
241 compatible = "jedec,spi-nor"; 436 compatible = "jedec,spi-nor";
242 reg = <0x0>; 437 reg = <0x0>;
243 spi-tx-bus-width = <8>; 438 spi-tx-bus-width = <8>;
244 spi-rx-bus-width = <8>; 439 spi-rx-bus-width = <8>;
245 spi-max-frequency = <25000000> 440 spi-max-frequency = <25000000>;
246 cdns,tshsl-ns = <60>; 441 cdns,tshsl-ns = <60>;
247 cdns,tsd2d-ns = <60>; 442 cdns,tsd2d-ns = <60>;
248 cdns,tchsh-ns = <60>; 443 cdns,tchsh-ns = <60>;
249 cdns,tslch-ns = <60>; 444 cdns,tslch-ns = <60>;
250 cdns,read-delay = <4>; 445 cdns,read-delay = <4>;
251 446
252 partitions { 447 partitions {
253 bootph-all; <<
254 compatible = "fixed-pa 448 compatible = "fixed-partitions";
255 #address-cells = <1>; 449 #address-cells = <1>;
256 #size-cells = <1>; 450 #size-cells = <1>;
257 451
258 partition@0 { 452 partition@0 {
259 label = "ospi. 453 label = "ospi.tiboot3";
260 reg = <0x0 0x8 454 reg = <0x0 0x80000>;
261 }; 455 };
262 456
263 partition@80000 { 457 partition@80000 {
264 label = "ospi. 458 label = "ospi.tispl";
265 reg = <0x80000 459 reg = <0x80000 0x200000>;
266 }; 460 };
267 461
268 partition@280000 { 462 partition@280000 {
269 label = "ospi. 463 label = "ospi.u-boot";
270 reg = <0x28000 464 reg = <0x280000 0x400000>;
271 }; 465 };
272 466
273 partition@680000 { 467 partition@680000 {
274 label = "ospi. 468 label = "ospi.env";
275 reg = <0x68000 469 reg = <0x680000 0x40000>;
276 }; 470 };
277 471
278 partition@6c0000 { 472 partition@6c0000 {
279 label = "ospi. 473 label = "ospi.env.backup";
280 reg = <0x6c000 474 reg = <0x6c0000 0x40000>;
281 }; 475 };
282 476
283 partition@800000 { 477 partition@800000 {
284 label = "ospi. 478 label = "ospi.rootfs";
285 reg = <0x80000 479 reg = <0x800000 0x37c0000>;
286 }; 480 };
287 481
288 partition@3fc0000 { 482 partition@3fc0000 {
289 bootph-pre-ram <<
290 label = "ospi. 483 label = "ospi.phypattern";
291 reg = <0x3fc00 484 reg = <0x3fc0000 0x40000>;
292 }; 485 };
293 }; 486 };
294 }; 487 };
295 }; 488 };
296 489
297 &tlv320aic3106 { !! 490 &ecap0 {
298 DVDD-supply = <&vcc_1v8>; !! 491 status = "disabled";
>> 492 };
>> 493
>> 494 &ecap1 {
>> 495 status = "disabled";
>> 496 };
>> 497
>> 498 &ecap2 {
>> 499 status = "disabled";
>> 500 };
>> 501
>> 502 &main_mcan0 {
>> 503 status = "disabled";
>> 504 };
>> 505
>> 506 &epwm0 {
>> 507 status = "disabled";
>> 508 };
>> 509
>> 510 &epwm1 {
>> 511 status = "disabled";
>> 512 };
>> 513
>> 514 &epwm2 {
>> 515 status = "disabled";
299 }; 516 };
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