1 // SPDX-License-Identifier: GPL-2.0-only OR MI !! 1 // SPDX-License-Identifier: GPL-2.0
2 /* 2 /*
3 * Device Tree Source for AM62A SoC Family Mai 3 * Device Tree Source for AM62A SoC Family Main Domain peripherals
4 * 4 *
5 * Copyright (C) 2022-2024 Texas Instruments I !! 5 * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
6 */ 6 */
7 7
8 &cbass_main { 8 &cbass_main {
9 oc_sram: sram@70000000 { 9 oc_sram: sram@70000000 {
10 compatible = "mmio-sram"; 10 compatible = "mmio-sram";
11 reg = <0x00 0x70000000 0x00 0x 11 reg = <0x00 0x70000000 0x00 0x10000>;
12 #address-cells = <1>; 12 #address-cells = <1>;
13 #size-cells = <1>; 13 #size-cells = <1>;
14 ranges = <0x0 0x00 0x70000000 14 ranges = <0x0 0x00 0x70000000 0x10000>;
15 }; 15 };
16 16
17 gic500: interrupt-controller@1800000 { 17 gic500: interrupt-controller@1800000 {
18 compatible = "arm,gic-v3"; 18 compatible = "arm,gic-v3";
19 reg = <0x00 0x01800000 0x00 0x 19 reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */
20 <0x00 0x01880000 0x00 0x 20 <0x00 0x01880000 0x00 0xc0000>, /* GICR */
21 <0x00 0x01880000 0x00 0x 21 <0x00 0x01880000 0x00 0xc0000>, /* GICR */
22 <0x01 0x00000000 0x00 0x 22 <0x01 0x00000000 0x00 0x2000>, /* GICC */
23 <0x01 0x00010000 0x00 0x 23 <0x01 0x00010000 0x00 0x1000>, /* GICH */
24 <0x01 0x00020000 0x00 0x 24 <0x01 0x00020000 0x00 0x2000>; /* GICV */
25 #address-cells = <2>; 25 #address-cells = <2>;
26 #size-cells = <2>; 26 #size-cells = <2>;
27 ranges; 27 ranges;
28 #interrupt-cells = <3>; 28 #interrupt-cells = <3>;
29 interrupt-controller; 29 interrupt-controller;
30 /* 30 /*
31 * vcpumntirq: 31 * vcpumntirq:
32 * virtual CPU interface maint 32 * virtual CPU interface maintenance interrupt
33 */ 33 */
34 interrupts = <GIC_PPI 9 IRQ_TY 34 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
35 35
36 gic_its: msi-controller@182000 36 gic_its: msi-controller@1820000 {
37 compatible = "arm,gic- 37 compatible = "arm,gic-v3-its";
38 reg = <0x00 0x01820000 38 reg = <0x00 0x01820000 0x00 0x10000>;
39 socionext,synquacer-pr 39 socionext,synquacer-pre-its = <0x1000000 0x400000>;
40 msi-controller; 40 msi-controller;
41 #msi-cells = <1>; 41 #msi-cells = <1>;
42 }; 42 };
43 }; 43 };
44 44
45 main_conf: bus@100000 { !! 45 main_conf: syscon@100000 {
46 compatible = "simple-bus"; !! 46 compatible = "ti,j721e-system-controller", "syscon", "simple-mfd";
>> 47 reg = <0x00 0x00100000 0x00 0x20000>;
47 #address-cells = <1>; 48 #address-cells = <1>;
48 #size-cells = <1>; 49 #size-cells = <1>;
49 ranges = <0x00 0x00 0x00100000 50 ranges = <0x00 0x00 0x00100000 0x20000>;
50 51
51 phy_gmii_sel: phy@4044 { 52 phy_gmii_sel: phy@4044 {
52 compatible = "ti,am654 53 compatible = "ti,am654-phy-gmii-sel";
53 reg = <0x4044 0x8>; 54 reg = <0x4044 0x8>;
54 #phy-cells = <1>; 55 #phy-cells = <1>;
55 }; 56 };
56 57
57 epwm_tbclk: clock-controller@4 58 epwm_tbclk: clock-controller@4130 {
58 compatible = "ti,am62- 59 compatible = "ti,am62-epwm-tbclk";
59 reg = <0x4130 0x4>; 60 reg = <0x4130 0x4>;
60 #clock-cells = <1>; 61 #clock-cells = <1>;
61 }; 62 };
62 <<
63 audio_refclk0: clock-controlle <<
64 compatible = "ti,am62- <<
65 reg = <0x82e0 0x4>; <<
66 clocks = <&k3_clks 157 <<
67 assigned-clocks = <&k3 <<
68 assigned-clock-parents <<
69 #clock-cells = <0>; <<
70 }; <<
71 <<
72 audio_refclk1: clock-controlle <<
73 compatible = "ti,am62- <<
74 reg = <0x82e4 0x4>; <<
75 clocks = <&k3_clks 157 <<
76 assigned-clocks = <&k3 <<
77 assigned-clock-parents <<
78 #clock-cells = <0>; <<
79 }; <<
80 }; 63 };
81 64
82 dmss: bus@48000000 { 65 dmss: bus@48000000 {
83 compatible = "simple-bus"; 66 compatible = "simple-bus";
84 #address-cells = <2>; 67 #address-cells = <2>;
85 #size-cells = <2>; 68 #size-cells = <2>;
86 dma-ranges; 69 dma-ranges;
87 ranges = <0x00 0x48000000 0x00 70 ranges = <0x00 0x48000000 0x00 0x48000000 0x00 0x06000000>;
88 71
89 ti,sci-dev-id = <25>; 72 ti,sci-dev-id = <25>;
90 73
91 secure_proxy_main: mailbox@4d0 74 secure_proxy_main: mailbox@4d000000 {
92 compatible = "ti,am654 75 compatible = "ti,am654-secure-proxy";
93 reg = <0x00 0x4d000000 76 reg = <0x00 0x4d000000 0x00 0x80000>,
94 <0x00 0x4a600000 77 <0x00 0x4a600000 0x00 0x80000>,
95 <0x00 0x4a400000 78 <0x00 0x4a400000 0x00 0x80000>;
96 reg-names = "target_da 79 reg-names = "target_data", "rt", "scfg";
97 #mbox-cells = <1>; 80 #mbox-cells = <1>;
98 interrupt-names = "rx_ 81 interrupt-names = "rx_012";
99 interrupts = <GIC_SPI 82 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
100 }; 83 };
101 84
102 inta_main_dmss: interrupt-cont 85 inta_main_dmss: interrupt-controller@48000000 {
103 compatible = "ti,sci-i 86 compatible = "ti,sci-inta";
104 reg = <0x00 0x48000000 87 reg = <0x00 0x48000000 0x00 0x100000>;
105 #interrupt-cells = <0> 88 #interrupt-cells = <0>;
106 interrupt-controller; 89 interrupt-controller;
107 interrupt-parent = <&g 90 interrupt-parent = <&gic500>;
108 msi-controller; 91 msi-controller;
109 ti,sci = <&dmsc>; 92 ti,sci = <&dmsc>;
110 ti,sci-dev-id = <28>; 93 ti,sci-dev-id = <28>;
111 ti,interrupt-ranges = 94 ti,interrupt-ranges = <6 70 34>;
112 ti,unmapped-event-sour 95 ti,unmapped-event-sources = <&main_bcdma>, <&main_pktdma>;
113 }; 96 };
114 97
115 main_bcdma: dma-controller@485 98 main_bcdma: dma-controller@485c0100 {
116 compatible = "ti,am64- 99 compatible = "ti,am64-dmss-bcdma";
117 reg = <0x00 0x485c0100 100 reg = <0x00 0x485c0100 0x00 0x100>,
118 <0x00 0x4c000000 101 <0x00 0x4c000000 0x00 0x20000>,
119 <0x00 0x4a820000 102 <0x00 0x4a820000 0x00 0x20000>,
120 <0x00 0x4aa40000 103 <0x00 0x4aa40000 0x00 0x20000>,
121 <0x00 0x4bc00000 !! 104 <0x00 0x4bc00000 0x00 0x100000>;
122 <0x00 0x48600000 !! 105 reg-names = "gcfg", "bchanrt", "rchanrt", "tchanrt", "ringrt";
123 <0x00 0x484a4000 <<
124 <0x00 0x484c2000 <<
125 <0x00 0x48420000 <<
126 reg-names = "gcfg", "b <<
127 "ring", "t <<
128 msi-parent = <&inta_ma 106 msi-parent = <&inta_main_dmss>;
129 #dma-cells = <3>; 107 #dma-cells = <3>;
130 ti,sci = <&dmsc>; 108 ti,sci = <&dmsc>;
131 ti,sci-dev-id = <26>; 109 ti,sci-dev-id = <26>;
132 ti,sci-rm-range-bchan 110 ti,sci-rm-range-bchan = <0x20>; /* BLOCK_COPY_CHAN */
133 ti,sci-rm-range-rchan 111 ti,sci-rm-range-rchan = <0x21>; /* SPLIT_TR_RX_CHAN */
134 ti,sci-rm-range-tchan 112 ti,sci-rm-range-tchan = <0x22>; /* SPLIT_TR_TX_CHAN */
135 }; 113 };
136 114
137 main_pktdma: dma-controller@48 115 main_pktdma: dma-controller@485c0000 {
138 compatible = "ti,am64- 116 compatible = "ti,am64-dmss-pktdma";
139 reg = <0x00 0x485c0000 117 reg = <0x00 0x485c0000 0x00 0x100>,
140 <0x00 0x4a800000 118 <0x00 0x4a800000 0x00 0x20000>,
141 <0x00 0x4aa00000 !! 119 <0x00 0x4aa00000 0x00 0x40000>,
142 <0x00 0x4b800000 !! 120 <0x00 0x4b800000 0x00 0x400000>;
143 <0x00 0x485e0000 !! 121 reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt";
144 <0x00 0x484a0000 <<
145 <0x00 0x484c0000 <<
146 <0x00 0x48430000 <<
147 reg-names = "gcfg", "r <<
148 "ring", "t <<
149 msi-parent = <&inta_ma 122 msi-parent = <&inta_main_dmss>;
150 #dma-cells = <2>; 123 #dma-cells = <2>;
151 ti,sci = <&dmsc>; 124 ti,sci = <&dmsc>;
152 ti,sci-dev-id = <30>; 125 ti,sci-dev-id = <30>;
153 ti,sci-rm-range-tchan 126 ti,sci-rm-range-tchan = <0x23>, /* UNMAPPED_TX_CHAN */
154 127 <0x24>, /* CPSW_TX_CHAN */
155 128 <0x25>, /* SAUL_TX_0_CHAN */
156 129 <0x26>; /* SAUL_TX_1_CHAN */
157 ti,sci-rm-range-tflow 130 ti,sci-rm-range-tflow = <0x10>, /* RING_UNMAPPED_TX_CHAN */
158 131 <0x11>, /* RING_CPSW_TX_CHAN */
159 132 <0x12>, /* RING_SAUL_TX_0_CHAN */
160 133 <0x13>; /* RING_SAUL_TX_1_CHAN */
161 ti,sci-rm-range-rchan 134 ti,sci-rm-range-rchan = <0x29>, /* UNMAPPED_RX_CHAN */
162 135 <0x2b>, /* CPSW_RX_CHAN */
163 136 <0x2d>, /* SAUL_RX_0_CHAN */
164 137 <0x2f>, /* SAUL_RX_1_CHAN */
165 138 <0x31>, /* SAUL_RX_2_CHAN */
166 139 <0x33>; /* SAUL_RX_3_CHAN */
167 ti,sci-rm-range-rflow 140 ti,sci-rm-range-rflow = <0x2a>, /* FLOW_UNMAPPED_RX_CHAN */
168 141 <0x2c>, /* FLOW_CPSW_RX_CHAN */
169 142 <0x2e>, /* FLOW_SAUL_RX_0/1_CHAN */
170 143 <0x32>; /* FLOW_SAUL_RX_2/3_CHAN */
171 }; 144 };
172 }; 145 };
173 146
174 dmss_csi: bus@4e000000 { <<
175 compatible = "simple-bus"; <<
176 #address-cells = <2>; <<
177 #size-cells = <2>; <<
178 dma-ranges; <<
179 ranges = <0x00 0x4e000000 0x00 <<
180 <<
181 ti,sci-dev-id = <198>; <<
182 <<
183 inta_main_dmss_csi: interrupt- <<
184 compatible = "ti,sci-i <<
185 reg = <0x00 0x4e0a0000 <<
186 #interrupt-cells = <0> <<
187 interrupt-controller; <<
188 interrupt-parent = <&g <<
189 msi-controller; <<
190 ti,sci = <&dmsc>; <<
191 ti,sci-dev-id = <200>; <<
192 ti,interrupt-ranges = <<
193 ti,unmapped-event-sour <<
194 power-domains = <&k3_p <<
195 }; <<
196 <<
197 main_bcdma_csi: dma-controller <<
198 compatible = "ti,am62a <<
199 reg = <0x00 0x4e230000 <<
200 <0x00 0x4e180000 <<
201 <0x00 0x4e100000 <<
202 reg-names = "gcfg", "r <<
203 msi-parent = <&inta_ma <<
204 #dma-cells = <3>; <<
205 ti,sci = <&dmsc>; <<
206 ti,sci-dev-id = <199>; <<
207 ti,sci-rm-range-rchan <<
208 power-domains = <&k3_p <<
209 }; <<
210 }; <<
211 <<
212 dmsc: system-controller@44043000 { 147 dmsc: system-controller@44043000 {
213 compatible = "ti,k2g-sci"; 148 compatible = "ti,k2g-sci";
214 reg = <0x00 0x44043000 0x00 0x 149 reg = <0x00 0x44043000 0x00 0xfe0>;
215 reg-names = "debug_messages"; 150 reg-names = "debug_messages";
216 ti,host-id = <12>; 151 ti,host-id = <12>;
217 mbox-names = "rx", "tx"; 152 mbox-names = "rx", "tx";
218 mboxes = <&secure_proxy_main 1 153 mboxes = <&secure_proxy_main 12>,
219 <&secure_proxy_main 1 154 <&secure_proxy_main 13>;
220 155
221 k3_pds: power-controller { 156 k3_pds: power-controller {
222 compatible = "ti,sci-p 157 compatible = "ti,sci-pm-domain";
223 #power-domain-cells = 158 #power-domain-cells = <2>;
224 }; 159 };
225 160
226 k3_clks: clock-controller { 161 k3_clks: clock-controller {
227 compatible = "ti,k2g-s 162 compatible = "ti,k2g-sci-clk";
228 #clock-cells = <2>; 163 #clock-cells = <2>;
229 }; 164 };
230 165
231 k3_reset: reset-controller { 166 k3_reset: reset-controller {
232 compatible = "ti,sci-r 167 compatible = "ti,sci-reset";
233 #reset-cells = <2>; 168 #reset-cells = <2>;
234 }; 169 };
235 }; 170 };
236 171
237 crypto: crypto@40900000 { <<
238 compatible = "ti,am62-sa3ul"; <<
239 reg = <0x00 0x40900000 0x00 0x <<
240 dmas = <&main_pktdma 0xf501 0> <<
241 <&main_pktdma 0x7507 0> <<
242 dma-names = "tx", "rx1", "rx2" <<
243 }; <<
244 <<
245 secure_proxy_sa3: mailbox@43600000 { 172 secure_proxy_sa3: mailbox@43600000 {
246 compatible = "ti,am654-secure- 173 compatible = "ti,am654-secure-proxy";
247 #mbox-cells = <1>; 174 #mbox-cells = <1>;
248 reg-names = "target_data", "rt 175 reg-names = "target_data", "rt", "scfg";
249 reg = <0x00 0x43600000 0x00 0x 176 reg = <0x00 0x43600000 0x00 0x10000>,
250 <0x00 0x44880000 0x00 0x 177 <0x00 0x44880000 0x00 0x20000>,
251 <0x00 0x44860000 0x00 0x 178 <0x00 0x44860000 0x00 0x20000>;
252 /* 179 /*
253 * Marked Disabled: 180 * Marked Disabled:
254 * Node is incomplete as it is 181 * Node is incomplete as it is meant for bootloaders and
255 * firmware on non-MPU process 182 * firmware on non-MPU processors
256 */ 183 */
257 status = "disabled"; 184 status = "disabled";
258 }; 185 };
259 186
260 main_pmx0: pinctrl@f4000 { 187 main_pmx0: pinctrl@f4000 {
261 compatible = "pinctrl-single"; 188 compatible = "pinctrl-single";
262 reg = <0x00 0xf4000 0x00 0x2ac 189 reg = <0x00 0xf4000 0x00 0x2ac>;
263 #pinctrl-cells = <1>; 190 #pinctrl-cells = <1>;
264 pinctrl-single,register-width 191 pinctrl-single,register-width = <32>;
265 pinctrl-single,function-mask = 192 pinctrl-single,function-mask = <0xffffffff>;
266 }; 193 };
267 194
268 main_esm: esm@420000 { <<
269 compatible = "ti,j721e-esm"; <<
270 reg = <0x0 0x420000 0x0 0x1000 <<
271 bootph-pre-ram; <<
272 /* Interrupt sources: rti0, rt <<
273 ti,esm-pins = <192>, <193>, <1 <<
274 }; <<
275 <<
276 main_timer0: timer@2400000 { 195 main_timer0: timer@2400000 {
277 compatible = "ti,am654-timer"; 196 compatible = "ti,am654-timer";
278 reg = <0x00 0x2400000 0x00 0x4 197 reg = <0x00 0x2400000 0x00 0x400>;
279 interrupts = <GIC_SPI 120 IRQ_ 198 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
280 clocks = <&k3_clks 36 2>; 199 clocks = <&k3_clks 36 2>;
281 clock-names = "fck"; 200 clock-names = "fck";
282 assigned-clocks = <&k3_clks 36 201 assigned-clocks = <&k3_clks 36 2>;
283 assigned-clock-parents = <&k3_ 202 assigned-clock-parents = <&k3_clks 36 3>;
284 power-domains = <&k3_pds 36 TI 203 power-domains = <&k3_pds 36 TI_SCI_PD_EXCLUSIVE>;
285 ti,timer-pwm; 204 ti,timer-pwm;
286 }; 205 };
287 206
288 main_timer1: timer@2410000 { 207 main_timer1: timer@2410000 {
289 compatible = "ti,am654-timer"; 208 compatible = "ti,am654-timer";
290 reg = <0x00 0x2410000 0x00 0x4 209 reg = <0x00 0x2410000 0x00 0x400>;
291 interrupts = <GIC_SPI 121 IRQ_ 210 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
292 clocks = <&k3_clks 37 2>; 211 clocks = <&k3_clks 37 2>;
293 clock-names = "fck"; 212 clock-names = "fck";
294 assigned-clocks = <&k3_clks 37 213 assigned-clocks = <&k3_clks 37 2>;
295 assigned-clock-parents = <&k3_ 214 assigned-clock-parents = <&k3_clks 37 3>;
296 power-domains = <&k3_pds 37 TI 215 power-domains = <&k3_pds 37 TI_SCI_PD_EXCLUSIVE>;
297 ti,timer-pwm; 216 ti,timer-pwm;
298 }; 217 };
299 218
300 main_timer2: timer@2420000 { 219 main_timer2: timer@2420000 {
301 compatible = "ti,am654-timer"; 220 compatible = "ti,am654-timer";
302 reg = <0x00 0x2420000 0x00 0x4 221 reg = <0x00 0x2420000 0x00 0x400>;
303 interrupts = <GIC_SPI 122 IRQ_ 222 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
304 clocks = <&k3_clks 38 2>; 223 clocks = <&k3_clks 38 2>;
305 clock-names = "fck"; 224 clock-names = "fck";
306 assigned-clocks = <&k3_clks 38 225 assigned-clocks = <&k3_clks 38 2>;
307 assigned-clock-parents = <&k3_ 226 assigned-clock-parents = <&k3_clks 38 3>;
308 power-domains = <&k3_pds 38 TI 227 power-domains = <&k3_pds 38 TI_SCI_PD_EXCLUSIVE>;
309 ti,timer-pwm; 228 ti,timer-pwm;
310 }; 229 };
311 230
312 main_timer3: timer@2430000 { 231 main_timer3: timer@2430000 {
313 compatible = "ti,am654-timer"; 232 compatible = "ti,am654-timer";
314 reg = <0x00 0x2430000 0x00 0x4 233 reg = <0x00 0x2430000 0x00 0x400>;
315 interrupts = <GIC_SPI 123 IRQ_ 234 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
316 clocks = <&k3_clks 39 2>; 235 clocks = <&k3_clks 39 2>;
317 clock-names = "fck"; 236 clock-names = "fck";
318 assigned-clocks = <&k3_clks 39 237 assigned-clocks = <&k3_clks 39 2>;
319 assigned-clock-parents = <&k3_ 238 assigned-clock-parents = <&k3_clks 39 3>;
320 power-domains = <&k3_pds 39 TI 239 power-domains = <&k3_pds 39 TI_SCI_PD_EXCLUSIVE>;
321 ti,timer-pwm; 240 ti,timer-pwm;
322 }; 241 };
323 242
324 main_timer4: timer@2440000 { 243 main_timer4: timer@2440000 {
325 compatible = "ti,am654-timer"; 244 compatible = "ti,am654-timer";
326 reg = <0x00 0x2440000 0x00 0x4 245 reg = <0x00 0x2440000 0x00 0x400>;
327 interrupts = <GIC_SPI 124 IRQ_ 246 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
328 clocks = <&k3_clks 40 2>; 247 clocks = <&k3_clks 40 2>;
329 clock-names = "fck"; 248 clock-names = "fck";
330 assigned-clocks = <&k3_clks 40 249 assigned-clocks = <&k3_clks 40 2>;
331 assigned-clock-parents = <&k3_ 250 assigned-clock-parents = <&k3_clks 40 3>;
332 power-domains = <&k3_pds 40 TI 251 power-domains = <&k3_pds 40 TI_SCI_PD_EXCLUSIVE>;
333 ti,timer-pwm; 252 ti,timer-pwm;
334 }; 253 };
335 254
336 main_timer5: timer@2450000 { 255 main_timer5: timer@2450000 {
337 compatible = "ti,am654-timer"; 256 compatible = "ti,am654-timer";
338 reg = <0x00 0x2450000 0x00 0x4 257 reg = <0x00 0x2450000 0x00 0x400>;
339 interrupts = <GIC_SPI 125 IRQ_ 258 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
340 clocks = <&k3_clks 41 2>; 259 clocks = <&k3_clks 41 2>;
341 clock-names = "fck"; 260 clock-names = "fck";
342 assigned-clocks = <&k3_clks 41 261 assigned-clocks = <&k3_clks 41 2>;
343 assigned-clock-parents = <&k3_ 262 assigned-clock-parents = <&k3_clks 41 3>;
344 power-domains = <&k3_pds 41 TI 263 power-domains = <&k3_pds 41 TI_SCI_PD_EXCLUSIVE>;
345 ti,timer-pwm; 264 ti,timer-pwm;
346 }; 265 };
347 266
348 main_timer6: timer@2460000 { 267 main_timer6: timer@2460000 {
349 compatible = "ti,am654-timer"; 268 compatible = "ti,am654-timer";
350 reg = <0x00 0x2460000 0x00 0x4 269 reg = <0x00 0x2460000 0x00 0x400>;
351 interrupts = <GIC_SPI 126 IRQ_ 270 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
352 clocks = <&k3_clks 42 2>; 271 clocks = <&k3_clks 42 2>;
353 clock-names = "fck"; 272 clock-names = "fck";
354 assigned-clocks = <&k3_clks 42 273 assigned-clocks = <&k3_clks 42 2>;
355 assigned-clock-parents = <&k3_ 274 assigned-clock-parents = <&k3_clks 42 3>;
356 power-domains = <&k3_pds 42 TI 275 power-domains = <&k3_pds 42 TI_SCI_PD_EXCLUSIVE>;
357 ti,timer-pwm; 276 ti,timer-pwm;
358 }; 277 };
359 278
360 main_timer7: timer@2470000 { 279 main_timer7: timer@2470000 {
361 compatible = "ti,am654-timer"; 280 compatible = "ti,am654-timer";
362 reg = <0x00 0x2470000 0x00 0x4 281 reg = <0x00 0x2470000 0x00 0x400>;
363 interrupts = <GIC_SPI 127 IRQ_ 282 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
364 clocks = <&k3_clks 43 2>; 283 clocks = <&k3_clks 43 2>;
365 clock-names = "fck"; 284 clock-names = "fck";
366 assigned-clocks = <&k3_clks 43 285 assigned-clocks = <&k3_clks 43 2>;
367 assigned-clock-parents = <&k3_ 286 assigned-clock-parents = <&k3_clks 43 3>;
368 power-domains = <&k3_pds 43 TI 287 power-domains = <&k3_pds 43 TI_SCI_PD_EXCLUSIVE>;
369 ti,timer-pwm; 288 ti,timer-pwm;
370 }; 289 };
371 290
372 main_uart0: serial@2800000 { 291 main_uart0: serial@2800000 {
373 compatible = "ti,am64-uart", " 292 compatible = "ti,am64-uart", "ti,am654-uart";
374 reg = <0x00 0x02800000 0x00 0x 293 reg = <0x00 0x02800000 0x00 0x100>;
375 interrupts = <GIC_SPI 178 IRQ_ 294 interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
376 power-domains = <&k3_pds 146 T 295 power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>;
377 clocks = <&k3_clks 146 0>; 296 clocks = <&k3_clks 146 0>;
378 clock-names = "fclk"; 297 clock-names = "fclk";
379 status = "disabled"; 298 status = "disabled";
380 }; 299 };
381 300
382 main_uart1: serial@2810000 { 301 main_uart1: serial@2810000 {
383 compatible = "ti,am64-uart", " 302 compatible = "ti,am64-uart", "ti,am654-uart";
384 reg = <0x00 0x02810000 0x00 0x 303 reg = <0x00 0x02810000 0x00 0x100>;
385 interrupts = <GIC_SPI 179 IRQ_ 304 interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
386 power-domains = <&k3_pds 152 T 305 power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>;
387 clocks = <&k3_clks 152 0>; 306 clocks = <&k3_clks 152 0>;
388 clock-names = "fclk"; 307 clock-names = "fclk";
389 status = "disabled"; 308 status = "disabled";
390 }; 309 };
391 310
392 main_uart2: serial@2820000 { 311 main_uart2: serial@2820000 {
393 compatible = "ti,am64-uart", " 312 compatible = "ti,am64-uart", "ti,am654-uart";
394 reg = <0x00 0x02820000 0x00 0x 313 reg = <0x00 0x02820000 0x00 0x100>;
395 interrupts = <GIC_SPI 180 IRQ_ 314 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
396 power-domains = <&k3_pds 153 T 315 power-domains = <&k3_pds 153 TI_SCI_PD_EXCLUSIVE>;
397 clocks = <&k3_clks 153 0>; 316 clocks = <&k3_clks 153 0>;
398 clock-names = "fclk"; 317 clock-names = "fclk";
399 status = "disabled"; 318 status = "disabled";
400 }; 319 };
401 320
402 main_uart3: serial@2830000 { 321 main_uart3: serial@2830000 {
403 compatible = "ti,am64-uart", " 322 compatible = "ti,am64-uart", "ti,am654-uart";
404 reg = <0x00 0x02830000 0x00 0x 323 reg = <0x00 0x02830000 0x00 0x100>;
405 interrupts = <GIC_SPI 181 IRQ_ 324 interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>;
406 power-domains = <&k3_pds 154 T 325 power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>;
407 clocks = <&k3_clks 154 0>; 326 clocks = <&k3_clks 154 0>;
408 clock-names = "fclk"; 327 clock-names = "fclk";
409 status = "disabled"; 328 status = "disabled";
410 }; 329 };
411 330
412 main_uart4: serial@2840000 { 331 main_uart4: serial@2840000 {
413 compatible = "ti,am64-uart", " 332 compatible = "ti,am64-uart", "ti,am654-uart";
414 reg = <0x00 0x02840000 0x00 0x 333 reg = <0x00 0x02840000 0x00 0x100>;
415 interrupts = <GIC_SPI 182 IRQ_ 334 interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>;
416 power-domains = <&k3_pds 155 T 335 power-domains = <&k3_pds 155 TI_SCI_PD_EXCLUSIVE>;
417 clocks = <&k3_clks 155 0>; 336 clocks = <&k3_clks 155 0>;
418 clock-names = "fclk"; 337 clock-names = "fclk";
419 status = "disabled"; 338 status = "disabled";
420 }; 339 };
421 340
422 main_uart5: serial@2850000 { 341 main_uart5: serial@2850000 {
423 compatible = "ti,am64-uart", " 342 compatible = "ti,am64-uart", "ti,am654-uart";
424 reg = <0x00 0x02850000 0x00 0x 343 reg = <0x00 0x02850000 0x00 0x100>;
425 interrupts = <GIC_SPI 183 IRQ_ 344 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
426 power-domains = <&k3_pds 156 T 345 power-domains = <&k3_pds 156 TI_SCI_PD_EXCLUSIVE>;
427 clocks = <&k3_clks 156 0>; 346 clocks = <&k3_clks 156 0>;
428 clock-names = "fclk"; 347 clock-names = "fclk";
429 status = "disabled"; 348 status = "disabled";
430 }; 349 };
431 350
432 main_uart6: serial@2860000 { 351 main_uart6: serial@2860000 {
433 compatible = "ti,am64-uart", " 352 compatible = "ti,am64-uart", "ti,am654-uart";
434 reg = <0x00 0x02860000 0x00 0x 353 reg = <0x00 0x02860000 0x00 0x100>;
435 interrupts = <GIC_SPI 184 IRQ_ 354 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
436 power-domains = <&k3_pds 158 T 355 power-domains = <&k3_pds 158 TI_SCI_PD_EXCLUSIVE>;
437 clocks = <&k3_clks 158 0>; 356 clocks = <&k3_clks 158 0>;
438 clock-names = "fclk"; 357 clock-names = "fclk";
439 status = "disabled"; 358 status = "disabled";
440 }; 359 };
441 360
442 main_i2c0: i2c@20000000 { 361 main_i2c0: i2c@20000000 {
443 compatible = "ti,am64-i2c", "t 362 compatible = "ti,am64-i2c", "ti,omap4-i2c";
444 reg = <0x00 0x20000000 0x00 0x 363 reg = <0x00 0x20000000 0x00 0x100>;
445 interrupts = <GIC_SPI 161 IRQ_ 364 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
446 #address-cells = <1>; 365 #address-cells = <1>;
447 #size-cells = <0>; 366 #size-cells = <0>;
448 power-domains = <&k3_pds 102 T 367 power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>;
449 clocks = <&k3_clks 102 2>; 368 clocks = <&k3_clks 102 2>;
450 clock-names = "fck"; 369 clock-names = "fck";
451 status = "disabled"; 370 status = "disabled";
452 }; 371 };
453 372
454 main_i2c1: i2c@20010000 { 373 main_i2c1: i2c@20010000 {
455 compatible = "ti,am64-i2c", "t 374 compatible = "ti,am64-i2c", "ti,omap4-i2c";
456 reg = <0x00 0x20010000 0x00 0x 375 reg = <0x00 0x20010000 0x00 0x100>;
457 interrupts = <GIC_SPI 162 IRQ_ 376 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
458 #address-cells = <1>; 377 #address-cells = <1>;
459 #size-cells = <0>; 378 #size-cells = <0>;
460 power-domains = <&k3_pds 103 T 379 power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>;
461 clocks = <&k3_clks 103 2>; 380 clocks = <&k3_clks 103 2>;
462 clock-names = "fck"; 381 clock-names = "fck";
463 status = "disabled"; 382 status = "disabled";
464 }; 383 };
465 384
466 main_i2c2: i2c@20020000 { 385 main_i2c2: i2c@20020000 {
467 compatible = "ti,am64-i2c", "t 386 compatible = "ti,am64-i2c", "ti,omap4-i2c";
468 reg = <0x00 0x20020000 0x00 0x 387 reg = <0x00 0x20020000 0x00 0x100>;
469 interrupts = <GIC_SPI 163 IRQ_ 388 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
470 #address-cells = <1>; 389 #address-cells = <1>;
471 #size-cells = <0>; 390 #size-cells = <0>;
472 power-domains = <&k3_pds 104 T 391 power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>;
473 clocks = <&k3_clks 104 2>; 392 clocks = <&k3_clks 104 2>;
474 clock-names = "fck"; 393 clock-names = "fck";
475 status = "disabled"; 394 status = "disabled";
476 }; 395 };
477 396
478 main_i2c3: i2c@20030000 { 397 main_i2c3: i2c@20030000 {
479 compatible = "ti,am64-i2c", "t 398 compatible = "ti,am64-i2c", "ti,omap4-i2c";
480 reg = <0x00 0x20030000 0x00 0x 399 reg = <0x00 0x20030000 0x00 0x100>;
481 interrupts = <GIC_SPI 164 IRQ_ 400 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
482 #address-cells = <1>; 401 #address-cells = <1>;
483 #size-cells = <0>; 402 #size-cells = <0>;
484 power-domains = <&k3_pds 105 T 403 power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>;
485 clocks = <&k3_clks 105 2>; 404 clocks = <&k3_clks 105 2>;
486 clock-names = "fck"; 405 clock-names = "fck";
487 status = "disabled"; 406 status = "disabled";
488 }; 407 };
489 408
490 main_spi0: spi@20100000 { 409 main_spi0: spi@20100000 {
491 compatible = "ti,am654-mcspi", 410 compatible = "ti,am654-mcspi", "ti,omap4-mcspi";
492 reg = <0x00 0x20100000 0x00 0x 411 reg = <0x00 0x20100000 0x00 0x400>;
493 interrupts = <GIC_SPI 172 IRQ_ 412 interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
494 #address-cells = <1>; 413 #address-cells = <1>;
495 #size-cells = <0>; 414 #size-cells = <0>;
496 power-domains = <&k3_pds 141 T 415 power-domains = <&k3_pds 141 TI_SCI_PD_EXCLUSIVE>;
497 clocks = <&k3_clks 141 0>; 416 clocks = <&k3_clks 141 0>;
498 status = "disabled"; 417 status = "disabled";
499 }; 418 };
500 419
501 main_spi1: spi@20110000 { 420 main_spi1: spi@20110000 {
502 compatible = "ti,am654-mcspi", 421 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
503 reg = <0x00 0x20110000 0x00 0x 422 reg = <0x00 0x20110000 0x00 0x400>;
504 interrupts = <GIC_SPI 173 IRQ_ 423 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
505 #address-cells = <1>; 424 #address-cells = <1>;
506 #size-cells = <0>; 425 #size-cells = <0>;
507 power-domains = <&k3_pds 142 T 426 power-domains = <&k3_pds 142 TI_SCI_PD_EXCLUSIVE>;
508 clocks = <&k3_clks 142 0>; 427 clocks = <&k3_clks 142 0>;
509 status = "disabled"; 428 status = "disabled";
510 }; 429 };
511 430
512 main_spi2: spi@20120000 { 431 main_spi2: spi@20120000 {
513 compatible = "ti,am654-mcspi", 432 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
514 reg = <0x00 0x20120000 0x00 0x 433 reg = <0x00 0x20120000 0x00 0x400>;
515 interrupts = <GIC_SPI 174 IRQ_ 434 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
516 #address-cells = <1>; 435 #address-cells = <1>;
517 #size-cells = <0>; 436 #size-cells = <0>;
518 power-domains = <&k3_pds 143 T 437 power-domains = <&k3_pds 143 TI_SCI_PD_EXCLUSIVE>;
519 clocks = <&k3_clks 143 0>; 438 clocks = <&k3_clks 143 0>;
520 status = "disabled"; 439 status = "disabled";
521 }; 440 };
522 441
523 main_gpio_intr: interrupt-controller@a 442 main_gpio_intr: interrupt-controller@a00000 {
524 compatible = "ti,sci-intr"; 443 compatible = "ti,sci-intr";
525 reg = <0x00 0x00a00000 0x00 0x 444 reg = <0x00 0x00a00000 0x00 0x800>;
526 ti,intr-trigger-type = <1>; 445 ti,intr-trigger-type = <1>;
527 interrupt-controller; 446 interrupt-controller;
528 interrupt-parent = <&gic500>; 447 interrupt-parent = <&gic500>;
529 #interrupt-cells = <1>; 448 #interrupt-cells = <1>;
530 ti,sci = <&dmsc>; 449 ti,sci = <&dmsc>;
531 ti,sci-dev-id = <3>; 450 ti,sci-dev-id = <3>;
532 ti,interrupt-ranges = <0 32 16 451 ti,interrupt-ranges = <0 32 16>;
533 status = "disabled"; 452 status = "disabled";
534 }; 453 };
535 454
536 main_gpio0: gpio@600000 { 455 main_gpio0: gpio@600000 {
537 compatible = "ti,am64-gpio", " 456 compatible = "ti,am64-gpio", "ti,keystone-gpio";
538 reg = <0x00 0x00600000 0x0 0x1 457 reg = <0x00 0x00600000 0x0 0x100>;
539 gpio-controller; 458 gpio-controller;
540 #gpio-cells = <2>; 459 #gpio-cells = <2>;
541 interrupt-parent = <&main_gpio 460 interrupt-parent = <&main_gpio_intr>;
542 interrupts = <190>, <191>, <19 461 interrupts = <190>, <191>, <192>,
543 <193>, <194>, <19 462 <193>, <194>, <195>;
544 interrupt-controller; 463 interrupt-controller;
545 #interrupt-cells = <2>; 464 #interrupt-cells = <2>;
546 ti,ngpio = <92>; 465 ti,ngpio = <92>;
547 ti,davinci-gpio-unbanked = <0> 466 ti,davinci-gpio-unbanked = <0>;
548 power-domains = <&k3_pds 77 TI 467 power-domains = <&k3_pds 77 TI_SCI_PD_EXCLUSIVE>;
549 clocks = <&k3_clks 77 0>; 468 clocks = <&k3_clks 77 0>;
550 clock-names = "gpio"; 469 clock-names = "gpio";
551 status = "disabled"; 470 status = "disabled";
552 }; 471 };
553 472
554 main_gpio1: gpio@601000 { 473 main_gpio1: gpio@601000 {
555 compatible = "ti,am64-gpio", " 474 compatible = "ti,am64-gpio", "ti,keystone-gpio";
556 reg = <0x00 0x00601000 0x0 0x1 475 reg = <0x00 0x00601000 0x0 0x100>;
557 gpio-controller; 476 gpio-controller;
558 #gpio-cells = <2>; 477 #gpio-cells = <2>;
559 interrupt-parent = <&main_gpio 478 interrupt-parent = <&main_gpio_intr>;
560 interrupts = <180>, <181>, <18 479 interrupts = <180>, <181>, <182>,
561 <183>, <184>, <18 480 <183>, <184>, <185>;
562 interrupt-controller; 481 interrupt-controller;
563 #interrupt-cells = <2>; 482 #interrupt-cells = <2>;
564 ti,ngpio = <52>; 483 ti,ngpio = <52>;
565 ti,davinci-gpio-unbanked = <0> 484 ti,davinci-gpio-unbanked = <0>;
566 power-domains = <&k3_pds 78 TI 485 power-domains = <&k3_pds 78 TI_SCI_PD_EXCLUSIVE>;
567 clocks = <&k3_clks 78 0>; 486 clocks = <&k3_clks 78 0>;
568 clock-names = "gpio"; 487 clock-names = "gpio";
569 status = "disabled"; 488 status = "disabled";
570 }; 489 };
571 490
572 sdhci0: mmc@fa10000 { <<
573 compatible = "ti,am62-sdhci"; <<
574 reg = <0x00 0xfa10000 0x00 0x2 <<
575 interrupts = <GIC_SPI 133 IRQ_ <<
576 power-domains = <&k3_pds 57 TI <<
577 clocks = <&k3_clks 57 5>, <&k3 <<
578 clock-names = "clk_ahb", "clk_ <<
579 assigned-clocks = <&k3_clks 57 <<
580 assigned-clock-parents = <&k3_ <<
581 bus-width = <8>; <<
582 mmc-hs200-1_8v; <<
583 ti,clkbuf-sel = <0x7>; <<
584 ti,otap-del-sel-legacy = <0x0> <<
585 ti,otap-del-sel-mmc-hs = <0x0> <<
586 ti,otap-del-sel-hs200 = <0x6>; <<
587 status = "disabled"; <<
588 }; <<
589 <<
590 sdhci1: mmc@fa00000 { 491 sdhci1: mmc@fa00000 {
591 compatible = "ti,am62-sdhci"; 492 compatible = "ti,am62-sdhci";
592 reg = <0x00 0xfa00000 0x00 0x2 493 reg = <0x00 0xfa00000 0x00 0x260>, <0x00 0xfa08000 0x00 0x134>;
593 interrupts = <GIC_SPI 83 IRQ_T 494 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
594 power-domains = <&k3_pds 58 TI 495 power-domains = <&k3_pds 58 TI_SCI_PD_EXCLUSIVE>;
595 clocks = <&k3_clks 58 5>, <&k3 496 clocks = <&k3_clks 58 5>, <&k3_clks 58 6>;
596 clock-names = "clk_ahb", "clk_ 497 clock-names = "clk_ahb", "clk_xin";
597 bus-width = <4>; !! 498 ti,trm-icp = <0x2>;
598 ti,clkbuf-sel = <0x7>; <<
599 ti,otap-del-sel-legacy = <0x0> 499 ti,otap-del-sel-legacy = <0x0>;
600 ti,otap-del-sel-sd-hs = <0x0>; 500 ti,otap-del-sel-sd-hs = <0x0>;
601 ti,otap-del-sel-sdr12 = <0xf>; 501 ti,otap-del-sel-sdr12 = <0xf>;
602 ti,otap-del-sel-sdr25 = <0xf>; 502 ti,otap-del-sel-sdr25 = <0xf>;
603 ti,otap-del-sel-sdr50 = <0xc>; 503 ti,otap-del-sel-sdr50 = <0xc>;
604 ti,otap-del-sel-sdr104 = <0x6> 504 ti,otap-del-sel-sdr104 = <0x6>;
605 ti,otap-del-sel-ddr50 = <0x9>; 505 ti,otap-del-sel-ddr50 = <0x9>;
606 ti,itap-del-sel-legacy = <0x0> 506 ti,itap-del-sel-legacy = <0x0>;
607 ti,itap-del-sel-sd-hs = <0x0>; 507 ti,itap-del-sel-sd-hs = <0x0>;
608 ti,itap-del-sel-sdr12 = <0x0>; 508 ti,itap-del-sel-sdr12 = <0x0>;
609 ti,itap-del-sel-sdr25 = <0x0>; 509 ti,itap-del-sel-sdr25 = <0x0>;
610 status = "disabled"; <<
611 }; <<
612 <<
613 sdhci2: mmc@fa20000 { <<
614 compatible = "ti,am62-sdhci"; <<
615 reg = <0x00 0xfa20000 0x00 0x2 <<
616 interrupts = <GIC_SPI 82 IRQ_T <<
617 power-domains = <&k3_pds 184 T <<
618 clocks = <&k3_clks 184 5>, <&k <<
619 clock-names = "clk_ahb", "clk_ <<
620 bus-width = <4>; <<
621 ti,clkbuf-sel = <0x7>; 510 ti,clkbuf-sel = <0x7>;
622 ti,otap-del-sel-legacy = <0x0> !! 511 bus-width = <4>;
623 ti,otap-del-sel-sd-hs = <0x0>; !! 512 no-1-8-v;
624 ti,otap-del-sel-sdr12 = <0xf>; <<
625 ti,otap-del-sel-sdr25 = <0xf>; <<
626 ti,otap-del-sel-sdr50 = <0xc>; <<
627 ti,otap-del-sel-sdr104 = <0x6> <<
628 ti,otap-del-sel-ddr50 = <0x9>; <<
629 ti,itap-del-sel-legacy = <0x0> <<
630 ti,itap-del-sel-sd-hs = <0x0>; <<
631 ti,itap-del-sel-sdr12 = <0x0>; <<
632 ti,itap-del-sel-sdr25 = <0x0>; <<
633 status = "disabled"; 513 status = "disabled";
634 }; 514 };
635 515
636 usbss0: dwc3-usb@f900000 { 516 usbss0: dwc3-usb@f900000 {
637 compatible = "ti,am62-usb"; 517 compatible = "ti,am62-usb";
638 reg = <0x00 0x0f900000 0x00 0x !! 518 reg = <0x00 0x0f900000 0x00 0x800>;
639 <0x00 0x0f908000 0x00 0x <<
640 clocks = <&k3_clks 161 3>; 519 clocks = <&k3_clks 161 3>;
641 clock-names = "ref"; 520 clock-names = "ref";
642 ti,syscon-phy-pll-refclk = <&u !! 521 ti,syscon-phy-pll-refclk = <&wkup_conf 0x4008>;
643 #address-cells = <2>; 522 #address-cells = <2>;
644 #size-cells = <2>; 523 #size-cells = <2>;
645 power-domains = <&k3_pds 178 T 524 power-domains = <&k3_pds 178 TI_SCI_PD_EXCLUSIVE>;
646 ranges; 525 ranges;
647 status = "disabled"; 526 status = "disabled";
648 527
649 usb0: usb@31000000 { 528 usb0: usb@31000000 {
650 compatible = "snps,dwc 529 compatible = "snps,dwc3";
651 reg = <0x00 0x31000000 530 reg = <0x00 0x31000000 0x00 0x50000>;
652 interrupts = <GIC_SPI 531 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */
653 <GIC_SPI 532 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; /* irq.0 */
654 interrupt-names = "hos 533 interrupt-names = "host", "peripheral";
655 maximum-speed = "high- 534 maximum-speed = "high-speed";
656 dr_mode = "otg"; 535 dr_mode = "otg";
657 snps,usb2-gadget-lpm-d <<
658 snps,usb2-lpm-disable; <<
659 }; 536 };
660 }; 537 };
661 538
662 usbss1: dwc3-usb@f910000 { 539 usbss1: dwc3-usb@f910000 {
663 compatible = "ti,am62-usb"; 540 compatible = "ti,am62-usb";
664 reg = <0x00 0x0f910000 0x00 0x !! 541 reg = <0x00 0x0f910000 0x00 0x800>;
665 <0x00 0x0f918000 0x00 0x <<
666 clocks = <&k3_clks 162 3>; 542 clocks = <&k3_clks 162 3>;
667 clock-names = "ref"; 543 clock-names = "ref";
668 ti,syscon-phy-pll-refclk = <&u !! 544 ti,syscon-phy-pll-refclk = <&wkup_conf 0x4018>;
669 #address-cells = <2>; 545 #address-cells = <2>;
670 #size-cells = <2>; 546 #size-cells = <2>;
671 power-domains = <&k3_pds 179 T 547 power-domains = <&k3_pds 179 TI_SCI_PD_EXCLUSIVE>;
672 ranges; 548 ranges;
673 status = "disabled"; 549 status = "disabled";
674 550
675 usb1: usb@31100000 { 551 usb1: usb@31100000 {
676 compatible = "snps,dwc 552 compatible = "snps,dwc3";
677 reg = <0x00 0x31100000 553 reg = <0x00 0x31100000 0x00 0x50000>;
678 interrupts = <GIC_SPI 554 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */
679 <GIC_SPI 555 <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; /* irq.0 */
680 interrupt-names = "hos 556 interrupt-names = "host", "peripheral";
681 maximum-speed = "high- 557 maximum-speed = "high-speed";
682 dr_mode = "otg"; 558 dr_mode = "otg";
683 snps,usb2-gadget-lpm-d <<
684 snps,usb2-lpm-disable; <<
685 }; 559 };
686 }; 560 };
687 561
688 fss: bus@fc00000 { 562 fss: bus@fc00000 {
689 compatible = "simple-bus"; 563 compatible = "simple-bus";
690 reg = <0x00 0x0fc00000 0x00 0x 564 reg = <0x00 0x0fc00000 0x00 0x70000>;
691 #address-cells = <2>; 565 #address-cells = <2>;
692 #size-cells = <2>; 566 #size-cells = <2>;
693 ranges; 567 ranges;
694 status = "disabled"; 568 status = "disabled";
695 569
696 ospi0: spi@fc40000 { 570 ospi0: spi@fc40000 {
697 compatible = "ti,am654 571 compatible = "ti,am654-ospi", "cdns,qspi-nor";
698 reg = <0x00 0x0fc40000 572 reg = <0x00 0x0fc40000 0x00 0x100>,
699 <0x05 0x00000000 573 <0x05 0x00000000 0x01 0x00000000>;
700 interrupts = <GIC_SPI 574 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
701 cdns,fifo-depth = <256 575 cdns,fifo-depth = <256>;
702 cdns,fifo-width = <4>; 576 cdns,fifo-width = <4>;
703 cdns,trigger-address = 577 cdns,trigger-address = <0x0>;
704 clocks = <&k3_clks 75 578 clocks = <&k3_clks 75 7>;
705 assigned-clocks = <&k3 579 assigned-clocks = <&k3_clks 75 7>;
706 assigned-clock-parents 580 assigned-clock-parents = <&k3_clks 75 8>;
707 assigned-clock-rates = 581 assigned-clock-rates = <166666666>;
708 power-domains = <&k3_p 582 power-domains = <&k3_pds 75 TI_SCI_PD_EXCLUSIVE>;
709 #address-cells = <1>; 583 #address-cells = <1>;
710 #size-cells = <0>; 584 #size-cells = <0>;
711 }; 585 };
712 }; 586 };
713 587
714 cpsw3g: ethernet@8000000 { 588 cpsw3g: ethernet@8000000 {
715 compatible = "ti,am642-cpsw-nu 589 compatible = "ti,am642-cpsw-nuss";
716 #address-cells = <2>; 590 #address-cells = <2>;
717 #size-cells = <2>; 591 #size-cells = <2>;
718 reg = <0x0 0x8000000 0x0 0x200 592 reg = <0x0 0x8000000 0x0 0x200000>;
719 reg-names = "cpsw_nuss"; 593 reg-names = "cpsw_nuss";
720 ranges = <0x0 0x0 0x0 0x800000 594 ranges = <0x0 0x0 0x0 0x8000000 0x0 0x200000>;
721 clocks = <&k3_clks 13 0>; 595 clocks = <&k3_clks 13 0>;
722 assigned-clocks = <&k3_clks 13 596 assigned-clocks = <&k3_clks 13 3>;
723 assigned-clock-parents = <&k3_ 597 assigned-clock-parents = <&k3_clks 13 11>;
724 clock-names = "fck"; 598 clock-names = "fck";
725 power-domains = <&k3_pds 13 TI 599 power-domains = <&k3_pds 13 TI_SCI_PD_EXCLUSIVE>;
726 status = "disabled"; 600 status = "disabled";
727 601
728 dmas = <&main_pktdma 0xc600 15 602 dmas = <&main_pktdma 0xc600 15>,
729 <&main_pktdma 0xc601 15 603 <&main_pktdma 0xc601 15>,
730 <&main_pktdma 0xc602 15 604 <&main_pktdma 0xc602 15>,
731 <&main_pktdma 0xc603 15 605 <&main_pktdma 0xc603 15>,
732 <&main_pktdma 0xc604 15 606 <&main_pktdma 0xc604 15>,
733 <&main_pktdma 0xc605 15 607 <&main_pktdma 0xc605 15>,
734 <&main_pktdma 0xc606 15 608 <&main_pktdma 0xc606 15>,
735 <&main_pktdma 0xc607 15 609 <&main_pktdma 0xc607 15>,
736 <&main_pktdma 0x4600 15 610 <&main_pktdma 0x4600 15>;
737 dma-names = "tx0", "tx1", "tx2 611 dma-names = "tx0", "tx1", "tx2", "tx3", "tx4", "tx5", "tx6",
738 "tx7", "rx"; 612 "tx7", "rx";
739 613
740 ethernet-ports { 614 ethernet-ports {
741 #address-cells = <1>; 615 #address-cells = <1>;
742 #size-cells = <0>; 616 #size-cells = <0>;
743 617
744 cpsw_port1: port@1 { 618 cpsw_port1: port@1 {
745 reg = <1>; 619 reg = <1>;
746 ti,mac-only; 620 ti,mac-only;
747 label = "port1 621 label = "port1";
748 phys = <&phy_g 622 phys = <&phy_gmii_sel 1>;
749 mac-address = 623 mac-address = [00 00 00 00 00 00];
750 ti,syscon-efus !! 624 ti,syscon-efuse = <&wkup_conf 0x200>;
751 }; 625 };
752 626
753 cpsw_port2: port@2 { 627 cpsw_port2: port@2 {
754 reg = <2>; 628 reg = <2>;
755 ti,mac-only; 629 ti,mac-only;
756 label = "port2 630 label = "port2";
757 phys = <&phy_g 631 phys = <&phy_gmii_sel 2>;
758 mac-address = 632 mac-address = [00 00 00 00 00 00];
759 }; 633 };
760 }; 634 };
761 635
762 cpsw3g_mdio: mdio@f00 { 636 cpsw3g_mdio: mdio@f00 {
763 compatible = "ti,cpsw- 637 compatible = "ti,cpsw-mdio","ti,davinci_mdio";
764 reg = <0x0 0xf00 0x0 0 638 reg = <0x0 0xf00 0x0 0x100>;
765 #address-cells = <1>; 639 #address-cells = <1>;
766 #size-cells = <0>; 640 #size-cells = <0>;
767 clocks = <&k3_clks 13 641 clocks = <&k3_clks 13 0>;
768 clock-names = "fck"; 642 clock-names = "fck";
769 bus_freq = <1000000>; 643 bus_freq = <1000000>;
770 }; 644 };
771 645
772 cpts@3d000 { 646 cpts@3d000 {
773 compatible = "ti,j721e 647 compatible = "ti,j721e-cpts";
774 reg = <0x0 0x3d000 0x0 648 reg = <0x0 0x3d000 0x0 0x400>;
775 clocks = <&k3_clks 13 649 clocks = <&k3_clks 13 3>;
776 clock-names = "cpts"; 650 clock-names = "cpts";
777 interrupts-extended = 651 interrupts-extended = <&gic500 GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
778 interrupt-names = "cpt 652 interrupt-names = "cpts";
779 ti,cpts-ext-ts-inputs 653 ti,cpts-ext-ts-inputs = <4>;
780 ti,cpts-periodic-outpu 654 ti,cpts-periodic-outputs = <2>;
781 }; 655 };
782 }; 656 };
783 657
784 hwspinlock: spinlock@2a000000 { 658 hwspinlock: spinlock@2a000000 {
785 compatible = "ti,am64-hwspinlo 659 compatible = "ti,am64-hwspinlock";
786 reg = <0x00 0x2a000000 0x00 0x 660 reg = <0x00 0x2a000000 0x00 0x1000>;
787 #hwlock-cells = <1>; 661 #hwlock-cells = <1>;
788 }; 662 };
789 663
790 mailbox0_cluster0: mailbox@29000000 { 664 mailbox0_cluster0: mailbox@29000000 {
791 compatible = "ti,am64-mailbox" 665 compatible = "ti,am64-mailbox";
792 reg = <0x00 0x29000000 0x00 0x 666 reg = <0x00 0x29000000 0x00 0x200>;
793 interrupts = <GIC_SPI 76 IRQ_T 667 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
794 #mbox-cells = <1>; 668 #mbox-cells = <1>;
795 ti,mbox-num-users = <4>; 669 ti,mbox-num-users = <4>;
796 ti,mbox-num-fifos = <16>; 670 ti,mbox-num-fifos = <16>;
797 }; 671 };
798 672
799 mailbox0_cluster1: mailbox@29010000 { 673 mailbox0_cluster1: mailbox@29010000 {
800 compatible = "ti,am64-mailbox" 674 compatible = "ti,am64-mailbox";
801 reg = <0x00 0x29010000 0x00 0x 675 reg = <0x00 0x29010000 0x00 0x200>;
802 interrupts = <GIC_SPI 77 IRQ_T 676 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
803 #mbox-cells = <1>; 677 #mbox-cells = <1>;
804 ti,mbox-num-users = <4>; 678 ti,mbox-num-users = <4>;
805 ti,mbox-num-fifos = <16>; 679 ti,mbox-num-fifos = <16>;
806 }; 680 };
807 681
808 mailbox0_cluster2: mailbox@29020000 { 682 mailbox0_cluster2: mailbox@29020000 {
809 compatible = "ti,am64-mailbox" 683 compatible = "ti,am64-mailbox";
810 reg = <0x00 0x29020000 0x00 0x 684 reg = <0x00 0x29020000 0x00 0x200>;
811 interrupts = <GIC_SPI 108 IRQ_ 685 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
812 #mbox-cells = <1>; 686 #mbox-cells = <1>;
813 ti,mbox-num-users = <4>; 687 ti,mbox-num-users = <4>;
814 ti,mbox-num-fifos = <16>; 688 ti,mbox-num-fifos = <16>;
815 }; 689 };
816 690
817 mailbox0_cluster3: mailbox@29030000 { 691 mailbox0_cluster3: mailbox@29030000 {
818 compatible = "ti,am64-mailbox" 692 compatible = "ti,am64-mailbox";
819 reg = <0x00 0x29030000 0x00 0x 693 reg = <0x00 0x29030000 0x00 0x200>;
820 interrupts = <GIC_SPI 109 IRQ_ 694 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
821 #mbox-cells = <1>; 695 #mbox-cells = <1>;
822 ti,mbox-num-users = <4>; 696 ti,mbox-num-users = <4>;
823 ti,mbox-num-fifos = <16>; 697 ti,mbox-num-fifos = <16>;
824 }; 698 };
825 699
826 main_mcan0: can@20701000 { 700 main_mcan0: can@20701000 {
827 compatible = "bosch,m_can"; 701 compatible = "bosch,m_can";
828 reg = <0x00 0x20701000 0x00 0x 702 reg = <0x00 0x20701000 0x00 0x200>,
829 <0x00 0x20708000 0x00 0x 703 <0x00 0x20708000 0x00 0x8000>;
830 reg-names = "m_can", "message_ 704 reg-names = "m_can", "message_ram";
831 power-domains = <&k3_pds 98 TI 705 power-domains = <&k3_pds 98 TI_SCI_PD_EXCLUSIVE>;
832 clocks = <&k3_clks 98 6>, <&k3 706 clocks = <&k3_clks 98 6>, <&k3_clks 98 1>;
833 clock-names = "hclk", "cclk"; 707 clock-names = "hclk", "cclk";
834 interrupts = <GIC_SPI 155 IRQ_ 708 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
835 <GIC_SPI 156 IRQ_ 709 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
836 interrupt-names = "int0", "int 710 interrupt-names = "int0", "int1";
837 bosch,mram-cfg = <0x0 128 64 6 711 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
838 status = "disabled"; 712 status = "disabled";
839 }; 713 };
840 714
841 main_rti0: watchdog@e000000 { 715 main_rti0: watchdog@e000000 {
842 compatible = "ti,j7-rti-wdt"; 716 compatible = "ti,j7-rti-wdt";
843 reg = <0x00 0x0e000000 0x00 0x 717 reg = <0x00 0x0e000000 0x00 0x100>;
844 clocks = <&k3_clks 125 0>; 718 clocks = <&k3_clks 125 0>;
845 power-domains = <&k3_pds 125 T 719 power-domains = <&k3_pds 125 TI_SCI_PD_EXCLUSIVE>;
846 assigned-clocks = <&k3_clks 12 720 assigned-clocks = <&k3_clks 125 0>;
847 assigned-clock-parents = <&k3_ 721 assigned-clock-parents = <&k3_clks 125 2>;
848 }; 722 };
849 723
850 main_rti1: watchdog@e010000 { 724 main_rti1: watchdog@e010000 {
851 compatible = "ti,j7-rti-wdt"; 725 compatible = "ti,j7-rti-wdt";
852 reg = <0x00 0x0e010000 0x00 0x 726 reg = <0x00 0x0e010000 0x00 0x100>;
853 clocks = <&k3_clks 126 0>; 727 clocks = <&k3_clks 126 0>;
854 power-domains = <&k3_pds 126 T 728 power-domains = <&k3_pds 126 TI_SCI_PD_EXCLUSIVE>;
855 assigned-clocks = <&k3_clks 12 729 assigned-clocks = <&k3_clks 126 0>;
856 assigned-clock-parents = <&k3_ 730 assigned-clock-parents = <&k3_clks 126 2>;
857 }; 731 };
858 732
859 main_rti2: watchdog@e020000 { 733 main_rti2: watchdog@e020000 {
860 compatible = "ti,j7-rti-wdt"; 734 compatible = "ti,j7-rti-wdt";
861 reg = <0x00 0x0e020000 0x00 0x 735 reg = <0x00 0x0e020000 0x00 0x100>;
862 clocks = <&k3_clks 127 0>; 736 clocks = <&k3_clks 127 0>;
863 power-domains = <&k3_pds 127 T 737 power-domains = <&k3_pds 127 TI_SCI_PD_EXCLUSIVE>;
864 assigned-clocks = <&k3_clks 12 738 assigned-clocks = <&k3_clks 127 0>;
865 assigned-clock-parents = <&k3_ 739 assigned-clock-parents = <&k3_clks 127 2>;
866 }; 740 };
867 741
868 main_rti3: watchdog@e030000 { 742 main_rti3: watchdog@e030000 {
869 compatible = "ti,j7-rti-wdt"; 743 compatible = "ti,j7-rti-wdt";
870 reg = <0x00 0x0e030000 0x00 0x 744 reg = <0x00 0x0e030000 0x00 0x100>;
871 clocks = <&k3_clks 128 0>; 745 clocks = <&k3_clks 128 0>;
872 power-domains = <&k3_pds 128 T 746 power-domains = <&k3_pds 128 TI_SCI_PD_EXCLUSIVE>;
873 assigned-clocks = <&k3_clks 12 747 assigned-clocks = <&k3_clks 128 0>;
874 assigned-clock-parents = <&k3_ 748 assigned-clock-parents = <&k3_clks 128 2>;
875 }; 749 };
876 750
877 main_rti4: watchdog@e040000 { 751 main_rti4: watchdog@e040000 {
878 compatible = "ti,j7-rti-wdt"; 752 compatible = "ti,j7-rti-wdt";
879 reg = <0x00 0x0e040000 0x00 0x 753 reg = <0x00 0x0e040000 0x00 0x100>;
880 clocks = <&k3_clks 205 0>; 754 clocks = <&k3_clks 205 0>;
881 power-domains = <&k3_pds 205 T 755 power-domains = <&k3_pds 205 TI_SCI_PD_EXCLUSIVE>;
882 assigned-clocks = <&k3_clks 20 756 assigned-clocks = <&k3_clks 205 0>;
883 assigned-clock-parents = <&k3_ 757 assigned-clock-parents = <&k3_clks 205 2>;
884 }; 758 };
885 759
886 epwm0: pwm@23000000 { 760 epwm0: pwm@23000000 {
887 compatible = "ti,am64-epwm", " 761 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm";
888 #pwm-cells = <3>; 762 #pwm-cells = <3>;
889 reg = <0x00 0x23000000 0x00 0x 763 reg = <0x00 0x23000000 0x00 0x100>;
890 power-domains = <&k3_pds 86 TI 764 power-domains = <&k3_pds 86 TI_SCI_PD_EXCLUSIVE>;
891 clocks = <&epwm_tbclk 0>, <&k3 765 clocks = <&epwm_tbclk 0>, <&k3_clks 86 0>;
892 clock-names = "tbclk", "fck"; 766 clock-names = "tbclk", "fck";
893 status = "disabled"; 767 status = "disabled";
894 }; 768 };
895 769
896 epwm1: pwm@23010000 { 770 epwm1: pwm@23010000 {
897 compatible = "ti,am64-epwm", " 771 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm";
898 #pwm-cells = <3>; 772 #pwm-cells = <3>;
899 reg = <0x00 0x23010000 0x00 0x 773 reg = <0x00 0x23010000 0x00 0x100>;
900 power-domains = <&k3_pds 87 TI 774 power-domains = <&k3_pds 87 TI_SCI_PD_EXCLUSIVE>;
901 clocks = <&epwm_tbclk 1>, <&k3 775 clocks = <&epwm_tbclk 1>, <&k3_clks 87 0>;
902 clock-names = "tbclk", "fck"; 776 clock-names = "tbclk", "fck";
903 status = "disabled"; 777 status = "disabled";
904 }; 778 };
905 779
906 epwm2: pwm@23020000 { 780 epwm2: pwm@23020000 {
907 compatible = "ti,am64-epwm", " 781 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm";
908 #pwm-cells = <3>; 782 #pwm-cells = <3>;
909 reg = <0x00 0x23020000 0x00 0x 783 reg = <0x00 0x23020000 0x00 0x100>;
910 power-domains = <&k3_pds 88 TI 784 power-domains = <&k3_pds 88 TI_SCI_PD_EXCLUSIVE>;
911 clocks = <&epwm_tbclk 2>, <&k3 785 clocks = <&epwm_tbclk 2>, <&k3_clks 88 0>;
912 clock-names = "tbclk", "fck"; 786 clock-names = "tbclk", "fck";
913 status = "disabled"; 787 status = "disabled";
914 }; 788 };
915 789
916 ecap0: pwm@23100000 { 790 ecap0: pwm@23100000 {
917 compatible = "ti,am3352-ecap"; 791 compatible = "ti,am3352-ecap";
918 #pwm-cells = <3>; 792 #pwm-cells = <3>;
919 reg = <0x00 0x23100000 0x00 0x 793 reg = <0x00 0x23100000 0x00 0x100>;
920 power-domains = <&k3_pds 51 TI 794 power-domains = <&k3_pds 51 TI_SCI_PD_EXCLUSIVE>;
921 clocks = <&k3_clks 51 0>; 795 clocks = <&k3_clks 51 0>;
922 clock-names = "fck"; 796 clock-names = "fck";
923 status = "disabled"; 797 status = "disabled";
924 }; 798 };
925 799
926 ecap1: pwm@23110000 { 800 ecap1: pwm@23110000 {
927 compatible = "ti,am3352-ecap"; 801 compatible = "ti,am3352-ecap";
928 #pwm-cells = <3>; 802 #pwm-cells = <3>;
929 reg = <0x00 0x23110000 0x00 0x 803 reg = <0x00 0x23110000 0x00 0x100>;
930 power-domains = <&k3_pds 52 TI 804 power-domains = <&k3_pds 52 TI_SCI_PD_EXCLUSIVE>;
931 clocks = <&k3_clks 52 0>; 805 clocks = <&k3_clks 52 0>;
932 clock-names = "fck"; 806 clock-names = "fck";
933 status = "disabled"; 807 status = "disabled";
934 }; 808 };
935 809
936 ecap2: pwm@23120000 { 810 ecap2: pwm@23120000 {
937 compatible = "ti,am3352-ecap"; 811 compatible = "ti,am3352-ecap";
938 #pwm-cells = <3>; 812 #pwm-cells = <3>;
939 reg = <0x00 0x23120000 0x00 0x 813 reg = <0x00 0x23120000 0x00 0x100>;
940 power-domains = <&k3_pds 53 TI 814 power-domains = <&k3_pds 53 TI_SCI_PD_EXCLUSIVE>;
941 clocks = <&k3_clks 53 0>; 815 clocks = <&k3_clks 53 0>;
942 clock-names = "fck"; 816 clock-names = "fck";
943 status = "disabled"; 817 status = "disabled";
944 }; <<
945 <<
946 mcasp0: audio-controller@2b00000 { <<
947 compatible = "ti,am33xx-mcasp- <<
948 reg = <0x00 0x02b00000 0x00 0x <<
949 <0x00 0x02b08000 0x00 0x <<
950 reg-names = "mpu", "dat"; <<
951 interrupts = <GIC_SPI 236 IRQ_ <<
952 <GIC_SPI 235 IRQ_ <<
953 interrupt-names = "tx", "rx"; <<
954 <<
955 dmas = <&main_bcdma 0 0xc500 0 <<
956 dma-names = "tx", "rx"; <<
957 <<
958 clocks = <&k3_clks 190 0>; <<
959 clock-names = "fck"; <<
960 assigned-clocks = <&k3_clks 19 <<
961 assigned-clock-parents = <&k3_ <<
962 power-domains = <&k3_pds 190 T <<
963 status = "disabled"; <<
964 }; <<
965 <<
966 mcasp1: audio-controller@2b10000 { <<
967 compatible = "ti,am33xx-mcasp- <<
968 reg = <0x00 0x02b10000 0x00 0x <<
969 <0x00 0x02b18000 0x00 0x <<
970 reg-names = "mpu", "dat"; <<
971 interrupts = <GIC_SPI 238 IRQ_ <<
972 <GIC_SPI 237 IRQ_ <<
973 interrupt-names = "tx", "rx"; <<
974 <<
975 dmas = <&main_bcdma 0 0xc501 0 <<
976 dma-names = "tx", "rx"; <<
977 <<
978 clocks = <&k3_clks 191 0>; <<
979 clock-names = "fck"; <<
980 assigned-clocks = <&k3_clks 19 <<
981 assigned-clock-parents = <&k3_ <<
982 power-domains = <&k3_pds 191 T <<
983 status = "disabled"; <<
984 }; <<
985 <<
986 mcasp2: audio-controller@2b20000 { <<
987 compatible = "ti,am33xx-mcasp- <<
988 reg = <0x00 0x02b20000 0x00 0x <<
989 <0x00 0x02b28000 0x00 0x <<
990 reg-names = "mpu", "dat"; <<
991 interrupts = <GIC_SPI 240 IRQ_ <<
992 <GIC_SPI 239 IRQ_ <<
993 interrupt-names = "tx", "rx"; <<
994 <<
995 dmas = <&main_bcdma 0 0xc502 0 <<
996 dma-names = "tx", "rx"; <<
997 <<
998 clocks = <&k3_clks 192 0>; <<
999 clock-names = "fck"; <<
1000 assigned-clocks = <&k3_clks 1 <<
1001 assigned-clock-parents = <&k3 <<
1002 power-domains = <&k3_pds 192 <<
1003 status = "disabled"; <<
1004 }; <<
1005 <<
1006 ti_csi2rx0: ticsi2rx@30102000 { <<
1007 compatible = "ti,j721e-csi2rx <<
1008 dmas = <&main_bcdma_csi 0 0x5 <<
1009 dma-names = "rx0"; <<
1010 reg = <0x00 0x30102000 0x00 0 <<
1011 power-domains = <&k3_pds 182 <<
1012 #address-cells = <2>; <<
1013 #size-cells = <2>; <<
1014 ranges; <<
1015 status = "disabled"; <<
1016 <<
1017 cdns_csi2rx0: csi-bridge@3010 <<
1018 compatible = "ti,j721 <<
1019 reg = <0x00 0x3010100 <<
1020 clocks = <&k3_clks 18 <<
1021 <&k3_clks 182 <<
1022 clock-names = "sys_cl <<
1023 "pixel_if1_cl <<
1024 phys = <&dphy0>; <<
1025 phy-names = "dphy"; <<
1026 <<
1027 ports { <<
1028 #address-cell <<
1029 #size-cells = <<
1030 <<
1031 csi0_port0: p <<
1032 reg = <<
1033 statu <<
1034 }; <<
1035 <<
1036 csi0_port1: p <<
1037 reg = <<
1038 statu <<
1039 }; <<
1040 <<
1041 csi0_port2: p <<
1042 reg = <<
1043 statu <<
1044 }; <<
1045 <<
1046 csi0_port3: p <<
1047 reg = <<
1048 statu <<
1049 }; <<
1050 <<
1051 csi0_port4: p <<
1052 reg = <<
1053 statu <<
1054 }; <<
1055 }; <<
1056 }; <<
1057 }; <<
1058 <<
1059 dphy0: phy@30110000 { <<
1060 compatible = "cdns,dphy-rx"; <<
1061 reg = <0x00 0x30110000 0x00 0 <<
1062 #phy-cells = <0>; <<
1063 power-domains = <&k3_pds 185 <<
1064 status = "disabled"; <<
1065 }; <<
1066 <<
1067 dss: dss@30200000 { <<
1068 compatible = "ti,am62a7-dss"; <<
1069 reg = <0x00 0x30200000 0x00 0 <<
1070 <0x00 0x30202000 0x00 0 <<
1071 <0x00 0x30206000 0x00 0 <<
1072 <0x00 0x30207000 0x00 0 <<
1073 <0x00 0x30208000 0x00 0 <<
1074 <0x00 0x3020a000 0x00 0 <<
1075 <0x00 0x3020b000 0x00 0 <<
1076 <0x00 0x30201000 0x00 0 <<
1077 reg-names = "common", "vidl1" <<
1078 "ovr1", "ovr2", " <<
1079 power-domains = <&k3_pds 186 <<
1080 clocks = <&k3_clks 186 6>, <<
1081 <&k3_clks 186 0>, <<
1082 <&k3_clks 186 2>; <<
1083 clock-names = "fck", "vp1", " <<
1084 interrupts = <GIC_SPI 84 IRQ_ <<
1085 status = "disabled"; <<
1086 <<
1087 dss_ports: ports { <<
1088 #address-cells = <1>; <<
1089 #size-cells = <0>; <<
1090 }; <<
1091 }; <<
1092 <<
1093 vpu: video-codec@30210000 { <<
1094 compatible = "ti,j721s2-wave5 <<
1095 reg = <0x00 0x30210000 0x00 0 <<
1096 clocks = <&k3_clks 204 2>; <<
1097 power-domains = <&k3_pds 204 <<
1098 }; <<
1099 <<
1100 e5010: jpeg-encoder@fd20000 { <<
1101 compatible = "ti,am62a-jpeg-e <<
1102 reg = <0x00 0xfd20000 0x00 0x <<
1103 <0x00 0xfd20200 0x00 0x <<
1104 reg-names = "core", "mmu"; <<
1105 clocks = <&k3_clks 201 0>; <<
1106 power-domains = <&k3_pds 201 <<
1107 interrupts = <GIC_SPI 98 IRQ_ <<
1108 }; 818 };
1109 }; 819 };
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