1 // SPDX-License-Identifier: GPL-2.0-only OR MI
2 /*
3 * Device Tree file for the MAIN domain periph
4 *
5 * Copyright (C) 2023-2024 Texas Instruments I
6 */
7
8 &cbass_main {
9 oc_sram: sram@70000000 {
10 compatible = "mmio-sram";
11 #address-cells = <1>;
12 #size-cells = <1>;
13 };
14
15 gic500: interrupt-controller@1800000 {
16 compatible = "arm,gic-v3";
17 #address-cells = <2>;
18 #size-cells = <2>;
19 ranges;
20 #interrupt-cells = <3>;
21 interrupt-controller;
22 reg = <0x00 0x01800000 0x00 0x
23 <0x00 0x01880000 0x00 0x
24 <0x01 0x00000000 0x00 0x
25 <0x01 0x00010000 0x00 0x
26 <0x01 0x00020000 0x00 0x
27 /*
28 * vcpumntirq:
29 * virtual CPU interface maint
30 */
31 interrupts = <GIC_PPI 9 IRQ_TY
32
33 gic_its: msi-controller@182000
34 compatible = "arm,gic-
35 reg = <0x00 0x01820000
36 socionext,synquacer-pr
37 msi-controller;
38 #msi-cells = <1>;
39 };
40 };
41
42 main_conf: bus@100000 {
43 compatible = "simple-bus";
44 reg = <0x00 0x00100000 0x00 0x
45 #address-cells = <1>;
46 #size-cells = <1>;
47 ranges = <0x00 0x00 0x00100000
48
49 phy_gmii_sel: phy@4044 {
50 compatible = "ti,am654
51 reg = <0x4044 0x8>;
52 #phy-cells = <1>;
53 };
54
55 epwm_tbclk: clock-controller@4
56 compatible = "ti,am62-
57 reg = <0x4130 0x4>;
58 #clock-cells = <1>;
59 };
60 };
61
62 dmss: bus@48000000 {
63 compatible = "simple-bus";
64 #address-cells = <2>;
65 #size-cells = <2>;
66 dma-ranges;
67 ranges = <0x00 0x48000000 0x00
68 bootph-all;
69
70 ti,sci-dev-id = <25>;
71
72 secure_proxy_main: mailbox@4d0
73 compatible = "ti,am654
74 #mbox-cells = <1>;
75 reg-names = "target_da
76 reg = <0x00 0x4d000000
77 <0x00 0x4a600000
78 <0x00 0x4a400000
79 interrupt-names = "rx_
80 interrupts = <GIC_SPI
81 bootph-all;
82 };
83
84 inta_main_dmss: interrupt-cont
85 compatible = "ti,sci-i
86 reg = <0x00 0x48000000
87 #interrupt-cells = <0>
88 interrupt-controller;
89 interrupt-parent = <&g
90 msi-controller;
91 ti,sci = <&dmsc>;
92 ti,sci-dev-id = <28>;
93 ti,unmapped-event-sour
94 };
95
96 main_bcdma: dma-controller@485
97 compatible = "ti,am64-
98 reg = <0x00 0x485c0100
99 <0x00 0x4c000000
100 <0x00 0x4a820000
101 <0x00 0x4aa40000
102 <0x00 0x4bc00000
103 <0x00 0x48600000
104 <0x00 0x484a4000
105 <0x00 0x484c2000
106 <0x00 0x48420000
107 reg-names = "gcfg", "b
108 "ring", "t
109 msi-parent = <&inta_ma
110 #dma-cells = <3>;
111
112 ti,sci = <&dmsc>;
113 ti,sci-dev-id = <26>;
114 ti,sci-rm-range-bchan
115 ti,sci-rm-range-rchan
116 ti,sci-rm-range-tchan
117 bootph-all;
118 };
119
120 main_pktdma: dma-controller@48
121 compatible = "ti,am64-
122 reg = <0x00 0x485c0000
123 <0x00 0x4a800000
124 <0x00 0x4aa00000
125 <0x00 0x4b800000
126 <0x00 0x485e0000
127 <0x00 0x484a0000
128 <0x00 0x484c0000
129 <0x00 0x48430000
130 reg-names = "gcfg", "r
131 "ring", "t
132 msi-parent = <&inta_ma
133 #dma-cells = <2>;
134 bootph-all;
135
136 ti,sci = <&dmsc>;
137 ti,sci-dev-id = <30>;
138 ti,sci-rm-range-tchan
139
140
141
142 ti,sci-rm-range-tflow
143
144
145
146 ti,sci-rm-range-rchan
147
148
149
150
151
152 ti,sci-rm-range-rflow
153
154
155
156 };
157 };
158
159 dmss_csi: bus@4e000000 {
160 compatible = "simple-bus";
161 ranges = <0x00 0x4e000000 0x00
162 #address-cells = <2>;
163 #size-cells = <2>;
164 dma-ranges;
165 ti,sci-dev-id = <198>;
166
167 inta_main_dmss_csi: interrupt-
168 compatible = "ti,sci-i
169 reg = <0x00 0x4e400000
170 #interrupt-cells = <0>
171 interrupt-controller;
172 interrupt-parent = <&g
173 msi-controller;
174 power-domains = <&k3_p
175 ti,sci = <&dmsc>;
176 ti,sci-dev-id = <200>;
177 ti,interrupt-ranges =
178 ti,unmapped-event-sour
179 };
180
181 main_bcdma_csi: dma-controller
182 compatible = "ti,am62a
183 reg = <0x00 0x4e230000
184 <0x00 0x4e180000
185 <0x00 0x4e100000
186 reg-names = "gcfg", "r
187 #dma-cells = <3>;
188 msi-parent = <&inta_ma
189 power-domains = <&k3_p
190 ti,sci = <&dmsc>;
191 ti,sci-dev-id = <199>;
192 ti,sci-rm-range-rchan
193 };
194 };
195
196 dmsc: system-controller@44043000 {
197 compatible = "ti,k2g-sci";
198 ti,host-id = <12>;
199 mbox-names = "rx", "tx";
200 mboxes = <&secure_proxy_main 1
201 <&secure_proxy_main 1
202 reg-names = "debug_messages";
203 reg = <0x00 0x44043000 0x00 0x
204 bootph-all;
205
206 k3_pds: power-controller {
207 compatible = "ti,sci-p
208 #power-domain-cells =
209 bootph-all;
210 };
211
212 k3_clks: clock-controller {
213 compatible = "ti,k2g-s
214 #clock-cells = <2>;
215 bootph-all;
216 };
217
218 k3_reset: reset-controller {
219 compatible = "ti,sci-r
220 #reset-cells = <2>;
221 bootph-all;
222 };
223 };
224
225 crypto: crypto@40900000 {
226 compatible = "ti,am62-sa3ul";
227 reg = <0x00 0x40900000 0x00 0x
228 #address-cells = <2>;
229 #size-cells = <2>;
230 dmas = <&main_pktdma 0xf501 0>
231 <&main_pktdma 0x7507 0>
232 dma-names = "tx", "rx1", "rx2"
233 };
234
235 secure_proxy_sa3: mailbox@43600000 {
236 compatible = "ti,am654-secure-
237 #mbox-cells = <1>;
238 reg-names = "target_data", "rt
239 reg = <0x00 0x43600000 0x00 0x
240 <0x00 0x44880000 0x00 0x
241 <0x00 0x44860000 0x00 0x
242 /*
243 * Marked Disabled:
244 * Node is incomplete as it is
245 * firmware on non-MPU process
246 */
247 status = "disabled";
248 bootph-all;
249 };
250
251 main_pmx0: pinctrl@f4000 {
252 compatible = "pinctrl-single";
253 reg = <0x00 0xf4000 0x00 0x2ac
254 #pinctrl-cells = <1>;
255 pinctrl-single,register-width
256 pinctrl-single,function-mask =
257 bootph-all;
258 };
259
260 main_esm: esm@420000 {
261 compatible = "ti,j721e-esm";
262 reg = <0x00 0x420000 0x00 0x10
263 bootph-pre-ram;
264 /* Interrupt sources: rti0, rt
265 ti,esm-pins = <224>, <225>, <2
266 };
267
268 main_timer0: timer@2400000 {
269 compatible = "ti,am654-timer";
270 reg = <0x00 0x2400000 0x00 0x4
271 interrupts = <GIC_SPI 120 IRQ_
272 clocks = <&k3_clks 36 2>;
273 clock-names = "fck";
274 assigned-clocks = <&k3_clks 36
275 assigned-clock-parents = <&k3_
276 power-domains = <&k3_pds 36 TI
277 ti,timer-pwm;
278 bootph-all;
279 };
280
281 main_timer1: timer@2410000 {
282 compatible = "ti,am654-timer";
283 reg = <0x00 0x2410000 0x00 0x4
284 interrupts = <GIC_SPI 121 IRQ_
285 clocks = <&k3_clks 37 2>;
286 clock-names = "fck";
287 assigned-clocks = <&k3_clks 37
288 assigned-clock-parents = <&k3_
289 power-domains = <&k3_pds 37 TI
290 ti,timer-pwm;
291 };
292
293 main_timer2: timer@2420000 {
294 compatible = "ti,am654-timer";
295 reg = <0x00 0x2420000 0x00 0x4
296 interrupts = <GIC_SPI 122 IRQ_
297 clocks = <&k3_clks 38 2>;
298 clock-names = "fck";
299 assigned-clocks = <&k3_clks 38
300 assigned-clock-parents = <&k3_
301 power-domains = <&k3_pds 38 TI
302 ti,timer-pwm;
303 };
304
305 main_timer3: timer@2430000 {
306 compatible = "ti,am654-timer";
307 reg = <0x00 0x2430000 0x00 0x4
308 interrupts = <GIC_SPI 123 IRQ_
309 clocks = <&k3_clks 39 2>;
310 clock-names = "fck";
311 assigned-clocks = <&k3_clks 39
312 assigned-clock-parents = <&k3_
313 power-domains = <&k3_pds 39 TI
314 ti,timer-pwm;
315 };
316
317 main_timer4: timer@2440000 {
318 compatible = "ti,am654-timer";
319 reg = <0x00 0x2440000 0x00 0x4
320 interrupts = <GIC_SPI 124 IRQ_
321 clocks = <&k3_clks 40 2>;
322 clock-names = "fck";
323 assigned-clocks = <&k3_clks 40
324 assigned-clock-parents = <&k3_
325 power-domains = <&k3_pds 40 TI
326 ti,timer-pwm;
327 };
328
329 main_timer5: timer@2450000 {
330 compatible = "ti,am654-timer";
331 reg = <0x00 0x2450000 0x00 0x4
332 interrupts = <GIC_SPI 125 IRQ_
333 clocks = <&k3_clks 41 2>;
334 clock-names = "fck";
335 assigned-clocks = <&k3_clks 41
336 assigned-clock-parents = <&k3_
337 power-domains = <&k3_pds 41 TI
338 ti,timer-pwm;
339 };
340
341 main_timer6: timer@2460000 {
342 compatible = "ti,am654-timer";
343 reg = <0x00 0x2460000 0x00 0x4
344 interrupts = <GIC_SPI 126 IRQ_
345 clocks = <&k3_clks 42 2>;
346 clock-names = "fck";
347 assigned-clocks = <&k3_clks 42
348 assigned-clock-parents = <&k3_
349 power-domains = <&k3_pds 42 TI
350 ti,timer-pwm;
351 };
352
353 main_timer7: timer@2470000 {
354 compatible = "ti,am654-timer";
355 reg = <0x00 0x2470000 0x00 0x4
356 interrupts = <GIC_SPI 127 IRQ_
357 clocks = <&k3_clks 43 2>;
358 clock-names = "fck";
359 assigned-clocks = <&k3_clks 43
360 assigned-clock-parents = <&k3_
361 power-domains = <&k3_pds 43 TI
362 ti,timer-pwm;
363 };
364
365 main_uart0: serial@2800000 {
366 compatible = "ti,am64-uart", "
367 reg = <0x00 0x02800000 0x00 0x
368 interrupts = <GIC_SPI 178 IRQ_
369 power-domains = <&k3_pds 146 T
370 clocks = <&k3_clks 146 0>;
371 clock-names = "fclk";
372 status = "disabled";
373 };
374
375 main_uart1: serial@2810000 {
376 compatible = "ti,am64-uart", "
377 reg = <0x00 0x02810000 0x00 0x
378 interrupts = <GIC_SPI 179 IRQ_
379 power-domains = <&k3_pds 152 T
380 clocks = <&k3_clks 152 0>;
381 clock-names = "fclk";
382 status = "disabled";
383 };
384
385 main_uart2: serial@2820000 {
386 compatible = "ti,am64-uart", "
387 reg = <0x00 0x02820000 0x00 0x
388 interrupts = <GIC_SPI 180 IRQ_
389 power-domains = <&k3_pds 153 T
390 clocks = <&k3_clks 153 0>;
391 clock-names = "fclk";
392 status = "disabled";
393 };
394
395 main_uart3: serial@2830000 {
396 compatible = "ti,am64-uart", "
397 reg = <0x00 0x02830000 0x00 0x
398 interrupts = <GIC_SPI 181 IRQ_
399 power-domains = <&k3_pds 154 T
400 clocks = <&k3_clks 154 0>;
401 clock-names = "fclk";
402 status = "disabled";
403 };
404
405 main_uart4: serial@2840000 {
406 compatible = "ti,am64-uart", "
407 reg = <0x00 0x02840000 0x00 0x
408 interrupts = <GIC_SPI 182 IRQ_
409 power-domains = <&k3_pds 155 T
410 clocks = <&k3_clks 155 0>;
411 clock-names = "fclk";
412 status = "disabled";
413 };
414
415 main_uart5: serial@2850000 {
416 compatible = "ti,am64-uart", "
417 reg = <0x00 0x02850000 0x00 0x
418 interrupts = <GIC_SPI 183 IRQ_
419 power-domains = <&k3_pds 156 T
420 clocks = <&k3_clks 156 0>;
421 clock-names = "fclk";
422 status = "disabled";
423 };
424
425 main_uart6: serial@2860000 {
426 compatible = "ti,am64-uart", "
427 reg = <0x00 0x02860000 0x00 0x
428 interrupts = <GIC_SPI 184 IRQ_
429 power-domains = <&k3_pds 158 T
430 clocks = <&k3_clks 158 0>;
431 clock-names = "fclk";
432 status = "disabled";
433 };
434
435 main_i2c0: i2c@20000000 {
436 compatible = "ti,am64-i2c", "t
437 reg = <0x00 0x20000000 0x00 0x
438 interrupts = <GIC_SPI 161 IRQ_
439 #address-cells = <1>;
440 #size-cells = <0>;
441 power-domains = <&k3_pds 102 T
442 clocks = <&k3_clks 102 2>;
443 clock-names = "fck";
444 status = "disabled";
445 };
446
447 main_i2c1: i2c@20010000 {
448 compatible = "ti,am64-i2c", "t
449 reg = <0x00 0x20010000 0x00 0x
450 interrupts = <GIC_SPI 162 IRQ_
451 #address-cells = <1>;
452 #size-cells = <0>;
453 power-domains = <&k3_pds 103 T
454 clocks = <&k3_clks 103 2>;
455 clock-names = "fck";
456 status = "disabled";
457 };
458
459 main_i2c2: i2c@20020000 {
460 compatible = "ti,am64-i2c", "t
461 reg = <0x00 0x20020000 0x00 0x
462 interrupts = <GIC_SPI 163 IRQ_
463 #address-cells = <1>;
464 #size-cells = <0>;
465 power-domains = <&k3_pds 104 T
466 clocks = <&k3_clks 104 2>;
467 clock-names = "fck";
468 status = "disabled";
469 };
470
471 main_i2c3: i2c@20030000 {
472 compatible = "ti,am64-i2c", "t
473 reg = <0x00 0x20030000 0x00 0x
474 interrupts = <GIC_SPI 164 IRQ_
475 #address-cells = <1>;
476 #size-cells = <0>;
477 power-domains = <&k3_pds 105 T
478 clocks = <&k3_clks 105 2>;
479 clock-names = "fck";
480 status = "disabled";
481 };
482
483 main_spi0: spi@20100000 {
484 compatible = "ti,am654-mcspi",
485 reg = <0x00 0x20100000 0x00 0x
486 interrupts = <GIC_SPI 172 IRQ_
487 #address-cells = <1>;
488 #size-cells = <0>;
489 power-domains = <&k3_pds 141 T
490 clocks = <&k3_clks 141 0>;
491 status = "disabled";
492 };
493
494 main_spi1: spi@20110000 {
495 compatible = "ti,am654-mcspi",
496 reg = <0x00 0x20110000 0x00 0x
497 interrupts = <GIC_SPI 173 IRQ_
498 #address-cells = <1>;
499 #size-cells = <0>;
500 power-domains = <&k3_pds 142 T
501 clocks = <&k3_clks 142 0>;
502 status = "disabled";
503 };
504
505 main_spi2: spi@20120000 {
506 compatible = "ti,am654-mcspi",
507 reg = <0x00 0x20120000 0x00 0x
508 interrupts = <GIC_SPI 174 IRQ_
509 #address-cells = <1>;
510 #size-cells = <0>;
511 power-domains = <&k3_pds 143 T
512 clocks = <&k3_clks 143 0>;
513 status = "disabled";
514 };
515
516 main_gpio_intr: interrupt-controller@a
517 compatible = "ti,sci-intr";
518 reg = <0x00 0x00a00000 0x00 0x
519 ti,intr-trigger-type = <1>;
520 interrupt-controller;
521 interrupt-parent = <&gic500>;
522 #interrupt-cells = <1>;
523 ti,sci = <&dmsc>;
524 ti,sci-dev-id = <3>;
525 ti,interrupt-ranges = <0 32 16
526 };
527
528 main_gpio0: gpio@600000 {
529 compatible = "ti,am64-gpio", "
530 reg = <0x00 0x00600000 0x00 0x
531 gpio-controller;
532 #gpio-cells = <2>;
533 interrupt-parent = <&main_gpio
534 interrupts = <190>, <191>, <19
535 <193>, <194>, <19
536 interrupt-controller;
537 #interrupt-cells = <2>;
538 ti,davinci-gpio-unbanked = <0>
539 power-domains = <&k3_pds 77 TI
540 clocks = <&k3_clks 77 0>;
541 clock-names = "gpio";
542 };
543
544 main_gpio1: gpio@601000 {
545 compatible = "ti,am64-gpio", "
546 reg = <0x00 0x00601000 0x00 0x
547 gpio-controller;
548 #gpio-cells = <2>;
549 interrupt-parent = <&main_gpio
550 interrupts = <180>, <181>, <18
551 <183>, <184>, <18
552 interrupt-controller;
553 #interrupt-cells = <2>;
554 ti,davinci-gpio-unbanked = <0>
555 power-domains = <&k3_pds 78 TI
556 clocks = <&k3_clks 78 0>;
557 clock-names = "gpio";
558 };
559
560 sdhci0: mmc@fa10000 {
561 compatible = "ti,am64-sdhci-8b
562 reg = <0x00 0x0fa10000 0x00 0x
563 interrupts = <GIC_SPI 133 IRQ_
564 power-domains = <&k3_pds 57 TI
565 clocks = <&k3_clks 57 1>, <&k3
566 clock-names = "clk_ahb", "clk_
567 assigned-clocks = <&k3_clks 57
568 assigned-clock-parents = <&k3_
569 bus-width = <8>;
570 mmc-ddr-1_8v;
571 mmc-hs200-1_8v;
572 mmc-hs400-1_8v;
573 ti,clkbuf-sel = <0x7>;
574 ti,strobe-sel = <0x77>;
575 ti,trm-icp = <0x8>;
576 ti,otap-del-sel-legacy = <0x1>
577 ti,otap-del-sel-mmc-hs = <0x1>
578 ti,otap-del-sel-ddr52 = <0x6>;
579 ti,otap-del-sel-hs200 = <0x8>;
580 ti,otap-del-sel-hs400 = <0x5>;
581 ti,itap-del-sel-legacy = <0x10
582 ti,itap-del-sel-mmc-hs = <0xa>
583 ti,itap-del-sel-ddr52 = <0x3>;
584 status = "disabled";
585 };
586
587 sdhci1: mmc@fa00000 {
588 compatible = "ti,am62-sdhci";
589 reg = <0x00 0x0fa00000 0x00 0x
590 interrupts = <GIC_SPI 83 IRQ_T
591 power-domains = <&k3_pds 58 TI
592 clocks = <&k3_clks 58 5>, <&k3
593 clock-names = "clk_ahb", "clk_
594 bus-width = <4>;
595 ti,clkbuf-sel = <0x7>;
596 ti,otap-del-sel-legacy = <0x0>
597 ti,otap-del-sel-sd-hs = <0x0>;
598 ti,otap-del-sel-sdr12 = <0xf>;
599 ti,otap-del-sel-sdr25 = <0xf>;
600 ti,otap-del-sel-sdr50 = <0xc>;
601 ti,otap-del-sel-ddr50 = <0x9>;
602 ti,otap-del-sel-sdr104 = <0x6>
603 ti,itap-del-sel-legacy = <0x0>
604 ti,itap-del-sel-sd-hs = <0x0>;
605 ti,itap-del-sel-sdr12 = <0x0>;
606 ti,itap-del-sel-sdr25 = <0x0>;
607 status = "disabled";
608 };
609
610 sdhci2: mmc@fa20000 {
611 compatible = "ti,am62-sdhci";
612 reg = <0x00 0x0fa20000 0x00 0x
613 interrupts = <GIC_SPI 82 IRQ_T
614 power-domains = <&k3_pds 184 T
615 clocks = <&k3_clks 184 5>, <&k
616 clock-names = "clk_ahb", "clk_
617 bus-width = <4>;
618 ti,clkbuf-sel = <0x7>;
619 ti,otap-del-sel-legacy = <0x0>
620 ti,otap-del-sel-sd-hs = <0x0>;
621 ti,otap-del-sel-sdr12 = <0xf>;
622 ti,otap-del-sel-sdr25 = <0xf>;
623 ti,otap-del-sel-sdr50 = <0xc>;
624 ti,otap-del-sel-ddr50 = <0x9>;
625 ti,otap-del-sel-sdr104 = <0x6>
626 ti,itap-del-sel-legacy = <0x0>
627 ti,itap-del-sel-sd-hs = <0x0>;
628 ti,itap-del-sel-sdr12 = <0x0>;
629 ti,itap-del-sel-sdr25 = <0x0>;
630 status = "disabled";
631 };
632
633 usbss0: usb@f900000 {
634 compatible = "ti,am62-usb";
635 reg = <0x00 0x0f900000 0x00 0x
636 <0x00 0x0f908000 0x00 0x
637 clocks = <&k3_clks 161 3>;
638 clock-names = "ref";
639 ti,syscon-phy-pll-refclk = <&u
640 #address-cells = <2>;
641 #size-cells = <2>;
642 power-domains = <&k3_pds 178 T
643 ranges;
644 status = "disabled";
645
646 usb0: usb@31000000 {
647 compatible = "snps,dwc
648 reg = <0x00 0x31000000
649 interrupts = <GIC_SPI
650 <GIC_SPI 188 IRQ_TYPE_
651 interrupt-names = "hos
652 maximum-speed = "high-
653 dr_mode = "otg";
654 snps,usb2-gadget-lpm-d
655 snps,usb2-lpm-disable;
656 };
657 };
658
659 fss: bus@fc00000 {
660 compatible = "simple-bus";
661 reg = <0x00 0x0fc00000 0x00 0x
662 #address-cells = <2>;
663 #size-cells = <2>;
664 ranges;
665
666 ospi0: spi@fc40000 {
667 compatible = "ti,am654
668 reg = <0x00 0x0fc40000
669 <0x05 0x00000000
670 interrupts = <GIC_SPI
671 cdns,fifo-depth = <256
672 cdns,fifo-width = <4>;
673 cdns,trigger-address =
674 clocks = <&k3_clks 75
675 assigned-clocks = <&k3
676 assigned-clock-parents
677 assigned-clock-rates =
678 power-domains = <&k3_p
679 #address-cells = <1>;
680 #size-cells = <0>;
681 status = "disabled";
682 };
683 };
684
685 cpsw3g: ethernet@8000000 {
686 compatible = "ti,am642-cpsw-nu
687 #address-cells = <2>;
688 #size-cells = <2>;
689 reg = <0x00 0x08000000 0x00 0x
690 reg-names = "cpsw_nuss";
691 ranges = <0x00 0x00 0x00 0x080
692 clocks = <&k3_clks 13 0>;
693 assigned-clocks = <&k3_clks 13
694 assigned-clock-parents = <&k3_
695 clock-names = "fck";
696 power-domains = <&k3_pds 13 TI
697 status = "disabled";
698
699 dmas = <&main_pktdma 0xc600 15
700 <&main_pktdma 0xc601 15
701 <&main_pktdma 0xc602 15
702 <&main_pktdma 0xc603 15
703 <&main_pktdma 0xc604 15
704 <&main_pktdma 0xc605 15
705 <&main_pktdma 0xc606 15
706 <&main_pktdma 0xc607 15
707 <&main_pktdma 0x4600 15
708 dma-names = "tx0", "tx1", "tx2
709 "tx7", "rx";
710
711 ethernet-ports {
712 #address-cells = <1>;
713 #size-cells = <0>;
714
715 cpsw_port1: port@1 {
716 reg = <1>;
717 ti,mac-only;
718 label = "port1
719 phys = <&phy_g
720 mac-address =
721 ti,syscon-efus
722 status = "disa
723 };
724
725 cpsw_port2: port@2 {
726 reg = <2>;
727 ti,mac-only;
728 label = "port2
729 phys = <&phy_g
730 mac-address =
731 status = "disa
732 };
733 };
734
735 cpsw3g_mdio: mdio@f00 {
736 compatible = "ti,cpsw-
737 reg = <0x00 0xf00 0x00
738 #address-cells = <1>;
739 #size-cells = <0>;
740 clocks = <&k3_clks 13
741 clock-names = "fck";
742 bus_freq = <1000000>;
743 status = "disabled";
744 };
745
746 cpts@3d000 {
747 compatible = "ti,j721e
748 reg = <0x00 0x3d000 0x
749 clocks = <&k3_clks 13
750 clock-names = "cpts";
751 interrupts-extended =
752 interrupt-names = "cpt
753 ti,cpts-ext-ts-inputs
754 ti,cpts-periodic-outpu
755 };
756 };
757
758 hwspinlock: spinlock@2a000000 {
759 compatible = "ti,am64-hwspinlo
760 reg = <0x00 0x2a000000 0x00 0x
761 #hwlock-cells = <1>;
762 };
763
764 mailbox0_cluster0: mailbox@29000000 {
765 compatible = "ti,am64-mailbox"
766 reg = <0x00 0x29000000 0x00 0x
767 interrupts = <GIC_SPI 76 IRQ_T
768 #mbox-cells = <1>;
769 ti,mbox-num-users = <4>;
770 ti,mbox-num-fifos = <16>;
771 };
772
773 mailbox0_cluster1: mailbox@29010000 {
774 compatible = "ti,am64-mailbox"
775 reg = <0x00 0x29010000 0x00 0x
776 interrupts = <GIC_SPI 77 IRQ_T
777 #mbox-cells = <1>;
778 ti,mbox-num-users = <4>;
779 ti,mbox-num-fifos = <16>;
780 };
781
782 mailbox0_cluster2: mailbox@29020000 {
783 compatible = "ti,am64-mailbox"
784 reg = <0x00 0x29020000 0x00 0x
785 interrupts = <GIC_SPI 108 IRQ_
786 #mbox-cells = <1>;
787 ti,mbox-num-users = <4>;
788 ti,mbox-num-fifos = <16>;
789 };
790
791 mailbox0_cluster3: mailbox@29030000 {
792 compatible = "ti,am64-mailbox"
793 reg = <0x00 0x29030000 0x00 0x
794 interrupts = <GIC_SPI 109 IRQ_
795 #mbox-cells = <1>;
796 ti,mbox-num-users = <4>;
797 ti,mbox-num-fifos = <16>;
798 };
799
800 ecap0: pwm@23100000 {
801 compatible = "ti,am3352-ecap";
802 #pwm-cells = <3>;
803 reg = <0x00 0x23100000 0x00 0x
804 power-domains = <&k3_pds 51 TI
805 clocks = <&k3_clks 51 0>;
806 clock-names = "fck";
807 status = "disabled";
808 };
809
810 ecap1: pwm@23110000 {
811 compatible = "ti,am3352-ecap";
812 #pwm-cells = <3>;
813 reg = <0x00 0x23110000 0x00 0x
814 power-domains = <&k3_pds 52 TI
815 clocks = <&k3_clks 52 0>;
816 clock-names = "fck";
817 status = "disabled";
818 };
819
820 ecap2: pwm@23120000 {
821 compatible = "ti,am3352-ecap";
822 #pwm-cells = <3>;
823 reg = <0x00 0x23120000 0x00 0x
824 power-domains = <&k3_pds 53 TI
825 clocks = <&k3_clks 53 0>;
826 clock-names = "fck";
827 status = "disabled";
828 };
829
830 main_mcan0: can@20701000 {
831 compatible = "bosch,m_can";
832 reg = <0x00 0x20701000 0x00 0x
833 <0x00 0x20708000 0x00 0x
834 reg-names = "m_can", "message_
835 power-domains = <&k3_pds 98 TI
836 clocks = <&k3_clks 98 6>, <&k3
837 clock-names = "hclk", "cclk";
838 interrupts = <GIC_SPI 155 IRQ_
839 <GIC_SPI 156 IRQ_
840 interrupt-names = "int0", "int
841 bosch,mram-cfg = <0x0 128 64 6
842 status = "disabled";
843 };
844
845 main_mcan1: can@20711000 {
846 compatible = "bosch,m_can";
847 reg = <0x00 0x20711000 0x00 0x
848 <0x00 0x20718000 0x00 0x
849 reg-names = "m_can", "message_
850 power-domains = <&k3_pds 99 TI
851 clocks = <&k3_clks 99 6>, <&k3
852 clock-names = "hclk", "cclk";
853 interrupts = <GIC_SPI 213 IRQ_
854 <GIC_SPI 214 IRQ_
855 interrupt-names = "int0", "int
856 bosch,mram-cfg = <0x0 128 64 6
857 status = "disabled";
858 };
859
860 main_rti0: watchdog@e000000 {
861 compatible = "ti,j7-rti-wdt";
862 reg = <0x00 0x0e000000 0x00 0x
863 clocks = <&k3_clks 125 0>;
864 power-domains = <&k3_pds 125 T
865 assigned-clocks = <&k3_clks 12
866 assigned-clock-parents = <&k3_
867 };
868
869 main_rti1: watchdog@e010000 {
870 compatible = "ti,j7-rti-wdt";
871 reg = <0x00 0x0e010000 0x00 0x
872 clocks = <&k3_clks 126 0>;
873 power-domains = <&k3_pds 126 T
874 assigned-clocks = <&k3_clks 12
875 assigned-clock-parents = <&k3_
876 };
877
878 main_rti2: watchdog@e020000 {
879 compatible = "ti,j7-rti-wdt";
880 reg = <0x00 0x0e020000 0x00 0x
881 clocks = <&k3_clks 127 0>;
882 power-domains = <&k3_pds 127 T
883 assigned-clocks = <&k3_clks 12
884 assigned-clock-parents = <&k3_
885 };
886
887 main_rti3: watchdog@e030000 {
888 compatible = "ti,j7-rti-wdt";
889 reg = <0x00 0x0e030000 0x00 0x
890 clocks = <&k3_clks 128 0>;
891 power-domains = <&k3_pds 128 T
892 assigned-clocks = <&k3_clks 12
893 assigned-clock-parents = <&k3_
894 };
895
896 main_rti15: watchdog@e0f0000 {
897 compatible = "ti,j7-rti-wdt";
898 reg = <0x00 0x0e0f0000 0x00 0x
899 clocks = <&k3_clks 130 0>;
900 power-domains = <&k3_pds 130 T
901 assigned-clocks = <&k3_clks 13
902 assigned-clock-parents = <&k3_
903 };
904
905 epwm0: pwm@23000000 {
906 compatible = "ti,am64-epwm", "
907 #pwm-cells = <3>;
908 reg = <0x00 0x23000000 0x00 0x
909 power-domains = <&k3_pds 86 TI
910 clocks = <&epwm_tbclk 0>, <&k3
911 clock-names = "tbclk", "fck";
912 status = "disabled";
913 };
914
915 epwm1: pwm@23010000 {
916 compatible = "ti,am64-epwm", "
917 #pwm-cells = <3>;
918 reg = <0x00 0x23010000 0x00 0x
919 power-domains = <&k3_pds 87 TI
920 clocks = <&epwm_tbclk 1>, <&k3
921 clock-names = "tbclk", "fck";
922 status = "disabled";
923 };
924
925 epwm2: pwm@23020000 {
926 compatible = "ti,am64-epwm", "
927 #pwm-cells = <3>;
928 reg = <0x00 0x23020000 0x00 0x
929 power-domains = <&k3_pds 88 TI
930 clocks = <&epwm_tbclk 2>, <&k3
931 clock-names = "tbclk", "fck";
932 status = "disabled";
933 };
934
935 mcasp0: audio-controller@2b00000 {
936 compatible = "ti,am33xx-mcasp-
937 reg = <0x00 0x02b00000 0x00 0x
938 <0x00 0x02b08000 0x00 0x
939 reg-names = "mpu", "dat";
940 interrupts = <GIC_SPI 236 IRQ_
941 <GIC_SPI 235 IRQ_
942 interrupt-names = "tx", "rx";
943
944 dmas = <&main_bcdma 0 0xc500 0
945 dma-names = "tx", "rx";
946
947 clocks = <&k3_clks 190 0>;
948 clock-names = "fck";
949 assigned-clocks = <&k3_clks 19
950 assigned-clock-parents = <&k3_
951 power-domains = <&k3_pds 190 T
952 status = "disabled";
953 };
954
955 mcasp1: audio-controller@2b10000 {
956 compatible = "ti,am33xx-mcasp-
957 reg = <0x00 0x02b10000 0x00 0x
958 <0x00 0x02b18000 0x00 0x
959 reg-names = "mpu", "dat";
960 interrupts = <GIC_SPI 238 IRQ_
961 <GIC_SPI 237 IRQ_
962 interrupt-names = "tx", "rx";
963
964 dmas = <&main_bcdma 0 0xc501 0
965 dma-names = "tx", "rx";
966
967 clocks = <&k3_clks 191 0>;
968 clock-names = "fck";
969 assigned-clocks = <&k3_clks 19
970 assigned-clock-parents = <&k3_
971 power-domains = <&k3_pds 191 T
972 status = "disabled";
973 };
974
975 mcasp2: audio-controller@2b20000 {
976 compatible = "ti,am33xx-mcasp-
977 reg = <0x00 0x02b20000 0x00 0x
978 <0x00 0x02b28000 0x00 0x
979 reg-names = "mpu", "dat";
980 interrupts = <GIC_SPI 240 IRQ_
981 <GIC_SPI 239 IRQ_
982 interrupt-names = "tx", "rx";
983
984 dmas = <&main_bcdma 0 0xc502 0
985 dma-names = "tx", "rx";
986
987 clocks = <&k3_clks 192 0>;
988 clock-names = "fck";
989 assigned-clocks = <&k3_clks 19
990 assigned-clock-parents = <&k3_
991 power-domains = <&k3_pds 192 T
992 status = "disabled";
993 };
994
995 ti_csi2rx0: ticsi2rx@30102000 {
996 compatible = "ti,j721e-csi2rx-
997 reg = <0x00 0x30102000 0x00 0x
998 ranges;
999 #address-cells = <2>;
1000 #size-cells = <2>;
1001 dmas = <&main_bcdma_csi 0 0x5
1002 dma-names = "rx0";
1003 power-domains = <&k3_pds 182
1004 status = "disabled";
1005
1006 cdns_csi2rx0: csi-bridge@3010
1007 compatible = "ti,j721
1008 reg = <0x00 0x3010100
1009 clocks = <&k3_clks 18
1010 <&k3_clks 182
1011 clock-names = "sys_cl
1012 "pixel_if1_cl
1013 phys = <&dphy0>;
1014 phy-names = "dphy";
1015
1016 ports {
1017 #address-cell
1018 #size-cells =
1019
1020 csi0_port0: p
1021 reg =
1022 statu
1023 };
1024
1025 csi0_port1: p
1026 reg =
1027 statu
1028 };
1029
1030 csi0_port2: p
1031 reg =
1032 statu
1033 };
1034
1035 csi0_port3: p
1036 reg =
1037 statu
1038 };
1039
1040 csi0_port4: p
1041 reg =
1042 statu
1043 };
1044 };
1045 };
1046 };
1047
1048 dphy0: phy@30110000 {
1049 compatible = "cdns,dphy-rx";
1050 reg = <0x00 0x30110000 0x00 0
1051 #phy-cells = <0>;
1052 power-domains = <&k3_pds 185
1053 status = "disabled";
1054 };
1055
1056 vpu: video-codec@30210000 {
1057 compatible = "ti,j721s2-wave5
1058 reg = <0x00 0x30210000 0x00 0
1059 interrupts = <GIC_SPI 225 IRQ
1060 clocks = <&k3_clks 204 2>;
1061 power-domains = <&k3_pds 204
1062 };
1063 };
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