1 // SPDX-License-Identifier: GPL-2.0-only OR MI !! 1 // SPDX-License-Identifier: GPL-2.0
2 /* 2 /*
3 * Copyright (C) 2016-2024 Texas Instruments I !! 3 * Copyright (C) 2016-2020 Texas Instruments Incorporated - https://www.ti.com/
4 */ 4 */
5 5
6 /dts-v1/; 6 /dts-v1/;
7 7
8 #include "k3-am654.dtsi" 8 #include "k3-am654.dtsi"
9 #include <dt-bindings/input/input.h> 9 #include <dt-bindings/input/input.h>
10 #include <dt-bindings/net/ti-dp83867.h> 10 #include <dt-bindings/net/ti-dp83867.h>
11 11
12 / { 12 / {
13 compatible = "ti,am654-evm", "ti,am654 !! 13 compatible = "ti,am654-evm", "ti,am654";
14 model = "Texas Instruments AM654 Base 14 model = "Texas Instruments AM654 Base Board";
15 15
16 aliases { <<
17 serial0 = &wkup_uart0; <<
18 serial1 = &mcu_uart0; <<
19 serial2 = &main_uart0; <<
20 i2c0 = &wkup_i2c0; <<
21 i2c1 = &mcu_i2c0; <<
22 i2c2 = &main_i2c0; <<
23 i2c3 = &main_i2c1; <<
24 i2c4 = &main_i2c2; <<
25 ethernet0 = &cpsw_port1; <<
26 mmc0 = &sdhci0; <<
27 mmc1 = &sdhci1; <<
28 }; <<
29 <<
30 chosen { 16 chosen {
31 stdout-path = "serial2:115200n 17 stdout-path = "serial2:115200n8";
>> 18 bootargs = "earlycon=ns16550a,mmio32,0x02800000";
32 }; 19 };
33 20
34 memory@80000000 { 21 memory@80000000 {
35 device_type = "memory"; 22 device_type = "memory";
36 bootph-all; <<
37 /* 4G RAM */ 23 /* 4G RAM */
38 reg = <0x00000000 0x80000000 0 24 reg = <0x00000000 0x80000000 0x00000000 0x80000000>,
39 <0x00000008 0x80000000 0 25 <0x00000008 0x80000000 0x00000000 0x80000000>;
40 }; 26 };
41 27
42 reserved-memory { 28 reserved-memory {
43 #address-cells = <2>; 29 #address-cells = <2>;
44 #size-cells = <2>; 30 #size-cells = <2>;
45 ranges; 31 ranges;
46 32
47 secure_ddr: secure-ddr@9e80000 33 secure_ddr: secure-ddr@9e800000 {
48 reg = <0 0x9e800000 0 34 reg = <0 0x9e800000 0 0x01800000>; /* for OP-TEE */
49 alignment = <0x1000>; 35 alignment = <0x1000>;
50 no-map; 36 no-map;
51 }; 37 };
52 38
53 mcu_r5fss0_core0_dma_memory_re 39 mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 {
54 compatible = "shared-d 40 compatible = "shared-dma-pool";
55 reg = <0 0xa0000000 0 41 reg = <0 0xa0000000 0 0x100000>;
56 no-map; 42 no-map;
57 }; 43 };
58 44
59 mcu_r5fss0_core0_memory_region 45 mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 {
60 compatible = "shared-d 46 compatible = "shared-dma-pool";
61 reg = <0 0xa0100000 0 47 reg = <0 0xa0100000 0 0xf00000>;
62 no-map; 48 no-map;
63 }; 49 };
64 50
65 mcu_r5fss0_core1_dma_memory_re 51 mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 {
66 compatible = "shared-d 52 compatible = "shared-dma-pool";
67 reg = <0 0xa1000000 0 53 reg = <0 0xa1000000 0 0x100000>;
68 no-map; 54 no-map;
69 }; 55 };
70 56
71 mcu_r5fss0_core1_memory_region 57 mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 {
72 compatible = "shared-d 58 compatible = "shared-dma-pool";
73 reg = <0 0xa1100000 0 59 reg = <0 0xa1100000 0 0xf00000>;
74 no-map; 60 no-map;
75 }; 61 };
76 62
77 rtos_ipc_memory_region: ipc-me 63 rtos_ipc_memory_region: ipc-memories@a2000000 {
78 reg = <0x00 0xa2000000 64 reg = <0x00 0xa2000000 0x00 0x00100000>;
79 alignment = <0x1000>; 65 alignment = <0x1000>;
80 no-map; 66 no-map;
81 }; 67 };
82 }; 68 };
83 69
84 gpio-keys { 70 gpio-keys {
85 compatible = "gpio-keys"; 71 compatible = "gpio-keys";
86 autorepeat; 72 autorepeat;
87 pinctrl-names = "default"; 73 pinctrl-names = "default";
88 pinctrl-0 = <&push_button_pins 74 pinctrl-0 = <&push_button_pins_default>;
89 75
90 switch-5 { !! 76 sw5 {
91 label = "GPIO Key USER 77 label = "GPIO Key USER1";
92 linux,code = <BTN_0>; 78 linux,code = <BTN_0>;
93 gpios = <&wkup_gpio0 2 79 gpios = <&wkup_gpio0 24 GPIO_ACTIVE_LOW>;
94 }; 80 };
95 81
96 switch-6 { !! 82 sw6 {
97 label = "GPIO Key USER 83 label = "GPIO Key USER2";
98 linux,code = <BTN_1>; 84 linux,code = <BTN_1>;
99 gpios = <&wkup_gpio0 2 85 gpios = <&wkup_gpio0 27 GPIO_ACTIVE_LOW>;
100 }; 86 };
101 }; 87 };
102 88
103 evm_12v0: regulator-0 { !! 89 evm_12v0: fixedregulator-evm12v0 {
104 /* main supply */ 90 /* main supply */
105 compatible = "regulator-fixed" 91 compatible = "regulator-fixed";
106 regulator-name = "evm_12v0"; 92 regulator-name = "evm_12v0";
107 regulator-min-microvolt = <120 93 regulator-min-microvolt = <12000000>;
108 regulator-max-microvolt = <120 94 regulator-max-microvolt = <12000000>;
109 regulator-always-on; 95 regulator-always-on;
110 regulator-boot-on; 96 regulator-boot-on;
111 }; 97 };
112 98
113 vcc3v3_io: regulator-1 { !! 99 vcc3v3_io: fixedregulator-vcc3v3io {
114 /* Output of TPS54334 */ 100 /* Output of TPS54334 */
115 compatible = "regulator-fixed" 101 compatible = "regulator-fixed";
116 regulator-name = "vcc3v3_io"; 102 regulator-name = "vcc3v3_io";
117 regulator-min-microvolt = <330 103 regulator-min-microvolt = <3300000>;
118 regulator-max-microvolt = <330 104 regulator-max-microvolt = <3300000>;
119 regulator-always-on; 105 regulator-always-on;
120 regulator-boot-on; 106 regulator-boot-on;
121 vin-supply = <&evm_12v0>; 107 vin-supply = <&evm_12v0>;
122 }; 108 };
123 109
124 vdd_mmc1_sd: regulator-2 { !! 110 vdd_mmc1_sd: fixedregulator-sd {
125 compatible = "regulator-fixed" 111 compatible = "regulator-fixed";
126 regulator-name = "vdd_mmc1_sd" 112 regulator-name = "vdd_mmc1_sd";
127 regulator-min-microvolt = <330 113 regulator-min-microvolt = <3300000>;
128 regulator-max-microvolt = <330 114 regulator-max-microvolt = <3300000>;
129 regulator-boot-on; 115 regulator-boot-on;
130 enable-active-high; 116 enable-active-high;
131 vin-supply = <&vcc3v3_io>; 117 vin-supply = <&vcc3v3_io>;
132 gpio = <&pca9554 4 GPIO_ACTIVE 118 gpio = <&pca9554 4 GPIO_ACTIVE_HIGH>;
133 }; 119 };
134 <<
135 vtt_supply: regulator-3 { <<
136 compatible = "regulator-fixed" <<
137 regulator-name = "vtt"; <<
138 pinctrl-names = "default"; <<
139 pinctrl-0 = <&ddr_vtt_pins_def <<
140 regulator-min-microvolt = <330 <<
141 regulator-max-microvolt = <330 <<
142 enable-active-high; <<
143 regulator-always-on; <<
144 regulator-boot-on; <<
145 vin-supply = <&vcc3v3_io>; <<
146 gpio = <&wkup_gpio0 28 GPIO_AC <<
147 }; <<
148 }; 120 };
149 121
150 &wkup_pmx0 { 122 &wkup_pmx0 {
151 wkup_uart0_pins_default: wkup-uart0-de !! 123 wkup_i2c0_pins_default: wkup-i2c0-pins-default {
152 pinctrl-single,pins = < <<
153 AM65X_WKUP_IOPAD(0x00a <<
154 AM65X_WKUP_IOPAD(0x00a <<
155 AM65X_WKUP_IOPAD(0x00c <<
156 AM65X_WKUP_IOPAD(0x00c <<
157 >; <<
158 }; <<
159 <<
160 ddr_vtt_pins_default: ddr-vtt-default- <<
161 pinctrl-single,pins = < <<
162 AM65X_WKUP_IOPAD(0x004 <<
163 >; <<
164 }; <<
165 <<
166 wkup_i2c0_pins_default: wkup-i2c0-defa <<
167 pinctrl-single,pins = < 124 pinctrl-single,pins = <
168 AM65X_WKUP_IOPAD(0x00e 125 AM65X_WKUP_IOPAD(0x00e0, PIN_INPUT, 0) /* (AC7) WKUP_I2C0_SCL */
169 AM65X_WKUP_IOPAD(0x00e 126 AM65X_WKUP_IOPAD(0x00e4, PIN_INPUT, 0) /* (AD6) WKUP_I2C0_SDA */
170 >; 127 >;
171 }; 128 };
172 129
173 push_button_pins_default: push-button- !! 130 push_button_pins_default: push-button-pins-default {
174 pinctrl-single,pins = < 131 pinctrl-single,pins = <
175 AM65X_WKUP_IOPAD(0x003 132 AM65X_WKUP_IOPAD(0x0030, PIN_INPUT, 7) /* (R5) WKUP_GPIO0_24 */
176 AM65X_WKUP_IOPAD(0x003 133 AM65X_WKUP_IOPAD(0x003c, PIN_INPUT, 7) /* (P2) WKUP_GPIO0_27 */
177 >; 134 >;
178 }; 135 };
179 136
180 mcu_fss0_ospi0_pins_default: mcu-fss0- !! 137 mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-pins-default {
181 pinctrl-single,pins = < 138 pinctrl-single,pins = <
182 AM65X_WKUP_IOPAD(0x000 139 AM65X_WKUP_IOPAD(0x0000, PIN_OUTPUT, 0) /* (V1) MCU_OSPI0_CLK */
183 AM65X_WKUP_IOPAD(0x000 140 AM65X_WKUP_IOPAD(0x0008, PIN_INPUT, 0) /* (U2) MCU_OSPI0_DQS */
184 AM65X_WKUP_IOPAD(0x000 141 AM65X_WKUP_IOPAD(0x000c, PIN_INPUT, 0) /* (U4) MCU_OSPI0_D0 */
185 AM65X_WKUP_IOPAD(0x001 142 AM65X_WKUP_IOPAD(0x0010, PIN_INPUT, 0) /* (U5) MCU_OSPI0_D1 */
186 AM65X_WKUP_IOPAD(0x001 143 AM65X_WKUP_IOPAD(0x0014, PIN_INPUT, 0) /* (T2) MCU_OSPI0_D2 */
187 AM65X_WKUP_IOPAD(0x001 144 AM65X_WKUP_IOPAD(0x0018, PIN_INPUT, 0) /* (T3) MCU_OSPI0_D3 */
188 AM65X_WKUP_IOPAD(0x001 145 AM65X_WKUP_IOPAD(0x001c, PIN_INPUT, 0) /* (T4) MCU_OSPI0_D4 */
189 AM65X_WKUP_IOPAD(0x002 146 AM65X_WKUP_IOPAD(0x0020, PIN_INPUT, 0) /* (T5) MCU_OSPI0_D5 */
190 AM65X_WKUP_IOPAD(0x002 147 AM65X_WKUP_IOPAD(0x0024, PIN_INPUT, 0) /* (R2) MCU_OSPI0_D6 */
191 AM65X_WKUP_IOPAD(0x002 148 AM65X_WKUP_IOPAD(0x0028, PIN_INPUT, 0) /* (R3) MCU_OSPI0_D7 */
192 AM65X_WKUP_IOPAD(0x002 149 AM65X_WKUP_IOPAD(0x002c, PIN_OUTPUT, 0) /* (R4) MCU_OSPI0_CSn0 */
193 >; 150 >;
194 }; 151 };
195 152
196 wkup_pca554_default: wkup-pca554-defau !! 153 wkup_pca554_default: wkup-pca554-default {
197 pinctrl-single,pins = < 154 pinctrl-single,pins = <
198 AM65X_WKUP_IOPAD(0x003 155 AM65X_WKUP_IOPAD(0x0034, PIN_INPUT, 7) /* (T1) MCU_OSPI1_CLK.WKUP_GPIO0_25 */
199 >; 156 >;
200 }; 157 };
201 158
202 mcu_uart0_pins_default: mcu-uart0-defa !! 159 mcu_cpsw_pins_default: mcu-cpsw-pins-default {
203 pinctrl-single,pins = < <<
204 AM65X_WKUP_IOPAD(0x004 <<
205 AM65X_WKUP_IOPAD(0x004 <<
206 AM65X_WKUP_IOPAD(0x004 <<
207 AM65X_WKUP_IOPAD(0x005 <<
208 >; <<
209 }; <<
210 <<
211 mcu_cpsw_pins_default: mcu-cpsw-defaul <<
212 pinctrl-single,pins = < 160 pinctrl-single,pins = <
213 AM65X_WKUP_IOPAD(0x005 161 AM65X_WKUP_IOPAD(0x0058, PIN_OUTPUT, 0) /* (N4) MCU_RGMII1_TX_CTL */
214 AM65X_WKUP_IOPAD(0x005 162 AM65X_WKUP_IOPAD(0x005c, PIN_INPUT, 0) /* (N5) MCU_RGMII1_RX_CTL */
215 AM65X_WKUP_IOPAD(0x006 163 AM65X_WKUP_IOPAD(0x0060, PIN_OUTPUT, 0) /* (M2) MCU_RGMII1_TD3 */
216 AM65X_WKUP_IOPAD(0x006 164 AM65X_WKUP_IOPAD(0x0064, PIN_OUTPUT, 0) /* (M3) MCU_RGMII1_TD2 */
217 AM65X_WKUP_IOPAD(0x006 165 AM65X_WKUP_IOPAD(0x0068, PIN_OUTPUT, 0) /* (M4) MCU_RGMII1_TD1 */
218 AM65X_WKUP_IOPAD(0x006 166 AM65X_WKUP_IOPAD(0x006c, PIN_OUTPUT, 0) /* (M5) MCU_RGMII1_TD0 */
219 AM65X_WKUP_IOPAD(0x007 167 AM65X_WKUP_IOPAD(0x0078, PIN_INPUT, 0) /* (L2) MCU_RGMII1_RD3 */
220 AM65X_WKUP_IOPAD(0x007 168 AM65X_WKUP_IOPAD(0x007c, PIN_INPUT, 0) /* (L5) MCU_RGMII1_RD2 */
221 AM65X_WKUP_IOPAD(0x008 169 AM65X_WKUP_IOPAD(0x0080, PIN_INPUT, 0) /* (M6) MCU_RGMII1_RD1 */
222 AM65X_WKUP_IOPAD(0x008 170 AM65X_WKUP_IOPAD(0x0084, PIN_INPUT, 0) /* (L6) MCU_RGMII1_RD0 */
223 AM65X_WKUP_IOPAD(0x007 171 AM65X_WKUP_IOPAD(0x0070, PIN_OUTPUT, 0) /* (N1) MCU_RGMII1_TXC */
224 AM65X_WKUP_IOPAD(0x007 172 AM65X_WKUP_IOPAD(0x0074, PIN_INPUT, 0) /* (M1) MCU_RGMII1_RXC */
225 >; 173 >;
226 }; 174 };
227 175
228 mcu_mdio_pins_default: mcu-mdio1-defau !! 176 mcu_mdio_pins_default: mcu-mdio1-pins-default {
229 pinctrl-single,pins = < 177 pinctrl-single,pins = <
230 AM65X_WKUP_IOPAD(0x008 178 AM65X_WKUP_IOPAD(0x008c, PIN_OUTPUT, 0) /* (L1) MCU_MDIO0_MDC */
231 AM65X_WKUP_IOPAD(0x008 179 AM65X_WKUP_IOPAD(0x0088, PIN_INPUT, 0) /* (L4) MCU_MDIO0_MDIO */
232 >; 180 >;
233 }; 181 };
234 <<
235 mcu_i2c0_pins_default: mcu-i2c0-defaul <<
236 pinctrl-single,pins = < <<
237 AM65X_WKUP_IOPAD(0x00e <<
238 AM65X_WKUP_IOPAD(0x00e <<
239 >; <<
240 }; <<
241 }; 182 };
242 183
243 &main_pmx0 { 184 &main_pmx0 {
244 main_uart0_pins_default: main-uart0-de !! 185 main_uart0_pins_default: main-uart0-pins-default {
245 pinctrl-single,pins = < 186 pinctrl-single,pins = <
246 AM65X_IOPAD(0x01e4, PI 187 AM65X_IOPAD(0x01e4, PIN_INPUT, 0) /* (AF11) UART0_RXD */
247 AM65X_IOPAD(0x01e8, PI 188 AM65X_IOPAD(0x01e8, PIN_OUTPUT, 0) /* (AE11) UART0_TXD */
248 AM65X_IOPAD(0x01ec, PI 189 AM65X_IOPAD(0x01ec, PIN_INPUT, 0) /* (AG11) UART0_CTSn */
249 AM65X_IOPAD(0x01f0, PI 190 AM65X_IOPAD(0x01f0, PIN_OUTPUT, 0) /* (AD11) UART0_RTSn */
250 >; 191 >;
251 }; 192 };
252 193
253 main_i2c2_pins_default: main-i2c2-defa !! 194 main_i2c2_pins_default: main-i2c2-pins-default {
254 pinctrl-single,pins = < 195 pinctrl-single,pins = <
255 AM65X_IOPAD(0x0074, PI 196 AM65X_IOPAD(0x0074, PIN_INPUT, 5) /* (T27) GPMC0_CSn3.I2C2_SCL */
256 AM65X_IOPAD(0x0070, PI 197 AM65X_IOPAD(0x0070, PIN_INPUT, 5) /* (R25) GPMC0_CSn2.I2C2_SDA */
257 >; 198 >;
258 }; 199 };
259 200
260 main_spi0_pins_default: main-spi0-defa !! 201 main_spi0_pins_default: main-spi0-pins-default {
261 pinctrl-single,pins = < 202 pinctrl-single,pins = <
262 AM65X_IOPAD(0x01c4, PI 203 AM65X_IOPAD(0x01c4, PIN_INPUT, 0) /* (AH13) SPI0_CLK */
263 AM65X_IOPAD(0x01c8, PI 204 AM65X_IOPAD(0x01c8, PIN_INPUT, 0) /* (AE13) SPI0_D0 */
264 AM65X_IOPAD(0x01cc, PI 205 AM65X_IOPAD(0x01cc, PIN_INPUT, 0) /* (AD13) SPI0_D1 */
265 AM65X_IOPAD(0x01bc, PI 206 AM65X_IOPAD(0x01bc, PIN_OUTPUT, 0) /* (AG13) SPI0_CS0 */
266 >; 207 >;
267 }; 208 };
268 209
269 main_mmc0_pins_default: main-mmc0-defa !! 210 main_mmc0_pins_default: main-mmc0-pins-default {
270 pinctrl-single,pins = < 211 pinctrl-single,pins = <
271 AM65X_IOPAD(0x01a8, PI 212 AM65X_IOPAD(0x01a8, PIN_INPUT_PULLDOWN, 0) /* (B25) MMC0_CLK */
272 AM65X_IOPAD(0x01ac, PI 213 AM65X_IOPAD(0x01ac, PIN_INPUT_PULLUP, 0) /* (B27) MMC0_CMD */
273 AM65X_IOPAD(0x01a4, PI 214 AM65X_IOPAD(0x01a4, PIN_INPUT_PULLUP, 0) /* (A26) MMC0_DAT0 */
274 AM65X_IOPAD(0x01a0, PI 215 AM65X_IOPAD(0x01a0, PIN_INPUT_PULLUP, 0) /* (E25) MMC0_DAT1 */
275 AM65X_IOPAD(0x019c, PI 216 AM65X_IOPAD(0x019c, PIN_INPUT_PULLUP, 0) /* (C26) MMC0_DAT2 */
276 AM65X_IOPAD(0x0198, PI 217 AM65X_IOPAD(0x0198, PIN_INPUT_PULLUP, 0) /* (A25) MMC0_DAT3 */
277 AM65X_IOPAD(0x0194, PI 218 AM65X_IOPAD(0x0194, PIN_INPUT_PULLUP, 0) /* (E24) MMC0_DAT4 */
278 AM65X_IOPAD(0x0190, PI 219 AM65X_IOPAD(0x0190, PIN_INPUT_PULLUP, 0) /* (A24) MMC0_DAT5 */
279 AM65X_IOPAD(0x018c, PI 220 AM65X_IOPAD(0x018c, PIN_INPUT_PULLUP, 0) /* (B26) MMC0_DAT6 */
280 AM65X_IOPAD(0x0188, PI 221 AM65X_IOPAD(0x0188, PIN_INPUT_PULLUP, 0) /* (D25) MMC0_DAT7 */
281 AM65X_IOPAD(0x01b4, PI 222 AM65X_IOPAD(0x01b4, PIN_INPUT_PULLUP, 0) /* (A23) MMC0_SDCD */
282 AM65X_IOPAD(0x01b0, PI 223 AM65X_IOPAD(0x01b0, PIN_INPUT, 0) /* (C25) MMC0_DS */
283 >; 224 >;
284 }; 225 };
285 226
286 main_mmc1_pins_default: main-mmc1-defa !! 227 main_mmc1_pins_default: main-mmc1-pins-default {
287 pinctrl-single,pins = < 228 pinctrl-single,pins = <
288 AM65X_IOPAD(0x02d4, PI 229 AM65X_IOPAD(0x02d4, PIN_INPUT_PULLDOWN, 0) /* (C27) MMC1_CLK */
289 AM65X_IOPAD(0x02d8, PI 230 AM65X_IOPAD(0x02d8, PIN_INPUT_PULLUP, 0) /* (C28) MMC1_CMD */
290 AM65X_IOPAD(0x02d0, PI 231 AM65X_IOPAD(0x02d0, PIN_INPUT_PULLUP, 0) /* (D28) MMC1_DAT0 */
291 AM65X_IOPAD(0x02cc, PI 232 AM65X_IOPAD(0x02cc, PIN_INPUT_PULLUP, 0) /* (E27) MMC1_DAT1 */
292 AM65X_IOPAD(0x02c8, PI 233 AM65X_IOPAD(0x02c8, PIN_INPUT_PULLUP, 0) /* (D26) MMC1_DAT2 */
293 AM65X_IOPAD(0x02c4, PI 234 AM65X_IOPAD(0x02c4, PIN_INPUT_PULLUP, 0) /* (D27) MMC1_DAT3 */
294 AM65X_IOPAD(0x02dc, PI 235 AM65X_IOPAD(0x02dc, PIN_INPUT_PULLUP, 0) /* (B24) MMC1_SDCD */
295 AM65X_IOPAD(0x02e0, PI 236 AM65X_IOPAD(0x02e0, PIN_INPUT, 0) /* (C24) MMC1_SDWP */
296 >; 237 >;
297 }; 238 };
298 239
299 usb1_pins_default: usb1-default-pins { !! 240 usb1_pins_default: usb1-pins-default {
300 pinctrl-single,pins = < 241 pinctrl-single,pins = <
301 AM65X_IOPAD(0x02c0, PI 242 AM65X_IOPAD(0x02c0, PIN_OUTPUT, 0) /* (AC8) USB1_DRVVBUS */
302 >; 243 >;
303 }; 244 };
304 }; 245 };
305 246
306 &main_pmx1 { 247 &main_pmx1 {
307 main_i2c0_pins_default: main-i2c0-defa !! 248 main_i2c0_pins_default: main-i2c0-pins-default {
308 pinctrl-single,pins = < 249 pinctrl-single,pins = <
309 AM65X_IOPAD(0x0000, PI 250 AM65X_IOPAD(0x0000, PIN_INPUT, 0) /* (D20) I2C0_SCL */
310 AM65X_IOPAD(0x0004, PI 251 AM65X_IOPAD(0x0004, PIN_INPUT, 0) /* (C21) I2C0_SDA */
311 >; 252 >;
312 }; 253 };
313 254
314 main_i2c1_pins_default: main-i2c1-defa !! 255 main_i2c1_pins_default: main-i2c1-pins-default {
315 pinctrl-single,pins = < 256 pinctrl-single,pins = <
316 AM65X_IOPAD(0x0008, PI 257 AM65X_IOPAD(0x0008, PIN_INPUT, 0) /* (B21) I2C1_SCL */
317 AM65X_IOPAD(0x000c, PI 258 AM65X_IOPAD(0x000c, PIN_INPUT, 0) /* (E21) I2C1_SDA */
318 >; 259 >;
319 }; 260 };
320 261
321 ecap0_pins_default: ecap0-default-pins !! 262 ecap0_pins_default: ecap0-pins-default {
322 pinctrl-single,pins = < 263 pinctrl-single,pins = <
323 AM65X_IOPAD(0x0010, PI 264 AM65X_IOPAD(0x0010, PIN_INPUT, 0) /* (D21) ECAP0_IN_APWM_OUT */
324 >; 265 >;
325 }; 266 };
326 }; 267 };
327 268
328 &wkup_uart0 { 269 &wkup_uart0 {
329 /* Wakeup UART is used by System firmw 270 /* Wakeup UART is used by System firmware */
330 status = "reserved"; 271 status = "reserved";
331 pinctrl-names = "default"; <<
332 pinctrl-0 = <&wkup_uart0_pins_default> <<
333 }; <<
334 <<
335 &mcu_uart0 { <<
336 status = "okay"; <<
337 pinctrl-names = "default"; <<
338 pinctrl-0 = <&mcu_uart0_pins_default>; <<
339 }; 272 };
340 273
341 &main_uart0 { 274 &main_uart0 {
342 status = "okay"; <<
343 pinctrl-names = "default"; 275 pinctrl-names = "default";
344 pinctrl-0 = <&main_uart0_pins_default> 276 pinctrl-0 = <&main_uart0_pins_default>;
345 power-domains = <&k3_pds 146 TI_SCI_PD 277 power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>;
346 }; 278 };
347 279
348 &wkup_i2c0 { 280 &wkup_i2c0 {
349 status = "okay"; <<
350 pinctrl-names = "default"; 281 pinctrl-names = "default";
351 pinctrl-0 = <&wkup_i2c0_pins_default>; 282 pinctrl-0 = <&wkup_i2c0_pins_default>;
352 clock-frequency = <400000>; 283 clock-frequency = <400000>;
353 284
354 eeprom@50 { <<
355 /* AT24CM01 */ <<
356 compatible = "atmel,24c1024"; <<
357 reg = <0x50>; <<
358 }; <<
359 <<
360 vdd_mpu: regulator@60 { <<
361 compatible = "ti,tps62363"; <<
362 reg = <0x60>; <<
363 regulator-name = "VDD_MPU"; <<
364 regulator-min-microvolt = <500 <<
365 regulator-max-microvolt = <177 <<
366 regulator-always-on; <<
367 regulator-boot-on; <<
368 ti,vsel0-state-high; <<
369 ti,vsel1-state-high; <<
370 ti,enable-vout-discharge; <<
371 }; <<
372 <<
373 gpio@38 { <<
374 compatible = "nxp,pca9554"; <<
375 reg = <0x38>; <<
376 gpio-controller; <<
377 #gpio-cells = <2>; <<
378 }; <<
379 <<
380 pca9554: gpio@39 { 285 pca9554: gpio@39 {
381 compatible = "nxp,pca9554"; 286 compatible = "nxp,pca9554";
382 reg = <0x39>; 287 reg = <0x39>;
383 gpio-controller; 288 gpio-controller;
384 #gpio-cells = <2>; 289 #gpio-cells = <2>;
385 pinctrl-names = "default"; 290 pinctrl-names = "default";
386 pinctrl-0 = <&wkup_pca554_defa 291 pinctrl-0 = <&wkup_pca554_default>;
387 interrupt-parent = <&wkup_gpio 292 interrupt-parent = <&wkup_gpio0>;
388 interrupts = <25 IRQ_TYPE_EDGE 293 interrupts = <25 IRQ_TYPE_EDGE_FALLING>;
389 interrupt-controller; 294 interrupt-controller;
390 #interrupt-cells = <2>; 295 #interrupt-cells = <2>;
391 }; 296 };
392 }; 297 };
393 298
394 &mcu_i2c0 { <<
395 status = "okay"; <<
396 pinctrl-names = "default"; <<
397 pinctrl-0 = <&mcu_i2c0_pins_default>; <<
398 clock-frequency = <400000>; <<
399 }; <<
400 <<
401 &main_i2c0 { 299 &main_i2c0 {
402 status = "okay"; <<
403 pinctrl-names = "default"; 300 pinctrl-names = "default";
404 pinctrl-0 = <&main_i2c0_pins_default>; 301 pinctrl-0 = <&main_i2c0_pins_default>;
405 clock-frequency = <400000>; 302 clock-frequency = <400000>;
406 303
407 pca9555: gpio@21 { 304 pca9555: gpio@21 {
408 compatible = "nxp,pca9555"; 305 compatible = "nxp,pca9555";
409 reg = <0x21>; 306 reg = <0x21>;
410 gpio-controller; 307 gpio-controller;
411 #gpio-cells = <2>; 308 #gpio-cells = <2>;
412 }; 309 };
413 }; 310 };
414 311
415 &main_i2c1 { 312 &main_i2c1 {
416 status = "okay"; <<
417 pinctrl-names = "default"; 313 pinctrl-names = "default";
418 pinctrl-0 = <&main_i2c1_pins_default>; 314 pinctrl-0 = <&main_i2c1_pins_default>;
419 clock-frequency = <400000>; 315 clock-frequency = <400000>;
420 }; 316 };
421 317
422 &main_i2c2 { 318 &main_i2c2 {
423 status = "okay"; <<
424 pinctrl-names = "default"; 319 pinctrl-names = "default";
425 pinctrl-0 = <&main_i2c2_pins_default>; 320 pinctrl-0 = <&main_i2c2_pins_default>;
426 clock-frequency = <400000>; 321 clock-frequency = <400000>;
427 }; 322 };
428 323
429 &ecap0 { 324 &ecap0 {
430 status = "okay"; <<
431 pinctrl-names = "default"; 325 pinctrl-names = "default";
432 pinctrl-0 = <&ecap0_pins_default>; 326 pinctrl-0 = <&ecap0_pins_default>;
433 }; 327 };
434 328
435 &main_spi0 { 329 &main_spi0 {
436 status = "okay"; <<
437 pinctrl-names = "default"; 330 pinctrl-names = "default";
438 pinctrl-0 = <&main_spi0_pins_default>; 331 pinctrl-0 = <&main_spi0_pins_default>;
439 #address-cells = <1>; 332 #address-cells = <1>;
440 #size-cells = <0>; !! 333 #size-cells= <0>;
441 ti,pindir-d0-out-d1-in; 334 ti,pindir-d0-out-d1-in;
442 335
443 flash@0 { 336 flash@0 {
444 compatible = "jedec,spi-nor"; 337 compatible = "jedec,spi-nor";
445 reg = <0x0>; 338 reg = <0x0>;
446 spi-tx-bus-width = <1>; 339 spi-tx-bus-width = <1>;
447 spi-rx-bus-width = <1>; 340 spi-rx-bus-width = <1>;
448 spi-max-frequency = <48000000> 341 spi-max-frequency = <48000000>;
449 }; 342 };
450 }; 343 };
451 344
452 &sdhci0 { 345 &sdhci0 {
453 status = "okay"; <<
454 pinctrl-names = "default"; 346 pinctrl-names = "default";
455 pinctrl-0 = <&main_mmc0_pins_default>; 347 pinctrl-0 = <&main_mmc0_pins_default>;
456 bus-width = <8>; 348 bus-width = <8>;
457 non-removable; 349 non-removable;
458 ti,driver-strength-ohm = <50>; 350 ti,driver-strength-ohm = <50>;
459 disable-wp; 351 disable-wp;
460 }; 352 };
461 353
462 /* 354 /*
463 * Because of erratas i2025 and i2026 for sili 355 * Because of erratas i2025 and i2026 for silicon revision 1.0, the
464 * SD card interface might fail. Boards with s 356 * SD card interface might fail. Boards with sr1.0 are recommended to
465 * disable sdhci1 357 * disable sdhci1
466 */ 358 */
467 &sdhci1 { 359 &sdhci1 {
468 status = "okay"; <<
469 vmmc-supply = <&vdd_mmc1_sd>; 360 vmmc-supply = <&vdd_mmc1_sd>;
470 pinctrl-names = "default"; 361 pinctrl-names = "default";
471 pinctrl-0 = <&main_mmc1_pins_default>; 362 pinctrl-0 = <&main_mmc1_pins_default>;
472 ti,driver-strength-ohm = <50>; 363 ti,driver-strength-ohm = <50>;
473 disable-wp; 364 disable-wp;
474 }; 365 };
475 366
476 &usb1 { 367 &usb1 {
477 pinctrl-names = "default"; 368 pinctrl-names = "default";
478 pinctrl-0 = <&usb1_pins_default>; 369 pinctrl-0 = <&usb1_pins_default>;
479 dr_mode = "otg"; 370 dr_mode = "otg";
480 }; 371 };
481 372
482 &dwc3_0 { 373 &dwc3_0 {
483 status = "disabled"; 374 status = "disabled";
484 }; 375 };
485 376
486 &usb0_phy { 377 &usb0_phy {
487 status = "disabled"; 378 status = "disabled";
488 }; 379 };
489 380
490 &tscadc0 { 381 &tscadc0 {
491 status = "okay"; <<
492 adc { 382 adc {
493 ti,adc-channels = <0 1 2 3 4 5 383 ti,adc-channels = <0 1 2 3 4 5 6 7>;
494 }; 384 };
495 }; 385 };
496 386
497 &tscadc1 { 387 &tscadc1 {
498 status = "okay"; <<
499 adc { 388 adc {
500 ti,adc-channels = <0 1 2 3 4 5 389 ti,adc-channels = <0 1 2 3 4 5 6 7>;
501 }; 390 };
502 }; 391 };
503 392
504 &serdes0 { 393 &serdes0 {
505 status = "disabled"; 394 status = "disabled";
506 }; 395 };
507 396
508 &serdes1 { 397 &serdes1 {
509 status = "disabled"; 398 status = "disabled";
510 }; 399 };
511 400
>> 401 &pcie0_rc {
>> 402 status = "disabled";
>> 403 };
>> 404
>> 405 &pcie0_ep {
>> 406 status = "disabled";
>> 407 };
>> 408
>> 409 &pcie1_rc {
>> 410 status = "disabled";
>> 411 };
>> 412
>> 413 &pcie1_ep {
>> 414 status = "disabled";
>> 415 };
>> 416
>> 417 &m_can0 {
>> 418 status = "disabled";
>> 419 };
>> 420
>> 421 &m_can1 {
>> 422 status = "disabled";
>> 423 };
>> 424
512 &mailbox0_cluster0 { 425 &mailbox0_cluster0 {
513 status = "okay"; <<
514 interrupts = <436>; 426 interrupts = <436>;
515 427
516 mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0 428 mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 {
517 ti,mbox-tx = <1 0 0>; 429 ti,mbox-tx = <1 0 0>;
518 ti,mbox-rx = <0 0 0>; 430 ti,mbox-rx = <0 0 0>;
519 }; 431 };
520 }; 432 };
521 433
522 &mailbox0_cluster1 { 434 &mailbox0_cluster1 {
523 status = "okay"; <<
524 interrupts = <432>; 435 interrupts = <432>;
525 436
526 mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0 437 mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 {
527 ti,mbox-tx = <1 0 0>; 438 ti,mbox-tx = <1 0 0>;
528 ti,mbox-rx = <0 0 0>; 439 ti,mbox-rx = <0 0 0>;
529 }; 440 };
530 }; 441 };
531 442
>> 443 &mailbox0_cluster2 {
>> 444 status = "disabled";
>> 445 };
>> 446
>> 447 &mailbox0_cluster3 {
>> 448 status = "disabled";
>> 449 };
>> 450
>> 451 &mailbox0_cluster4 {
>> 452 status = "disabled";
>> 453 };
>> 454
>> 455 &mailbox0_cluster5 {
>> 456 status = "disabled";
>> 457 };
>> 458
>> 459 &mailbox0_cluster6 {
>> 460 status = "disabled";
>> 461 };
>> 462
>> 463 &mailbox0_cluster7 {
>> 464 status = "disabled";
>> 465 };
>> 466
>> 467 &mailbox0_cluster8 {
>> 468 status = "disabled";
>> 469 };
>> 470
>> 471 &mailbox0_cluster9 {
>> 472 status = "disabled";
>> 473 };
>> 474
>> 475 &mailbox0_cluster10 {
>> 476 status = "disabled";
>> 477 };
>> 478
>> 479 &mailbox0_cluster11 {
>> 480 status = "disabled";
>> 481 };
>> 482
532 &mcu_r5fss0_core0 { 483 &mcu_r5fss0_core0 {
533 memory-region = <&mcu_r5fss0_core0_dma 484 memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
534 <&mcu_r5fss0_core0_mem 485 <&mcu_r5fss0_core0_memory_region>;
535 mboxes = <&mailbox0_cluster0 &mbox_mcu 486 mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>;
536 }; 487 };
537 488
538 &mcu_r5fss0_core1 { 489 &mcu_r5fss0_core1 {
539 memory-region = <&mcu_r5fss0_core1_dma 490 memory-region = <&mcu_r5fss0_core1_dma_memory_region>,
540 <&mcu_r5fss0_core1_mem 491 <&mcu_r5fss0_core1_memory_region>;
541 mboxes = <&mailbox0_cluster1 &mbox_mcu 492 mboxes = <&mailbox0_cluster1 &mbox_mcu_r5fss0_core1>;
542 }; 493 };
543 494
544 &ospi0 { 495 &ospi0 {
545 status = "okay"; <<
546 pinctrl-names = "default"; 496 pinctrl-names = "default";
547 pinctrl-0 = <&mcu_fss0_ospi0_pins_defa 497 pinctrl-0 = <&mcu_fss0_ospi0_pins_default>;
548 498
549 flash@0 { 499 flash@0 {
550 compatible = "jedec,spi-nor"; 500 compatible = "jedec,spi-nor";
551 reg = <0x0>; 501 reg = <0x0>;
552 spi-tx-bus-width = <8>; 502 spi-tx-bus-width = <8>;
553 spi-rx-bus-width = <8>; 503 spi-rx-bus-width = <8>;
554 spi-max-frequency = <25000000> 504 spi-max-frequency = <25000000>;
555 cdns,tshsl-ns = <60>; 505 cdns,tshsl-ns = <60>;
556 cdns,tsd2d-ns = <60>; 506 cdns,tsd2d-ns = <60>;
557 cdns,tchsh-ns = <60>; 507 cdns,tchsh-ns = <60>;
558 cdns,tslch-ns = <60>; 508 cdns,tslch-ns = <60>;
559 cdns,read-delay = <0>; 509 cdns,read-delay = <0>;
560 <<
561 partitions { <<
562 compatible = "fixed-pa <<
563 #address-cells = <1>; <<
564 #size-cells = <1>; <<
565 <<
566 partition@0 { <<
567 label = "ospi. <<
568 reg = <0x0 0x8 <<
569 }; <<
570 <<
571 partition@80000 { <<
572 label = "ospi. <<
573 reg = <0x80000 <<
574 }; <<
575 <<
576 partition@280000 { <<
577 label = "ospi. <<
578 reg = <0x28000 <<
579 }; <<
580 <<
581 partition@680000 { <<
582 label = "ospi. <<
583 reg = <0x68000 <<
584 }; <<
585 <<
586 partition@6a0000 { <<
587 label = "ospi. <<
588 reg = <0x6a000 <<
589 }; <<
590 <<
591 partition@6c0000 { <<
592 label = "ospi. <<
593 reg = <0x6c000 <<
594 }; <<
595 <<
596 partition@800000 { <<
597 label = "ospi. <<
598 reg = <0x80000 <<
599 }; <<
600 <<
601 partition@3fe0000 { <<
602 label = "ospi. <<
603 reg = <0x3fe00 <<
604 }; <<
605 }; <<
606 }; 510 };
607 }; 511 };
608 512
609 &mcu_cpsw { 513 &mcu_cpsw {
610 pinctrl-names = "default"; 514 pinctrl-names = "default";
611 pinctrl-0 = <&mcu_cpsw_pins_default>; !! 515 pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>;
612 }; 516 };
613 517
614 &davinci_mdio { 518 &davinci_mdio {
615 status = "okay"; <<
616 pinctrl-names = "default"; <<
617 pinctrl-0 = <&mcu_mdio_pins_default>; <<
618 <<
619 phy0: ethernet-phy@0 { 519 phy0: ethernet-phy@0 {
620 reg = <0>; 520 reg = <0>;
621 ti,rx-internal-delay = <DP8386 521 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
622 ti,fifo-depth = <DP83867_PHYCR 522 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
623 }; 523 };
624 }; 524 };
625 525
626 &cpsw_port1 { 526 &cpsw_port1 {
627 phy-mode = "rgmii-rxid"; 527 phy-mode = "rgmii-rxid";
628 phy-handle = <&phy0>; 528 phy-handle = <&phy0>;
629 }; 529 };
630 530
>> 531 &mcasp0 {
>> 532 status = "disabled";
>> 533 };
>> 534
>> 535 &mcasp1 {
>> 536 status = "disabled";
>> 537 };
>> 538
>> 539 &mcasp2 {
>> 540 status = "disabled";
>> 541 };
>> 542
631 &dss { 543 &dss {
>> 544 status = "disabled";
>> 545 };
>> 546
>> 547 &icssg0_mdio {
>> 548 status = "disabled";
>> 549 };
>> 550
>> 551 &icssg1_mdio {
>> 552 status = "disabled";
>> 553 };
>> 554
>> 555 &icssg2_mdio {
632 status = "disabled"; 556 status = "disabled";
633 }; 557 };
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