1 // SPDX-License-Identifier: GPL-2.0-only OR MI
2 /**
3 * DT overlay for IDK application board on AM6
4 *
5 * Copyright (C) 2018-2024 Texas Instruments I
6 */
7
8 /dts-v1/;
9 /plugin/;
10
11 #include <dt-bindings/net/ti-dp83867.h>
12 #include "k3-pinctrl.h"
13
14 &{/} {
15 aliases {
16 ethernet1 = "/icssg2-eth/ether
17 ethernet2 = "/icssg2-eth/ether
18 };
19
20 /* Ethernet node on PRU-ICSSG2 */
21 icssg2_eth: icssg2-eth {
22 compatible = "ti,am654-icssg-p
23 pinctrl-names = "default";
24 pinctrl-0 = <&icssg2_rgmii_pin
25 sram = <&msmc_ram>;
26 ti,prus = <&pru2_0>, <&rtu2_0>
27 <&pru2_1>, <&rtu2_1>,
28 firmware-name = "ti-pruss/am65
29 "ti-pruss/am65
30 "ti-pruss/am65
31 "ti-pruss/am65
32 "ti-pruss/am65
33 "ti-pruss/am65
34
35 ti,pruss-gp-mux-sel = <2>,
36 <2>,
37 <2>,
38 <2>,
39 <2>,
40 <2>;
41
42 ti,mii-g-rt = <&icssg2_mii_g_r
43 ti,mii-rt = <&icssg2_mii_rt>;
44 ti,iep = <&icssg2_iep0>, <&ics
45
46 interrupt-parent = <&icssg2_in
47 interrupts = <24 0 2>, <25 1 3
48 interrupt-names = "tx_ts0", "t
49
50 dmas = <&main_udmap 0xc300>, /
51 <&main_udmap 0xc301>, /
52 <&main_udmap 0xc302>, /
53 <&main_udmap 0xc303>, /
54 <&main_udmap 0xc304>, /
55 <&main_udmap 0xc305>, /
56 <&main_udmap 0xc306>, /
57 <&main_udmap 0xc307>, /
58 <&main_udmap 0x4300>, /
59 <&main_udmap 0x4301>; /
60
61 dma-names = "tx0-0", "tx0-1",
62 "tx1-0", "tx1-1",
63 "rx0", "rx1";
64 ethernet-ports {
65 #address-cells = <1>;
66 #size-cells = <0>;
67 icssg2_emac0: port@0 {
68 reg = <0>;
69 phy-handle = <
70 phy-mode = "rg
71 ti,syscon-rgmi
72 /* Filled in b
73 local-mac-addr
74 };
75 icssg2_emac1: port@1 {
76 reg = <1>;
77 phy-handle = <
78 phy-mode = "rg
79 ti,syscon-rgmi
80 /* Filled in b
81 local-mac-addr
82 };
83 };
84 };
85 };
86
87 &main_pmx0 {
88
89 icssg2_mdio_pins_default: icssg2-mdio-
90 pinctrl-single,pins = <
91 AM65X_IOPAD(0x0094, PI
92 AM65X_IOPAD(0x00c8, PI
93 >;
94 };
95
96 icssg2_rgmii_pins_default: icssg2-rgmi
97 pinctrl-single,pins = <
98 AM65X_IOPAD(0x00ac, PI
99 AM65X_IOPAD(0x00b0, PI
100 AM65X_IOPAD(0x00b4, PI
101 AM65X_IOPAD(0x00b8, PI
102 AM65X_IOPAD(0x00cc, PI
103 AM65X_IOPAD(0x00d0, PI
104 AM65X_IOPAD(0x00d4, PI
105 AM65X_IOPAD(0x00d8, PI
106 AM65X_IOPAD(0x00dc, PI
107 AM65X_IOPAD(0x00c4, PI
108 AM65X_IOPAD(0x00c0, PI
109 AM65X_IOPAD(0x00bc, PI
110
111 AM65X_IOPAD(0x0078, PI
112 AM65X_IOPAD(0x007c, PI
113 AM65X_IOPAD(0x0080, PI
114 AM65X_IOPAD(0x0084, PI
115 AM65X_IOPAD(0x0098, PI
116 AM65X_IOPAD(0x009c, PI
117 AM65X_IOPAD(0x00a0, PI
118 AM65X_IOPAD(0x00a4, PI
119 AM65X_IOPAD(0x00a8, PI
120 AM65X_IOPAD(0x0090, PI
121 AM65X_IOPAD(0x008c, PI
122 AM65X_IOPAD(0x0088, PI
123 >;
124 };
125 };
126
127 &icssg2_mdio {
128 status = "okay";
129 pinctrl-names = "default";
130 pinctrl-0 = <&icssg2_mdio_pins_default
131 #address-cells = <1>;
132 #size-cells = <0>;
133
134 icssg2_phy0: ethernet-phy@0 {
135 reg = <0>;
136 ti,rx-internal-delay = <DP8386
137 ti,fifo-depth = <DP83867_PHYCR
138 };
139
140 icssg2_phy1: ethernet-phy@3 {
141 reg = <3>;
142 ti,rx-internal-delay = <DP8386
143 ti,fifo-depth = <DP83867_PHYCR
144 };
145 };
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