1 // SPDX-License-Identifier: GPL-2.0-only OR MI
2 /**
3 * DT overlay for IDK application board on AM6
4 *
5 * Copyright (C) 2018-2024 Texas Instruments I
6 */
7
8 /dts-v1/;
9 /plugin/;
10
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/net/ti-dp83867.h>
13 #include "k3-pinctrl.h"
14
15 &{/} {
16 aliases {
17 ethernet3 = "/icssg0-eth/ether
18 ethernet4 = "/icssg0-eth/ether
19 ethernet5 = "/icssg1-eth/ether
20 ethernet6 = "/icssg1-eth/ether
21 };
22
23 /* Ethernet node on PRU-ICSSG0 */
24 icssg0_eth: icssg0-eth {
25 compatible = "ti,am654-icssg-p
26 pinctrl-names = "default";
27 pinctrl-0 = <&icssg0_rgmii_pin
28 sram = <&msmc_ram>;
29 ti,prus = <&pru0_0>, <&rtu0_0>
30 firmware-name = "ti-pruss/am65
31 "ti-pruss/am65
32 "ti-pruss/am65
33 "ti-pruss/am65
34 "ti-pruss/am65
35 "ti-pruss/am65
36
37 ti,pruss-gp-mux-sel = <2>,
38 <2>,
39 <2>,
40 <2>,
41 <2>,
42 <2>;
43
44 ti,mii-g-rt = <&icssg0_mii_g_r
45 ti,mii-rt = <&icssg0_mii_rt>;
46 ti,iep = <&icssg0_iep0>, <&ic
47
48 interrupt-parent = <&icssg0_in
49 interrupts = <24 0 2>, <25 1 3
50 interrupt-names = "tx_ts0", "t
51
52 dmas = <&main_udmap 0xc100>, /
53 <&main_udmap 0xc101>, /
54 <&main_udmap 0xc102>, /
55 <&main_udmap 0xc103>, /
56 <&main_udmap 0xc104>, /
57 <&main_udmap 0xc105>, /
58 <&main_udmap 0xc106>, /
59 <&main_udmap 0xc107>, /
60
61 <&main_udmap 0x4100>, /
62 <&main_udmap 0x4101>; /
63 dma-names = "tx0-0", "tx0-1",
64 "tx1-0", "tx1-1",
65 "rx0", "rx1";
66
67 ethernet-ports {
68 #address-cells = <1>;
69 #size-cells = <0>;
70 icssg0_emac0: port@0 {
71 reg = <0>;
72 phy-handle = <
73 phy-mode = "rg
74 ti,syscon-rgmi
75 /* Filled in b
76 local-mac-addr
77 };
78 icssg0_emac1: port@1 {
79 reg = <1>;
80 phy-handle = <
81 phy-mode = "rg
82 ti,syscon-rgmi
83 /* Filled in b
84 local-mac-addr
85 };
86 };
87 };
88
89 /* Ethernet node on PRU-ICSSG1 */
90 icssg1_eth: icssg1-eth {
91 compatible = "ti,am654-icssg-p
92 pinctrl-names = "default";
93 pinctrl-0 = <&icssg1_rgmii_pin
94 sram = <&msmc_ram>;
95 ti,prus = <&pru1_0>, <&rtu1_0>
96 firmware-name = "ti-pruss/am65
97 "ti-pruss/am65
98 "ti-pruss/am65
99 "ti-pruss/am65
100 "ti-pruss/am65
101 "ti-pruss/am65
102
103 ti,pruss-gp-mux-sel = <2>,
104 <2>,
105 <2>,
106 <2>,
107 <2>,
108 <2>;
109
110 ti,mii-g-rt = <&icssg1_mii_g_r
111 ti,mii-rt = <&icssg1_mii_rt>;
112 ti,iep = <&icssg1_iep0>, <&ic
113
114 interrupt-parent = <&icssg1_in
115 interrupts = <24 0 2>, <25 1 3
116 interrupt-names = "tx_ts0", "t
117
118 dmas = <&main_udmap 0xc200>, /
119 <&main_udmap 0xc201>, /
120 <&main_udmap 0xc202>, /
121 <&main_udmap 0xc203>, /
122 <&main_udmap 0xc204>, /
123 <&main_udmap 0xc205>, /
124 <&main_udmap 0xc206>, /
125 <&main_udmap 0xc207>, /
126
127 <&main_udmap 0x4200>, /
128 <&main_udmap 0x4201>; /
129 dma-names = "tx0-0", "tx0-1",
130 "tx1-0", "tx1-1",
131 "rx0", "rx1";
132
133 ethernet-ports {
134 #address-cells = <1>;
135 #size-cells = <0>;
136 icssg1_emac0: port@0 {
137 reg = <0>;
138 phy-handle = <
139 phy-mode = "rg
140 ti,syscon-rgmi
141 /* Filled in b
142 local-mac-addr
143 };
144 icssg1_emac1: port@1 {
145 reg = <1>;
146 phy-handle = <
147 phy-mode = "rg
148 ti,syscon-rgmi
149 /* Filled in b
150 local-mac-addr
151 };
152 };
153 };
154
155 transceiver1: can-phy0 {
156 compatible = "ti,tcan1042";
157 #phy-cells = <0>;
158 max-bitrate = <5000000>;
159 pinctrl-names = "default";
160 pinctrl-0 = <&mcan0_gpio_pins_
161 standby-gpios = <&main_gpio1 4
162 };
163
164 transceiver2: can-phy1 {
165 compatible = "ti,tcan1042";
166 #phy-cells = <0>;
167 max-bitrate = <5000000>;
168 pinctrl-names = "default";
169 pinctrl-0 = <&mcan1_gpio_pins_
170 standby-gpios = <&main_gpio1 6
171 };
172 };
173
174 &main_pmx0 {
175
176 icssg0_mdio_pins_default: icssg0-mdio-
177 pinctrl-single,pins = <
178 AM65X_IOPAD(0x0294, PI
179 AM65X_IOPAD(0x0298, PI
180 >;
181 };
182
183 icssg0_rgmii_pins_default: icssg0-rgmi
184 pinctrl-single,pins = <
185 AM65X_IOPAD(0x0244, PI
186 AM65X_IOPAD(0x0248, PI
187 AM65X_IOPAD(0x024c, PI
188 AM65X_IOPAD(0x0250, PI
189 AM65X_IOPAD(0x0274, PI
190 AM65X_IOPAD(0x0278, PI
191 AM65X_IOPAD(0x027c, PI
192 AM65X_IOPAD(0x0280, PI
193 AM65X_IOPAD(0x0284, PI
194 AM65X_IOPAD(0x0270, PI
195 AM65X_IOPAD(0x025c, PI
196 AM65X_IOPAD(0x0254, PI
197
198 AM65X_IOPAD(0x01f4, PI
199 AM65X_IOPAD(0x01f8, PI
200 AM65X_IOPAD(0x01fc, PI
201 AM65X_IOPAD(0x0200, PI
202 AM65X_IOPAD(0x0224, PI
203 AM65X_IOPAD(0x0228, PI
204 AM65X_IOPAD(0x022c, PI
205 AM65X_IOPAD(0x0230, PI
206 AM65X_IOPAD(0x0234, PI
207 AM65X_IOPAD(0x0220, PI
208 AM65X_IOPAD(0x020c, PI
209 AM65X_IOPAD(0x0204, PI
210 >;
211 };
212
213 icssg0_iep0_pins_default: icssg0-iep0-
214 pinctrl-single,pins = <
215 AM65X_IOPAD(0x0240, PI
216 >;
217 };
218
219 icssg1_mdio_pins_default: icssg1-mdio-
220 pinctrl-single,pins = <
221 AM65X_IOPAD(0x0180, PI
222 AM65X_IOPAD(0x0184, PI
223 >;
224 };
225
226 icssg1_rgmii_pins_default: icssg1-rgmi
227 pinctrl-single,pins = <
228 AM65X_IOPAD(0x0130, PI
229 AM65X_IOPAD(0x0134, PI
230 AM65X_IOPAD(0x0138, PI
231 AM65X_IOPAD(0x013c, PI
232 AM65X_IOPAD(0x0160, PI
233 AM65X_IOPAD(0x0164, PI
234 AM65X_IOPAD(0x0168, PI
235 AM65X_IOPAD(0x016c, PI
236 AM65X_IOPAD(0x0170, PI
237 AM65X_IOPAD(0x015c, PI
238 AM65X_IOPAD(0x0148, PI
239 AM65X_IOPAD(0x0140, PI
240
241 AM65X_IOPAD(0x00e0, PI
242 AM65X_IOPAD(0x00e4, PI
243 AM65X_IOPAD(0x00e8, PI
244 AM65X_IOPAD(0x00ec, PI
245 AM65X_IOPAD(0x0110, PI
246 AM65X_IOPAD(0x0114, PI
247 AM65X_IOPAD(0x0118, PI
248 AM65X_IOPAD(0x011c, PI
249 AM65X_IOPAD(0x0120, PI
250 AM65X_IOPAD(0x010c, PI
251 AM65X_IOPAD(0x00f8, PI
252 AM65X_IOPAD(0x00f0, PI
253 >;
254 };
255
256 icssg1_iep0_pins_default: icssg1-iep0-
257 pinctrl-single,pins = <
258 AM65X_IOPAD(0x012c, PI
259 >;
260 };
261
262 mcan0_gpio_pins_default: mcan0-gpio-de
263 pinctrl-single,pins = <
264 AM65X_IOPAD(0x023c, PI
265 >;
266 };
267
268 mcan1_gpio_pins_default: mcan1-gpio-de
269 pinctrl-single,pins = <
270 AM65X_IOPAD(0x028c, PI
271 >;
272 };
273 };
274
275 &wkup_pmx0 {
276 mcu_mcan0_pins_default: mcu-mcan0-defa
277 pinctrl-single,pins = <
278 AM65X_WKUP_IOPAD(0x00a
279 AM65X_WKUP_IOPAD(0x00a
280 >;
281 };
282
283 mcu_mcan1_pins_default: mcu-mcan1-defa
284 pinctrl-single,pins = <
285 AM65X_WKUP_IOPAD(0x00c
286 AM65X_WKUP_IOPAD(0x00c
287 >;
288 };
289 };
290
291 &icssg0_mdio {
292 status = "okay";
293 pinctrl-names = "default";
294 pinctrl-0 = <&icssg0_mdio_pins_default
295 #address-cells = <1>;
296 #size-cells = <0>;
297
298 icssg0_phy0: ethernet-phy@0 {
299 reg = <0>;
300 ti,rx-internal-delay = <DP8386
301 ti,fifo-depth = <DP83867_PHYCR
302 };
303
304 icssg0_phy1: ethernet-phy@3 {
305 reg = <3>;
306 ti,rx-internal-delay = <DP8386
307 ti,fifo-depth = <DP83867_PHYCR
308 };
309 };
310
311 &icssg0_iep0 {
312 pinctrl-names = "default";
313 pinctrl-0 = <&icssg0_iep0_pins_default
314 };
315
316 &icssg1_mdio {
317 status = "okay";
318 pinctrl-names = "default";
319 pinctrl-0 = <&icssg1_mdio_pins_default
320 #address-cells = <1>;
321 #size-cells = <0>;
322
323 icssg1_phy0: ethernet-phy@0 {
324 reg = <0>;
325 ti,rx-internal-delay = <DP8386
326 ti,fifo-depth = <DP83867_PHYCR
327 };
328
329 icssg1_phy1: ethernet-phy@3 {
330 reg = <3>;
331 ti,rx-internal-delay = <DP8386
332 ti,fifo-depth = <DP83867_PHYCR
333 };
334 };
335
336 &icssg1_iep0 {
337 pinctrl-names = "default";
338 pinctrl-0 = <&icssg1_iep0_pins_default
339 };
340
341 &m_can0 {
342 pinctrl-names = "default";
343 pinctrl-0 = <&mcu_mcan0_pins_default>;
344 phys = <&transceiver1>;
345 status = "okay";
346 };
347
348 &m_can1 {
349 pinctrl-names = "default";
350 pinctrl-0 = <&mcu_mcan1_pins_default>;
351 phys = <&transceiver2>;
352 status = "okay";
353 };
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