1 // SPDX-License-Identifier: GPL-2.0-only OR MI !! 1 // SPDX-License-Identifier: GPL-2.0
2 /* 2 /*
3 * Copyright (C) 2023-2024 Texas Instruments I !! 3 * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/
4 * 4 *
5 * Base Board: https://www.ti.com/lit/zip/SPRR 5 * Base Board: https://www.ti.com/lit/zip/SPRR463
6 */ 6 */
7 7
8 /dts-v1/; 8 /dts-v1/;
9 9
10 #include "k3-am68-sk-som.dtsi" 10 #include "k3-am68-sk-som.dtsi"
11 #include <dt-bindings/net/ti-dp83867.h> 11 #include <dt-bindings/net/ti-dp83867.h>
12 #include <dt-bindings/phy/phy-cadence.h> 12 #include <dt-bindings/phy/phy-cadence.h>
13 #include <dt-bindings/phy/phy.h> 13 #include <dt-bindings/phy/phy.h>
14 !! 14 #include <dt-bindings/mux/ti-serdes.h>
15 #include "k3-serdes.h" <<
16 15
17 / { 16 / {
18 compatible = "ti,am68-sk", "ti,j721s2" 17 compatible = "ti,am68-sk", "ti,j721s2";
19 model = "Texas Instruments AM68 SK"; 18 model = "Texas Instruments AM68 SK";
20 19
21 chosen { 20 chosen {
22 stdout-path = "serial2:115200n 21 stdout-path = "serial2:115200n8";
23 }; 22 };
24 23
25 aliases { 24 aliases {
26 serial0 = &wkup_uart0; 25 serial0 = &wkup_uart0;
27 serial1 = &mcu_uart0; 26 serial1 = &mcu_uart0;
28 serial2 = &main_uart8; 27 serial2 = &main_uart8;
29 mmc1 = &main_sdhci1; 28 mmc1 = &main_sdhci1;
30 can0 = &mcu_mcan0; 29 can0 = &mcu_mcan0;
31 can1 = &mcu_mcan1; 30 can1 = &mcu_mcan1;
32 can2 = &main_mcan6; 31 can2 = &main_mcan6;
33 can3 = &main_mcan7; 32 can3 = &main_mcan7;
34 ethernet0 = &cpsw_port1; <<
35 }; 33 };
36 34
37 vusb_main: regulator-vusb-main5v0 { 35 vusb_main: regulator-vusb-main5v0 {
38 /* USB MAIN INPUT 5V DC */ 36 /* USB MAIN INPUT 5V DC */
39 compatible = "regulator-fixed" 37 compatible = "regulator-fixed";
40 regulator-name = "vusb-main5v0 38 regulator-name = "vusb-main5v0";
41 regulator-min-microvolt = <500 39 regulator-min-microvolt = <5000000>;
42 regulator-max-microvolt = <500 40 regulator-max-microvolt = <5000000>;
43 regulator-always-on; 41 regulator-always-on;
44 regulator-boot-on; 42 regulator-boot-on;
45 }; 43 };
46 44
47 vsys_3v3: regulator-vsys3v3 { 45 vsys_3v3: regulator-vsys3v3 {
48 /* Output of LM5141 */ 46 /* Output of LM5141 */
49 compatible = "regulator-fixed" 47 compatible = "regulator-fixed";
50 regulator-name = "vsys_3v3"; 48 regulator-name = "vsys_3v3";
51 regulator-min-microvolt = <330 49 regulator-min-microvolt = <3300000>;
52 regulator-max-microvolt = <330 50 regulator-max-microvolt = <3300000>;
53 vin-supply = <&vusb_main>; 51 vin-supply = <&vusb_main>;
54 regulator-always-on; 52 regulator-always-on;
55 regulator-boot-on; 53 regulator-boot-on;
56 }; 54 };
57 55
58 vdd_mmc1: regulator-sd { 56 vdd_mmc1: regulator-sd {
59 /* Output of TPS22918 */ 57 /* Output of TPS22918 */
60 compatible = "regulator-fixed" 58 compatible = "regulator-fixed";
61 regulator-name = "vdd_mmc1"; 59 regulator-name = "vdd_mmc1";
62 regulator-min-microvolt = <330 60 regulator-min-microvolt = <3300000>;
63 regulator-max-microvolt = <330 61 regulator-max-microvolt = <3300000>;
64 regulator-boot-on; 62 regulator-boot-on;
65 enable-active-high; 63 enable-active-high;
66 vin-supply = <&vsys_3v3>; 64 vin-supply = <&vsys_3v3>;
67 gpio = <&exp1 8 GPIO_ACTIVE_HI 65 gpio = <&exp1 8 GPIO_ACTIVE_HIGH>;
68 }; 66 };
69 67
70 vdd_sd_dv: regulator-tlv71033 { 68 vdd_sd_dv: regulator-tlv71033 {
71 /* Output of TLV71033 */ 69 /* Output of TLV71033 */
72 compatible = "regulator-gpio"; 70 compatible = "regulator-gpio";
73 regulator-name = "tlv71033"; 71 regulator-name = "tlv71033";
74 pinctrl-names = "default"; 72 pinctrl-names = "default";
75 pinctrl-0 = <&vdd_sd_dv_pins_d 73 pinctrl-0 = <&vdd_sd_dv_pins_default>;
76 regulator-min-microvolt = <180 74 regulator-min-microvolt = <1800000>;
77 regulator-max-microvolt = <330 75 regulator-max-microvolt = <3300000>;
78 regulator-boot-on; 76 regulator-boot-on;
79 vin-supply = <&vsys_3v3>; 77 vin-supply = <&vsys_3v3>;
80 gpios = <&main_gpio0 49 GPIO_A 78 gpios = <&main_gpio0 49 GPIO_ACTIVE_HIGH>;
81 states = <1800000 0x0>, 79 states = <1800000 0x0>,
82 <3300000 0x1>; 80 <3300000 0x1>;
83 }; 81 };
84 82
85 vsys_io_1v8: regulator-vsys-io-1v8 { 83 vsys_io_1v8: regulator-vsys-io-1v8 {
86 compatible = "regulator-fixed" 84 compatible = "regulator-fixed";
87 regulator-name = "vsys_io_1v8" 85 regulator-name = "vsys_io_1v8";
88 regulator-min-microvolt = <180 86 regulator-min-microvolt = <1800000>;
89 regulator-max-microvolt = <180 87 regulator-max-microvolt = <1800000>;
90 regulator-always-on; 88 regulator-always-on;
91 regulator-boot-on; 89 regulator-boot-on;
92 }; 90 };
93 91
94 vsys_io_1v2: regulator-vsys-io-1v2 { 92 vsys_io_1v2: regulator-vsys-io-1v2 {
95 compatible = "regulator-fixed" 93 compatible = "regulator-fixed";
96 regulator-name = "vsys_io_1v2" 94 regulator-name = "vsys_io_1v2";
97 regulator-min-microvolt = <120 95 regulator-min-microvolt = <1200000>;
98 regulator-max-microvolt = <120 96 regulator-max-microvolt = <1200000>;
99 regulator-always-on; 97 regulator-always-on;
100 regulator-boot-on; 98 regulator-boot-on;
101 }; 99 };
102 100
103 transceiver1: can-phy0 { 101 transceiver1: can-phy0 {
104 compatible = "ti,tcan1042"; 102 compatible = "ti,tcan1042";
105 #phy-cells = <0>; 103 #phy-cells = <0>;
106 max-bitrate = <5000000>; 104 max-bitrate = <5000000>;
107 }; 105 };
108 106
109 transceiver2: can-phy1 { 107 transceiver2: can-phy1 {
110 compatible = "ti,tcan1042"; 108 compatible = "ti,tcan1042";
111 #phy-cells = <0>; 109 #phy-cells = <0>;
112 max-bitrate = <5000000>; 110 max-bitrate = <5000000>;
113 }; 111 };
114 112
115 transceiver3: can-phy2 { 113 transceiver3: can-phy2 {
116 compatible = "ti,tcan1042"; 114 compatible = "ti,tcan1042";
117 #phy-cells = <0>; 115 #phy-cells = <0>;
118 max-bitrate = <5000000>; 116 max-bitrate = <5000000>;
119 }; 117 };
120 118
121 transceiver4: can-phy3 { 119 transceiver4: can-phy3 {
122 compatible = "ti,tcan1042"; 120 compatible = "ti,tcan1042";
123 #phy-cells = <0>; 121 #phy-cells = <0>;
124 max-bitrate = <5000000>; 122 max-bitrate = <5000000>;
125 }; 123 };
126 <<
127 connector-hdmi { <<
128 compatible = "hdmi-connector"; <<
129 label = "hdmi"; <<
130 type = "a"; <<
131 pinctrl-names = "default"; <<
132 pinctrl-0 = <&hdmi_hpd_pins_de <<
133 ddc-i2c-bus = <&mcu_i2c1>; <<
134 /* HDMI_HPD */ <<
135 hpd-gpios = <&main_gpio0 0 GPI <<
136 <<
137 port { <<
138 hdmi_connector_in: end <<
139 remote-endpoin <<
140 }; <<
141 }; <<
142 }; <<
143 <<
144 bridge-dvi { <<
145 compatible = "ti,tfp410"; <<
146 /* HDMI_PDn */ <<
147 powerdown-gpios = <&exp2 0 GPI <<
148 ti,deskew = <0>; <<
149 <<
150 ports { <<
151 #address-cells = <1>; <<
152 #size-cells = <0>; <<
153 <<
154 port@0 { <<
155 reg = <0>; <<
156 <<
157 tfp410_in: end <<
158 remote <<
159 pclk-s <<
160 }; <<
161 }; <<
162 <<
163 port@1 { <<
164 reg = <1>; <<
165 <<
166 tfp410_out: en <<
167 remote <<
168 }; <<
169 }; <<
170 }; <<
171 }; <<
172 <<
173 csi_mux: mux-controller { <<
174 compatible = "gpio-mux"; <<
175 #mux-state-cells = <1>; <<
176 mux-gpios = <&exp3 1 GPIO_ACTI <<
177 idle-state = <0>; <<
178 }; <<
179 }; 124 };
180 125
181 &main_pmx0 { 126 &main_pmx0 {
182 main_uart8_pins_default: main-uart8-de 127 main_uart8_pins_default: main-uart8-default-pins {
183 pinctrl-single,pins = < 128 pinctrl-single,pins = <
184 J721S2_IOPAD(0x0d0, PI 129 J721S2_IOPAD(0x0d0, PIN_INPUT, 11) /* (AF26) SPI0_CS1.UART8_RXD */
185 J721S2_IOPAD(0x0d4, PI 130 J721S2_IOPAD(0x0d4, PIN_OUTPUT, 11) /* (AH27) SPI0_CLK.UART8_TXD */
186 >; 131 >;
187 }; 132 };
188 133
189 main_i2c0_pins_default: main-i2c0-defa 134 main_i2c0_pins_default: main-i2c0-default-pins {
190 pinctrl-single,pins = < 135 pinctrl-single,pins = <
191 J721S2_IOPAD(0x0e0, PI 136 J721S2_IOPAD(0x0e0, PIN_INPUT, 0) /* (AH25) I2C0_SCL */
192 J721S2_IOPAD(0x0e4, PI 137 J721S2_IOPAD(0x0e4, PIN_INPUT, 0) /* (AE24) I2C0_SDA */
193 >; 138 >;
194 }; 139 };
195 140
196 main_i2c1_pins_default: main-i2c1-defa <<
197 pinctrl-single,pins = < <<
198 J721S2_IOPAD(0x0ac, PI <<
199 J721S2_IOPAD(0x0b0, PI <<
200 >; <<
201 }; <<
202 <<
203 main_mmc1_pins_default: main-mmc1-defa 141 main_mmc1_pins_default: main-mmc1-default-pins {
204 pinctrl-single,pins = < 142 pinctrl-single,pins = <
205 J721S2_IOPAD(0x104, PI 143 J721S2_IOPAD(0x104, PIN_INPUT, 0) /* (P23) MMC1_CLK */
206 J721S2_IOPAD(0x108, PI 144 J721S2_IOPAD(0x108, PIN_INPUT, 0) /* (N24) MMC1_CMD */
207 J721S2_IOPAD(0x100, PI <<
208 J721S2_IOPAD(0x0fc, PI 145 J721S2_IOPAD(0x0fc, PIN_INPUT, 0) /* (M23) MMC1_DAT0 */
209 J721S2_IOPAD(0x0f8, PI 146 J721S2_IOPAD(0x0f8, PIN_INPUT, 0) /* (P24) MMC1_DAT1 */
210 J721S2_IOPAD(0x0f4, PI 147 J721S2_IOPAD(0x0f4, PIN_INPUT, 0) /* (R24) MMC1_DAT2 */
211 J721S2_IOPAD(0x0f0, PI 148 J721S2_IOPAD(0x0f0, PIN_INPUT, 0) /* (R22) MMC1_DAT3 */
212 J721S2_IOPAD(0x0e8, PI 149 J721S2_IOPAD(0x0e8, PIN_INPUT, 8) /* (AE25) TIMER_IO0.MMC1_SDCD */
213 >; 150 >;
214 }; 151 };
215 152
216 vdd_sd_dv_pins_default: vdd-sd-dv-defa 153 vdd_sd_dv_pins_default: vdd-sd-dv-default-pins {
217 pinctrl-single,pins = < 154 pinctrl-single,pins = <
218 J721S2_IOPAD(0x0c4, PI 155 J721S2_IOPAD(0x0c4, PIN_INPUT, 7) /* (AB26) ECAP0_IN_APWM_OUT.GPIO0_49 */
219 >; 156 >;
220 }; 157 };
221 158
222 main_usbss0_pins_default: main-usbss0- 159 main_usbss0_pins_default: main-usbss0-default-pins {
223 pinctrl-single,pins = < 160 pinctrl-single,pins = <
224 J721S2_IOPAD(0x0ec, PI 161 J721S2_IOPAD(0x0ec, PIN_OUTPUT, 6) /* (AG25) TIMER_IO1.USB0_DRVVBUS */
225 >; 162 >;
226 }; 163 };
227 164
228 main_mcan6_pins_default: main-mcan6-de 165 main_mcan6_pins_default: main-mcan6-default-pins {
229 pinctrl-single,pins = < 166 pinctrl-single,pins = <
230 J721S2_IOPAD(0x098, PI 167 J721S2_IOPAD(0x098, PIN_INPUT, 0) /* (V25) MCASP0_AXR10.MCAN6_RX */
231 J721S2_IOPAD(0x094, PI 168 J721S2_IOPAD(0x094, PIN_INPUT, 0) /* (AA25) MCASP0_AXR9.MCAN6_TX */
232 >; 169 >;
233 }; 170 };
234 171
235 main_mcan7_pins_default: main-mcan7-de 172 main_mcan7_pins_default: main-mcan7-default-pins {
236 pinctrl-single,pins = < 173 pinctrl-single,pins = <
237 J721S2_IOPAD(0x0a0, PI 174 J721S2_IOPAD(0x0a0, PIN_INPUT, 0) /* (AB25) MCASP0_AXR12.MCAN7_RX */
238 J721S2_IOPAD(0x09c, PI 175 J721S2_IOPAD(0x09c, PIN_INPUT, 0) /* (T24) MCASP0_AXR11.MCAN7_TX */
239 >; 176 >;
240 }; 177 };
241 178
242 main_i2c4_pins_default: main-i2c4-defa 179 main_i2c4_pins_default: main-i2c4-default-pins {
243 pinctrl-single,pins = < 180 pinctrl-single,pins = <
244 J721S2_IOPAD(0x010, PI 181 J721S2_IOPAD(0x010, PIN_INPUT_PULLUP, 8) /* (AF28) MCAN13_RX.I2C4_SDA */
245 J721S2_IOPAD(0x014, PI 182 J721S2_IOPAD(0x014, PIN_INPUT_PULLUP, 8) /* (AD25) MCAN14_TX.I2C4_SCL */
246 >; 183 >;
247 }; 184 };
248 185
249 rpi_header_gpio0_pins_default: rpi-hea 186 rpi_header_gpio0_pins_default: rpi-header-gpio0-default-pins {
250 pinctrl-single,pins = < 187 pinctrl-single,pins = <
251 J721S2_IOPAD(0x0a8, PI 188 J721S2_IOPAD(0x0a8, PIN_INPUT, 7) /* (U24) MCASP0_AXR14.GPIO0_42 */
252 J721S2_IOPAD(0x090, PI 189 J721S2_IOPAD(0x090, PIN_INPUT, 7) /* (W24) MCASP0_AXR8.GPIO0_36 */
253 J721S2_IOPAD(0x0bc, PI 190 J721S2_IOPAD(0x0bc, PIN_INPUT, 7) /* (V28) MCASP1_AFSX.GPIO0_47 */
254 J721S2_IOPAD(0x06c, PI 191 J721S2_IOPAD(0x06c, PIN_INPUT, 7) /* (V26) MCAN1_TX.GPIO0_27 */
255 J721S2_IOPAD(0x004, PI 192 J721S2_IOPAD(0x004, PIN_INPUT, 7) /* (W25) MCAN12_TX.GPIO0_1 */
256 J721S2_IOPAD(0x008, PI 193 J721S2_IOPAD(0x008, PIN_INPUT, 7) /* (AC24) MCAN12_RX.GPIO0_2 */
257 J721S2_IOPAD(0x0b8, PI 194 J721S2_IOPAD(0x0b8, PIN_INPUT, 7) /* (AA24) MCASP1_ACLKX.GPIO0_46 */
258 J721S2_IOPAD(0x00c, PI 195 J721S2_IOPAD(0x00c, PIN_INPUT, 7) /* (AE28) MCAN13_TX.GPIO0_3 */
259 J721S2_IOPAD(0x034, PI 196 J721S2_IOPAD(0x034, PIN_INPUT, 7) /* (AD24) PMIC_WAKE0.GPIO0_13 */
260 J721S2_IOPAD(0x0a4, PI 197 J721S2_IOPAD(0x0a4, PIN_INPUT, 7) /* (T23) MCASP0_AXR13.GPIO0_41 */
261 J721S2_IOPAD(0x0c0, PI 198 J721S2_IOPAD(0x0c0, PIN_INPUT, 7) /* (T28) MCASP1_AXR0.GPIO0_48 */
262 J721S2_IOPAD(0x0b4, PI 199 J721S2_IOPAD(0x0b4, PIN_INPUT, 7) /* (U25) MCASP1_AXR4.GPIO0_45 */
263 J721S2_IOPAD(0x0cc, PI 200 J721S2_IOPAD(0x0cc, PIN_INPUT, 7) /* (AE27) SPI0_CS0.GPIO0_51 */
264 J721S2_IOPAD(0x08c, PI 201 J721S2_IOPAD(0x08c, PIN_INPUT, 7) /* (T25) MCASP0_AXR7.GPIO0_35 */
265 >; 202 >;
266 }; 203 };
267 <<
268 dss_vout0_pins_default: dss-vout0-defa <<
269 pinctrl-single,pins = < <<
270 J721S2_IOPAD(0x074, PI <<
271 J721S2_IOPAD(0x070, PI <<
272 J721S2_IOPAD(0x04c, PI <<
273 J721S2_IOPAD(0x048, PI <<
274 J721S2_IOPAD(0x044, PI <<
275 J721S2_IOPAD(0x040, PI <<
276 J721S2_IOPAD(0x03c, PI <<
277 J721S2_IOPAD(0x038, PI <<
278 J721S2_IOPAD(0x0c8, PI <<
279 J721S2_IOPAD(0x030, PI <<
280 J721S2_IOPAD(0x02c, PI <<
281 J721S2_IOPAD(0x028, PI <<
282 J721S2_IOPAD(0x07c, PI <<
283 J721S2_IOPAD(0x024, PI <<
284 J721S2_IOPAD(0x020, PI <<
285 J721S2_IOPAD(0x01c, PI <<
286 J721S2_IOPAD(0x018, PI <<
287 J721S2_IOPAD(0x068, PI <<
288 J721S2_IOPAD(0x064, PI <<
289 J721S2_IOPAD(0x060, PI <<
290 J721S2_IOPAD(0x05c, PI <<
291 J721S2_IOPAD(0x058, PI <<
292 J721S2_IOPAD(0x054, PI <<
293 J721S2_IOPAD(0x050, PI <<
294 J721S2_IOPAD(0x084, PI <<
295 J721S2_IOPAD(0x080, PI <<
296 J721S2_IOPAD(0x078, PI <<
297 J721S2_IOPAD(0x088, PI <<
298 >; <<
299 }; <<
300 <<
301 hdmi_hpd_pins_default: hdmi-hpd-defaul <<
302 pinctrl-single,pins = < <<
303 J721S2_IOPAD(0x000, PI <<
304 >; <<
305 }; <<
306 }; 204 };
307 205
308 &wkup_pmx2 { 206 &wkup_pmx2 {
309 wkup_uart0_pins_default: wkup-uart0-de 207 wkup_uart0_pins_default: wkup-uart0-default-pins {
310 pinctrl-single,pins = < 208 pinctrl-single,pins = <
311 J721S2_WKUP_IOPAD(0x07 209 J721S2_WKUP_IOPAD(0x070, PIN_INPUT, 0) /* (E25) WKUP_GPIO0_6.WKUP_UART0_CTSn */
312 J721S2_WKUP_IOPAD(0x07 210 J721S2_WKUP_IOPAD(0x074, PIN_OUTPUT, 0) /* (F28) WKUP_GPIO0_7.WKUP_UART0_RTSn */
313 J721S2_WKUP_IOPAD(0x04 211 J721S2_WKUP_IOPAD(0x048, PIN_INPUT, 0) /* (D28) WKUP_UART0_RXD */
314 J721S2_WKUP_IOPAD(0x04 212 J721S2_WKUP_IOPAD(0x04c, PIN_OUTPUT, 0) /* (D27) WKUP_UART0_TXD */
315 >; 213 >;
316 }; 214 };
317 215
318 mcu_cpsw_pins_default: mcu-cpsw-defaul 216 mcu_cpsw_pins_default: mcu-cpsw-default-pins {
319 pinctrl-single,pins = < 217 pinctrl-single,pins = <
320 J721S2_WKUP_IOPAD(0x02 218 J721S2_WKUP_IOPAD(0x02C, PIN_INPUT, 0) /* (B22) MCU_RGMII1_RD0 */
321 J721S2_WKUP_IOPAD(0x02 219 J721S2_WKUP_IOPAD(0x028, PIN_INPUT, 0) /* (B21) MCU_RGMII1_RD1 */
322 J721S2_WKUP_IOPAD(0x02 220 J721S2_WKUP_IOPAD(0x024, PIN_INPUT, 0) /* (C22) MCU_RGMII1_RD2 */
323 J721S2_WKUP_IOPAD(0x02 221 J721S2_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (D23) MCU_RGMII1_RD3 */
324 J721S2_WKUP_IOPAD(0x01 222 J721S2_WKUP_IOPAD(0x01C, PIN_INPUT, 0) /* (D22) MCU_RGMII1_RXC */
325 J721S2_WKUP_IOPAD(0x00 223 J721S2_WKUP_IOPAD(0x004, PIN_INPUT, 0) /* (E23) MCU_RGMII1_RX_CTL */
326 J721S2_WKUP_IOPAD(0x01 224 J721S2_WKUP_IOPAD(0x014, PIN_OUTPUT, 0) /* (F23) MCU_RGMII1_TD0 */
327 J721S2_WKUP_IOPAD(0x01 225 J721S2_WKUP_IOPAD(0x010, PIN_OUTPUT, 0) /* (G22) MCU_RGMII1_TD1 */
328 J721S2_WKUP_IOPAD(0x00 226 J721S2_WKUP_IOPAD(0x00C, PIN_OUTPUT, 0) /* (E21) MCU_RGMII1_TD2 */
329 J721S2_WKUP_IOPAD(0x00 227 J721S2_WKUP_IOPAD(0x008, PIN_OUTPUT, 0) /* (E22) MCU_RGMII1_TD3 */
330 J721S2_WKUP_IOPAD(0x01 228 J721S2_WKUP_IOPAD(0x018, PIN_OUTPUT, 0) /* (F21) MCU_RGMII1_TXC */
331 J721S2_WKUP_IOPAD(0x00 229 J721S2_WKUP_IOPAD(0x000, PIN_OUTPUT, 0) /* (F22) MCU_RGMII1_TX_CTL */
332 >; 230 >;
333 }; 231 };
334 232
335 mcu_mdio_pins_default: mcu-mdio-defaul 233 mcu_mdio_pins_default: mcu-mdio-default-pins {
336 pinctrl-single,pins = < 234 pinctrl-single,pins = <
337 J721S2_WKUP_IOPAD(0x03 235 J721S2_WKUP_IOPAD(0x034, PIN_OUTPUT, 0) /* (A21) MCU_MDIO0_MDC */
338 J721S2_WKUP_IOPAD(0x03 236 J721S2_WKUP_IOPAD(0x030, PIN_INPUT, 0) /* (A22) MCU_MDIO0_MDIO */
339 >; 237 >;
340 }; 238 };
341 239
342 mcu_mcan0_pins_default: mcu-mcan0-defa 240 mcu_mcan0_pins_default: mcu-mcan0-default-pins {
343 pinctrl-single,pins = < 241 pinctrl-single,pins = <
344 J721S2_WKUP_IOPAD(0x05 242 J721S2_WKUP_IOPAD(0x054, PIN_INPUT, 0) /* (E28) MCU_MCAN0_RX */
345 J721S2_WKUP_IOPAD(0x05 243 J721S2_WKUP_IOPAD(0x050, PIN_OUTPUT, 0) /* (E27) MCU_MCAN0_TX */
346 >; 244 >;
347 }; 245 };
348 246
349 mcu_mcan1_pins_default: mcu-mcan1-defa 247 mcu_mcan1_pins_default: mcu-mcan1-default-pins {
350 pinctrl-single,pins = < 248 pinctrl-single,pins = <
351 J721S2_WKUP_IOPAD(0x06 249 J721S2_WKUP_IOPAD(0x06C, PIN_INPUT, 0) /* (F26) WKUP_GPIO0_5.MCU_MCAN1_RX */
352 J721S2_WKUP_IOPAD(0x06 250 J721S2_WKUP_IOPAD(0x068, PIN_OUTPUT, 0) /* (C23) WKUP_GPIO0_4.MCU_MCAN1_TX*/
353 >; 251 >;
354 }; 252 };
355 253
356 mcu_i2c0_pins_default: mcu-i2c0-defaul 254 mcu_i2c0_pins_default: mcu-i2c0-default-pins {
357 pinctrl-single,pins = < 255 pinctrl-single,pins = <
358 J721S2_WKUP_IOPAD(0x0a 256 J721S2_WKUP_IOPAD(0x0a0, PIN_INPUT, 0) /* (G24) MCU_I2C0_SCL */
359 J721S2_WKUP_IOPAD(0x0a 257 J721S2_WKUP_IOPAD(0x0a4, PIN_INPUT, 0) /* (J25) MCU_I2C0_SDA */
360 >; 258 >;
361 }; 259 };
362 260
363 mcu_i2c1_pins_default: mcu-i2c1-defaul 261 mcu_i2c1_pins_default: mcu-i2c1-default-pins {
364 pinctrl-single,pins = < 262 pinctrl-single,pins = <
365 J721S2_WKUP_IOPAD(0x07 263 J721S2_WKUP_IOPAD(0x078, PIN_INPUT, 0) /* (F24) WKUP_GPIO0_8.MCU_I2C1_SCL */
366 J721S2_WKUP_IOPAD(0x07 264 J721S2_WKUP_IOPAD(0x07c, PIN_INPUT, 0) /* (H26) WKUP_GPIO0_9.MCU_I2C1_SDA */
367 >; 265 >;
368 }; 266 };
369 267
370 mcu_uart0_pins_default: mcu-uart0-defa 268 mcu_uart0_pins_default: mcu-uart0-default-pins {
371 pinctrl-single,pins = < 269 pinctrl-single,pins = <
372 J721S2_WKUP_IOPAD(0x08 270 J721S2_WKUP_IOPAD(0x08c, PIN_INPUT, 0) /* (C24) WKUP_GPIO0_13.MCU_UART0_RXD */
373 J721S2_WKUP_IOPAD(0x08 271 J721S2_WKUP_IOPAD(0x088, PIN_OUTPUT, 0) /* (C25) WKUP_GPIO0_12.MCU_UART0_TXD */
374 >; 272 >;
375 }; 273 };
376 274
377 mcu_rpi_header_gpio0_pins0_default: mc !! 275 mcu_rpi_header_gpio0_pins0_default: mcu-rpi-header-gpio0-pins0-default {
378 pinctrl-single,pins = < 276 pinctrl-single,pins = <
379 J721S2_WKUP_IOPAD(0x11 277 J721S2_WKUP_IOPAD(0x118, PIN_INPUT, 7) /* (G25) WKUP_GPIO0_66 */
380 J721S2_WKUP_IOPAD(0x05 278 J721S2_WKUP_IOPAD(0x05C, PIN_INPUT, 7) /* (E24) MCU_SPI1_D0.WKUP_GPIO0_1 */
381 J721S2_WKUP_IOPAD(0x06 279 J721S2_WKUP_IOPAD(0x060, PIN_INPUT, 7) /* (C28) MCU_SPI1_D1.WKUP_GPIO0_2 */
382 J721S2_WKUP_IOPAD(0x05 280 J721S2_WKUP_IOPAD(0x058, PIN_INPUT, 7) /* (D26) MCU_SPI1_CLK.WKUP_GPIO0_0 */
383 J721S2_WKUP_IOPAD(0x09 281 J721S2_WKUP_IOPAD(0x094, PIN_INPUT, 7) /* (D25) MCU_SPI1_CS2.WKUP_GPIO0_15*/
384 J721S2_WKUP_IOPAD(0x0B 282 J721S2_WKUP_IOPAD(0x0B8, PIN_INPUT, 7) /* (G27) WKUP_GPIO0_56 */
385 J721S2_WKUP_IOPAD(0x11 283 J721S2_WKUP_IOPAD(0x114, PIN_INPUT, 7) /* (J26) WKUP_GPIO0_57 */
386 J721S2_WKUP_IOPAD(0x11 284 J721S2_WKUP_IOPAD(0x11C, PIN_INPUT, 7) /* (J27) WKUP_GPIO0_67 */
387 J721S2_WKUP_IOPAD(0x06 285 J721S2_WKUP_IOPAD(0x064, PIN_INPUT, 7) /* (C27) MCU_SPI1_CS0.WKUP_GPIO0_3 */
388 >; 286 >;
389 }; 287 };
390 }; 288 };
391 289
392 &wkup_pmx3 { 290 &wkup_pmx3 {
393 mcu_rpi_header_gpio0_pins1_default: mc !! 291 mcu_rpi_header_gpio0_pins1_default: mcu-rpi-header-gpio0-pins1-default {
394 pinctrl-single,pins = < 292 pinctrl-single,pins = <
395 J721S2_WKUP_IOPAD(0x00 293 J721S2_WKUP_IOPAD(0x000, PIN_INPUT, 7) /* (K26) WKUP_GPIO0_49 */
396 >; 294 >;
397 }; 295 };
398 }; 296 };
399 297
400 &main_gpio0 { 298 &main_gpio0 {
401 status = "okay"; <<
402 pinctrl-names = "default"; 299 pinctrl-names = "default";
403 pinctrl-0 = <&rpi_header_gpio0_pins_de 300 pinctrl-0 = <&rpi_header_gpio0_pins_default>;
404 }; 301 };
405 302
>> 303 &main_gpio2 {
>> 304 status = "disabled";
>> 305 };
>> 306
>> 307 &main_gpio4 {
>> 308 status = "disabled";
>> 309 };
>> 310
>> 311 &main_gpio6 {
>> 312 status = "disabled";
>> 313 };
>> 314
406 &wkup_gpio0 { 315 &wkup_gpio0 {
407 status = "okay"; <<
408 pinctrl-names = "default"; 316 pinctrl-names = "default";
409 pinctrl-0 = <&mcu_rpi_header_gpio0_pin 317 pinctrl-0 = <&mcu_rpi_header_gpio0_pins0_default>, <&mcu_rpi_header_gpio0_pins1_default>;
410 }; 318 };
411 319
>> 320 &wkup_gpio1 {
>> 321 status = "disabled";
>> 322 };
>> 323
412 &wkup_uart0 { 324 &wkup_uart0 {
413 status = "reserved"; 325 status = "reserved";
414 pinctrl-names = "default"; 326 pinctrl-names = "default";
415 pinctrl-0 = <&wkup_uart0_pins_default> 327 pinctrl-0 = <&wkup_uart0_pins_default>;
416 }; 328 };
417 329
418 &wkup_i2c0 { <<
419 bootph-all; <<
420 clock-frequency = <400000>; <<
421 pinctrl-names = "default"; <<
422 pinctrl-0 = <&wkup_i2c0_pins_default>; <<
423 status = "okay"; <<
424 <<
425 lp8733: pmic@60 { <<
426 compatible = "ti,lp8733"; <<
427 reg = <0x60>; <<
428 buck0-in-supply = <&vsys_3v3>; <<
429 buck1-in-supply = <&vsys_3v3>; <<
430 ldo0-in-supply = <&vsys_3v3>; <<
431 ldo1-in-supply = <&vsys_3v3>; <<
432 <<
433 lp8733_regulators: regulators <<
434 lp8733_buck0_reg: buck <<
435 /* FB_B0 -> LP <<
436 regulator-name <<
437 regulator-min- <<
438 regulator-max- <<
439 regulator-alwa <<
440 regulator-boot <<
441 }; <<
442 <<
443 lp8733_buck1_reg: buck <<
444 /* FB_B1 -> LP <<
445 regulator-name <<
446 regulator-min- <<
447 regulator-max- <<
448 regulator-alwa <<
449 regulator-boot <<
450 }; <<
451 <<
452 lp8733_ldo0_reg: ldo0 <<
453 /* LDO0 -> LP8 <<
454 regulator-name <<
455 regulator-min- <<
456 regulator-max- <<
457 regulator-boot <<
458 regulator-alwa <<
459 }; <<
460 <<
461 lp8733_ldo1_reg: ldo1 <<
462 /* LDO1 -> LP8 <<
463 regulator-name <<
464 regulator-min- <<
465 regulator-max- <<
466 regulator-alwa <<
467 regulator-boot <<
468 }; <<
469 }; <<
470 }; <<
471 <<
472 tps62873a: regulator@40 { <<
473 compatible = "ti,tps62873"; <<
474 reg = <0x40>; <<
475 bootph-pre-ram; <<
476 regulator-name = "VDD_CPU_AVS" <<
477 regulator-min-microvolt = <600 <<
478 regulator-max-microvolt = <900 <<
479 regulator-boot-on; <<
480 regulator-always-on; <<
481 }; <<
482 <<
483 tps62873b: regulator@43 { <<
484 compatible = "ti,tps62873"; <<
485 reg = <0x43>; <<
486 regulator-name = "VDD_CORE_0V8 <<
487 regulator-min-microvolt = <800 <<
488 regulator-max-microvolt = <800 <<
489 regulator-boot-on; <<
490 regulator-always-on; <<
491 }; <<
492 }; <<
493 <<
494 &mcu_uart0 { 330 &mcu_uart0 {
495 status = "okay"; 331 status = "okay";
496 pinctrl-names = "default"; 332 pinctrl-names = "default";
497 pinctrl-0 = <&mcu_uart0_pins_default>; 333 pinctrl-0 = <&mcu_uart0_pins_default>;
498 }; 334 };
499 335
500 &main_uart8 { 336 &main_uart8 {
501 status = "okay"; 337 status = "okay";
502 pinctrl-names = "default"; 338 pinctrl-names = "default";
503 pinctrl-0 = <&main_uart8_pins_default> 339 pinctrl-0 = <&main_uart8_pins_default>;
504 /* Shared with TFA on this platform */ 340 /* Shared with TFA on this platform */
505 power-domains = <&k3_pds 357 TI_SCI_PD 341 power-domains = <&k3_pds 357 TI_SCI_PD_SHARED>;
506 }; 342 };
507 343
508 &main_i2c0 { 344 &main_i2c0 {
509 pinctrl-names = "default"; 345 pinctrl-names = "default";
510 pinctrl-0 = <&main_i2c0_pins_default>; 346 pinctrl-0 = <&main_i2c0_pins_default>;
511 clock-frequency = <400000>; 347 clock-frequency = <400000>;
512 348
513 exp1: gpio@21 { 349 exp1: gpio@21 {
514 compatible = "ti,tca6416"; 350 compatible = "ti,tca6416";
515 reg = <0x21>; 351 reg = <0x21>;
516 gpio-controller; 352 gpio-controller;
517 #gpio-cells = <2>; 353 #gpio-cells = <2>;
518 gpio-line-names = " ", " ", " 354 gpio-line-names = " ", " ", " ", " ", " ",
519 "BOARDID_EEP 355 "BOARDID_EEPROM_WP", "CAN_STB", " ",
520 "GPIO_uSD_PW 356 "GPIO_uSD_PWR_EN", " ", "IO_EXP_PCIe1_M.2_RTSz",
521 "IO_EXP_MCU_ 357 "IO_EXP_MCU_RGMII_RST#", " ", " ", " ", " ";
522 }; 358 };
523 }; 359 };
524 360
525 &main_i2c1 { <<
526 pinctrl-names = "default"; <<
527 pinctrl-0 = <&main_i2c1_pins_default>; <<
528 status = "okay"; <<
529 <<
530 exp3: gpio@20 { <<
531 compatible = "ti,tca6408"; <<
532 reg = <0x20>; <<
533 gpio-controller; <<
534 #gpio-cells = <2>; <<
535 gpio-line-names = "CSI_VIO_SEL <<
536 "IO_EXP_CSI2 <<
537 "CSI1_B_GPIO <<
538 }; <<
539 <<
540 i2c-mux@70 { <<
541 compatible = "nxp,pca9543"; <<
542 #address-cells = <1>; <<
543 #size-cells = <0>; <<
544 reg = <0x70>; <<
545 <<
546 cam0_i2c: i2c@0 { <<
547 #address-cells = <1>; <<
548 #size-cells = <0>; <<
549 reg = <0>; <<
550 }; <<
551 <<
552 cam1_i2c: i2c@1 { <<
553 #address-cells = <1>; <<
554 #size-cells = <0>; <<
555 reg = <1>; <<
556 }; <<
557 <<
558 }; <<
559 }; <<
560 <<
561 &main_i2c4 { 361 &main_i2c4 {
562 status = "okay"; 362 status = "okay";
563 pinctrl-names = "default"; 363 pinctrl-names = "default";
564 pinctrl-0 = <&main_i2c4_pins_default>; 364 pinctrl-0 = <&main_i2c4_pins_default>;
565 clock-frequency = <400000>; 365 clock-frequency = <400000>;
566 }; 366 };
567 367
568 &mcu_i2c0 { 368 &mcu_i2c0 {
569 status = "okay"; 369 status = "okay";
570 pinctrl-names = "default"; 370 pinctrl-names = "default";
571 pinctrl-0 = <&mcu_i2c0_pins_default>; 371 pinctrl-0 = <&mcu_i2c0_pins_default>;
572 clock-frequency = <400000>; 372 clock-frequency = <400000>;
573 }; 373 };
574 374
575 &mcu_i2c1 { !! 375 &main_sdhci0 {
576 status = "okay"; !! 376 /* Unused */
577 pinctrl-names = "default"; !! 377 status = "disabled";
578 pinctrl-0 = <&mcu_i2c1_pins_default>; <<
579 /* i2c1 is used for DVI DDC, so we nee <<
580 clock-frequency = <100000>; <<
581 <<
582 exp2: gpio@20 { <<
583 compatible = "ti,tca6408"; <<
584 reg = <0x20>; <<
585 gpio-controller; <<
586 #gpio-cells = <2>; <<
587 gpio-line-names = "HDMI_PDn"," <<
588 "DP0_3V3_EN" <<
589 }; <<
590 }; 378 };
591 379
592 &main_sdhci1 { 380 &main_sdhci1 {
593 /* SD card */ 381 /* SD card */
594 status = "okay"; <<
595 pinctrl-0 = <&main_mmc1_pins_default>; 382 pinctrl-0 = <&main_mmc1_pins_default>;
596 pinctrl-names = "default"; 383 pinctrl-names = "default";
597 disable-wp; 384 disable-wp;
598 vmmc-supply = <&vdd_mmc1>; 385 vmmc-supply = <&vdd_mmc1>;
599 vqmmc-supply = <&vdd_sd_dv>; 386 vqmmc-supply = <&vdd_sd_dv>;
600 }; 387 };
601 388
602 &mcu_cpsw { 389 &mcu_cpsw {
603 pinctrl-names = "default"; 390 pinctrl-names = "default";
604 pinctrl-0 = <&mcu_cpsw_pins_default>, 391 pinctrl-0 = <&mcu_cpsw_pins_default>, <&mcu_mdio_pins_default>;
605 }; 392 };
606 393
607 &davinci_mdio { 394 &davinci_mdio {
608 phy0: ethernet-phy@0 { 395 phy0: ethernet-phy@0 {
609 reg = <0>; 396 reg = <0>;
610 ti,rx-internal-delay = <DP8386 397 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
611 ti,fifo-depth = <DP83867_PHYCR 398 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
612 ti,min-output-impedance; 399 ti,min-output-impedance;
613 }; 400 };
614 }; 401 };
615 402
616 &cpsw_port1 { 403 &cpsw_port1 {
617 phy-mode = "rgmii-rxid"; 404 phy-mode = "rgmii-rxid";
618 phy-handle = <&phy0>; 405 phy-handle = <&phy0>;
619 }; 406 };
620 407
621 &mcu_mcan0 { 408 &mcu_mcan0 {
622 status = "okay"; 409 status = "okay";
623 pinctrl-names = "default"; 410 pinctrl-names = "default";
624 pinctrl-0 = <&mcu_mcan0_pins_default>; 411 pinctrl-0 = <&mcu_mcan0_pins_default>;
625 phys = <&transceiver1>; 412 phys = <&transceiver1>;
626 }; 413 };
627 414
628 &mcu_mcan1 { 415 &mcu_mcan1 {
629 status = "okay"; 416 status = "okay";
630 pinctrl-names = "default"; 417 pinctrl-names = "default";
631 pinctrl-0 = <&mcu_mcan1_pins_default>; 418 pinctrl-0 = <&mcu_mcan1_pins_default>;
632 phys = <&transceiver2>; 419 phys = <&transceiver2>;
633 }; 420 };
634 421
635 &main_mcan6 { 422 &main_mcan6 {
636 status = "okay"; 423 status = "okay";
637 pinctrl-names = "default"; 424 pinctrl-names = "default";
638 pinctrl-0 = <&main_mcan6_pins_default> 425 pinctrl-0 = <&main_mcan6_pins_default>;
639 phys = <&transceiver3>; 426 phys = <&transceiver3>;
640 }; 427 };
641 428
642 &main_mcan7 { 429 &main_mcan7 {
643 status = "okay"; 430 status = "okay";
644 pinctrl-names = "default"; 431 pinctrl-names = "default";
645 pinctrl-0 = <&main_mcan7_pins_default> 432 pinctrl-0 = <&main_mcan7_pins_default>;
646 phys = <&transceiver4>; 433 phys = <&transceiver4>;
647 }; <<
648 <<
649 &dss { <<
650 status = "okay"; <<
651 pinctrl-names = "default"; <<
652 pinctrl-0 = <&dss_vout0_pins_default>; <<
653 /* <<
654 * These clock assignments are chosen <<
655 * <<
656 * VP0 - DisplayPort SST <<
657 * VP1 - DPI0 <<
658 * VP2 - DSI <<
659 * VP3 - DPI1 <<
660 */ <<
661 assigned-clocks = <&k3_clks 158 2>, <<
662 <&k3_clks 158 5>, <<
663 <&k3_clks 158 14>, <<
664 <&k3_clks 158 18>; <<
665 assigned-clock-parents = <&k3_clks 158 <<
666 <&k3_clks 158 <<
667 <&k3_clks 158 <<
668 <&k3_clks 158 <<
669 }; <<
670 <<
671 &dss_ports { <<
672 #address-cells = <1>; <<
673 #size-cells = <0>; <<
674 <<
675 /* HDMI */ <<
676 port@1 { <<
677 reg = <1>; <<
678 <<
679 dpi_out0: endpoint { <<
680 remote-endpoint = <&tf <<
681 }; <<
682 }; <<
683 }; <<
684 <<
685 &serdes_ln_ctrl { <<
686 idle-states = <J721S2_SERDES0_LANE0_PC <<
687 <J721S2_SERDES0_LANE2_US <<
688 }; <<
689 <<
690 &serdes_refclk { <<
691 clock-frequency = <100000000>; <<
692 }; <<
693 <<
694 &serdes0 { <<
695 status = "okay"; <<
696 <<
697 serdes0_pcie_link: phy@0 { <<
698 reg = <0>; <<
699 cdns,num-lanes = <2>; <<
700 #phy-cells = <0>; <<
701 cdns,phy-type = <PHY_TYPE_PCIE <<
702 resets = <&serdes_wiz0 1>, <&s <<
703 }; <<
704 <<
705 serdes0_usb_link: phy@2 { <<
706 status = "okay"; <<
707 reg = <2>; <<
708 cdns,num-lanes = <1>; <<
709 #phy-cells = <0>; <<
710 cdns,phy-type = <PHY_TYPE_USB3 <<
711 resets = <&serdes_wiz0 3>; <<
712 }; <<
713 }; <<
714 <<
715 &pcie1_rc { <<
716 status = "okay"; <<
717 reset-gpios = <&exp1 10 GPIO_ACTIVE_HI <<
718 phys = <&serdes0_pcie_link>; <<
719 phy-names = "pcie-phy"; <<
720 num-lanes = <2>; <<
721 }; <<
722 <<
723 &usb_serdes_mux { <<
724 idle-states = <0>; /* USB0 to SERDES l <<
725 }; <<
726 <<
727 &usbss0 { <<
728 status = "okay"; <<
729 pinctrl-0 = <&main_usbss0_pins_default <<
730 pinctrl-names = "default"; <<
731 ti,vbus-divider; <<
732 }; <<
733 <<
734 &usb0 { <<
735 dr_mode = "host"; <<
736 maximum-speed = "super-speed"; <<
737 phys = <&serdes0_usb_link>; <<
738 phy-names = "cdns3,usb3-phy"; <<
739 }; 434 };
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