1 // SPDX-License-Identifier: GPL-2.0-only OR MI 1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
2 /* 2 /*
3 * Copyright (C) 2023-2024 Texas Instruments I 3 * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/
4 */ 4 */
5 5
6 /dts-v1/; 6 /dts-v1/;
7 7
8 #include "k3-j721s2.dtsi" 8 #include "k3-j721s2.dtsi"
9 #include <dt-bindings/gpio/gpio.h> 9 #include <dt-bindings/gpio/gpio.h>
10 10
11 / { 11 / {
12 memory@80000000 { 12 memory@80000000 {
13 device_type = "memory"; 13 device_type = "memory";
14 bootph-all; 14 bootph-all;
15 /* 16 GB RAM */ 15 /* 16 GB RAM */
16 reg = <0x00000000 0x80000000 0 16 reg = <0x00000000 0x80000000 0x00000000 0x80000000>,
17 <0x00000008 0x80000000 0 17 <0x00000008 0x80000000 0x00000003 0x80000000>;
18 }; 18 };
19 19
20 reserved_memory: reserved-memory { 20 reserved_memory: reserved-memory {
21 #address-cells = <2>; 21 #address-cells = <2>;
22 #size-cells = <2>; 22 #size-cells = <2>;
23 ranges; 23 ranges;
24 24
25 secure_ddr: optee@9e800000 { 25 secure_ddr: optee@9e800000 {
26 reg = <0x00 0x9e800000 26 reg = <0x00 0x9e800000 0x00 0x01800000>;
27 no-map; 27 no-map;
28 }; 28 };
29 29
30 mcu_r5fss0_core0_dma_memory_re 30 mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 {
31 compatible = "shared-d 31 compatible = "shared-dma-pool";
32 reg = <0x00 0xa0000000 32 reg = <0x00 0xa0000000 0x00 0x100000>;
33 no-map; 33 no-map;
34 }; 34 };
35 35
36 mcu_r5fss0_core0_memory_region 36 mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 {
37 compatible = "shared-d 37 compatible = "shared-dma-pool";
38 reg = <0x00 0xa0100000 38 reg = <0x00 0xa0100000 0x00 0xf00000>;
39 no-map; 39 no-map;
40 }; 40 };
41 41
42 mcu_r5fss0_core1_dma_memory_re 42 mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 {
43 compatible = "shared-d 43 compatible = "shared-dma-pool";
44 reg = <0x00 0xa1000000 44 reg = <0x00 0xa1000000 0x00 0x100000>;
45 no-map; 45 no-map;
46 }; 46 };
47 47
48 mcu_r5fss0_core1_memory_region 48 mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 {
49 compatible = "shared-d 49 compatible = "shared-dma-pool";
50 reg = <0x00 0xa1100000 50 reg = <0x00 0xa1100000 0x00 0xf00000>;
51 no-map; 51 no-map;
52 }; 52 };
53 53
54 main_r5fss0_core0_dma_memory_r 54 main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a2000000 {
55 compatible = "shared-d 55 compatible = "shared-dma-pool";
56 reg = <0x00 0xa2000000 56 reg = <0x00 0xa2000000 0x00 0x100000>;
57 no-map; 57 no-map;
58 }; 58 };
59 59
60 main_r5fss0_core0_memory_regio 60 main_r5fss0_core0_memory_region: r5f-memory@a2100000 {
61 compatible = "shared-d 61 compatible = "shared-dma-pool";
62 reg = <0x00 0xa2100000 62 reg = <0x00 0xa2100000 0x00 0xf00000>;
63 no-map; 63 no-map;
64 }; 64 };
65 65
66 main_r5fss0_core1_dma_memory_r 66 main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a3000000 {
67 compatible = "shared-d 67 compatible = "shared-dma-pool";
68 reg = <0x00 0xa3000000 68 reg = <0x00 0xa3000000 0x00 0x100000>;
69 no-map; 69 no-map;
70 }; 70 };
71 71
72 main_r5fss0_core1_memory_regio 72 main_r5fss0_core1_memory_region: r5f-memory@a3100000 {
73 compatible = "shared-d 73 compatible = "shared-dma-pool";
74 reg = <0x00 0xa3100000 74 reg = <0x00 0xa3100000 0x00 0xf00000>;
75 no-map; 75 no-map;
76 }; 76 };
77 77
78 main_r5fss1_core0_dma_memory_r 78 main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a4000000 {
79 compatible = "shared-d 79 compatible = "shared-dma-pool";
80 reg = <0x00 0xa4000000 80 reg = <0x00 0xa4000000 0x00 0x100000>;
81 no-map; 81 no-map;
82 }; 82 };
83 83
84 main_r5fss1_core0_memory_regio 84 main_r5fss1_core0_memory_region: r5f-memory@a4100000 {
85 compatible = "shared-d 85 compatible = "shared-dma-pool";
86 reg = <0x00 0xa4100000 86 reg = <0x00 0xa4100000 0x00 0xf00000>;
87 no-map; 87 no-map;
88 }; 88 };
89 89
90 main_r5fss1_core1_dma_memory_r 90 main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a5000000 {
91 compatible = "shared-d 91 compatible = "shared-dma-pool";
92 reg = <0x00 0xa5000000 92 reg = <0x00 0xa5000000 0x00 0x100000>;
93 no-map; 93 no-map;
94 }; 94 };
95 95
96 main_r5fss1_core1_memory_regio 96 main_r5fss1_core1_memory_region: r5f-memory@a5100000 {
97 compatible = "shared-d 97 compatible = "shared-dma-pool";
98 reg = <0x00 0xa5100000 98 reg = <0x00 0xa5100000 0x00 0xf00000>;
99 no-map; 99 no-map;
100 }; 100 };
101 101
102 c71_0_dma_memory_region: c71-d 102 c71_0_dma_memory_region: c71-dma-memory@a6000000 {
103 compatible = "shared-d 103 compatible = "shared-dma-pool";
104 reg = <0x00 0xa6000000 104 reg = <0x00 0xa6000000 0x00 0x100000>;
105 no-map; 105 no-map;
106 }; 106 };
107 107
108 c71_0_memory_region: c71-memor 108 c71_0_memory_region: c71-memory@a6100000 {
109 compatible = "shared-d 109 compatible = "shared-dma-pool";
110 reg = <0x00 0xa6100000 110 reg = <0x00 0xa6100000 0x00 0xf00000>;
111 no-map; 111 no-map;
112 }; 112 };
113 113
114 c71_1_dma_memory_region: c71-d 114 c71_1_dma_memory_region: c71-dma-memory@a7000000 {
115 compatible = "shared-d 115 compatible = "shared-dma-pool";
116 reg = <0x00 0xa7000000 116 reg = <0x00 0xa7000000 0x00 0x100000>;
117 no-map; 117 no-map;
118 }; 118 };
119 119
120 c71_1_memory_region: c71-memor 120 c71_1_memory_region: c71-memory@a7100000 {
121 compatible = "shared-d 121 compatible = "shared-dma-pool";
122 reg = <0x00 0xa7100000 122 reg = <0x00 0xa7100000 0x00 0xf00000>;
123 no-map; 123 no-map;
124 }; 124 };
125 125
126 rtos_ipc_memory_region: ipc-me 126 rtos_ipc_memory_region: ipc-memories@a8000000 {
127 reg = <0x00 0xa8000000 127 reg = <0x00 0xa8000000 0x00 0x01c00000>;
128 alignment = <0x1000>; 128 alignment = <0x1000>;
129 no-map; 129 no-map;
130 }; 130 };
131 }; 131 };
132 }; 132 };
133 133
134 &wkup_pmx0 { 134 &wkup_pmx0 {
135 mcu_fss0_ospi0_pins_default: mcu-fss0- 135 mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-pins {
136 bootph-all; 136 bootph-all;
137 pinctrl-single,pins = < 137 pinctrl-single,pins = <
138 J721S2_WKUP_IOPAD(0x00 138 J721S2_WKUP_IOPAD(0x000, PIN_OUTPUT, 0) /* (D19) MCU_OSPI0_CLK */
139 J721S2_WKUP_IOPAD(0x02 139 J721S2_WKUP_IOPAD(0x02c, PIN_OUTPUT, 0) /* (F15) MCU_OSPI0_CSn0 */
140 J721S2_WKUP_IOPAD(0x00 140 J721S2_WKUP_IOPAD(0x00c, PIN_INPUT, 0) /* (C19) MCU_OSPI0_D0 */
141 J721S2_WKUP_IOPAD(0x01 141 J721S2_WKUP_IOPAD(0x010, PIN_INPUT, 0) /* (F16) MCU_OSPI0_D1 */
142 J721S2_WKUP_IOPAD(0x01 142 J721S2_WKUP_IOPAD(0x014, PIN_INPUT, 0) /* (G15) MCU_OSPI0_D2 */
143 J721S2_WKUP_IOPAD(0x01 143 J721S2_WKUP_IOPAD(0x018, PIN_INPUT, 0) /* (F18) MCU_OSPI0_D3 */
144 J721S2_WKUP_IOPAD(0x01 144 J721S2_WKUP_IOPAD(0x01c, PIN_INPUT, 0) /* (E19) MCU_OSPI0_D4 */
145 J721S2_WKUP_IOPAD(0x02 145 J721S2_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (G19) MCU_OSPI0_D5 */
146 J721S2_WKUP_IOPAD(0x02 146 J721S2_WKUP_IOPAD(0x024, PIN_INPUT, 0) /* (F19) MCU_OSPI0_D6 */
147 J721S2_WKUP_IOPAD(0x02 147 J721S2_WKUP_IOPAD(0x028, PIN_INPUT, 0) /* (F20) MCU_OSPI0_D7 */
148 J721S2_WKUP_IOPAD(0x00 148 J721S2_WKUP_IOPAD(0x008, PIN_INPUT, 0) /* (E18) MCU_OSPI0_DQS */
149 >; 149 >;
150 }; 150 };
151 }; 151 };
152 152
153 &wkup_pmx2 { 153 &wkup_pmx2 {
154 wkup_i2c0_pins_default: wkup-i2c0-defa 154 wkup_i2c0_pins_default: wkup-i2c0-default-pins {
155 pinctrl-single,pins = < 155 pinctrl-single,pins = <
156 J721S2_WKUP_IOPAD(0x09 156 J721S2_WKUP_IOPAD(0x098, PIN_INPUT, 0) /* (H24) WKUP_I2C0_SCL */
157 J721S2_WKUP_IOPAD(0x09 157 J721S2_WKUP_IOPAD(0x09c, PIN_INPUT, 0) /* (H27) WKUP_I2C0_SDA */
158 >; 158 >;
159 }; 159 };
160 }; 160 };
161 161
162 &wkup_i2c0 { 162 &wkup_i2c0 {
163 status = "okay"; 163 status = "okay";
164 pinctrl-names = "default"; 164 pinctrl-names = "default";
165 pinctrl-0 = <&wkup_i2c0_pins_default>; 165 pinctrl-0 = <&wkup_i2c0_pins_default>;
166 clock-frequency = <400000>; 166 clock-frequency = <400000>;
167 167
168 eeprom@51 { 168 eeprom@51 {
169 /* AT24C512C-MAHM-T */ 169 /* AT24C512C-MAHM-T */
170 compatible = "atmel,24c512"; 170 compatible = "atmel,24c512";
171 reg = <0x51>; 171 reg = <0x51>;
172 }; 172 };
173 }; 173 };
174 174
175 &ospi0 { 175 &ospi0 {
176 status = "okay"; 176 status = "okay";
177 pinctrl-names = "default"; 177 pinctrl-names = "default";
178 pinctrl-0 = <&mcu_fss0_ospi0_pins_defa 178 pinctrl-0 = <&mcu_fss0_ospi0_pins_default>;
179 179
180 flash@0 { 180 flash@0 {
181 compatible = "jedec,spi-nor"; 181 compatible = "jedec,spi-nor";
182 reg = <0x0>; 182 reg = <0x0>;
183 spi-tx-bus-width = <8>; 183 spi-tx-bus-width = <8>;
184 spi-rx-bus-width = <8>; 184 spi-rx-bus-width = <8>;
185 spi-max-frequency = <25000000> 185 spi-max-frequency = <25000000>;
186 cdns,tshsl-ns = <60>; 186 cdns,tshsl-ns = <60>;
187 cdns,tsd2d-ns = <60>; 187 cdns,tsd2d-ns = <60>;
188 cdns,tchsh-ns = <60>; 188 cdns,tchsh-ns = <60>;
189 cdns,tslch-ns = <60>; 189 cdns,tslch-ns = <60>;
190 cdns,read-delay = <4>; 190 cdns,read-delay = <4>;
191 191
192 partitions { 192 partitions {
193 bootph-all; 193 bootph-all;
194 compatible = "fixed-pa 194 compatible = "fixed-partitions";
195 #address-cells = <1>; 195 #address-cells = <1>;
196 #size-cells = <1>; 196 #size-cells = <1>;
197 197
198 partition@0 { 198 partition@0 {
199 label = "ospi. 199 label = "ospi.tiboot3";
200 reg = <0x0 0x8 200 reg = <0x0 0x80000>;
201 }; 201 };
202 202
203 partition@80000 { 203 partition@80000 {
204 label = "ospi. 204 label = "ospi.tispl";
205 reg = <0x80000 205 reg = <0x80000 0x200000>;
206 }; 206 };
207 207
208 partition@280000 { 208 partition@280000 {
209 label = "ospi. 209 label = "ospi.u-boot";
210 reg = <0x28000 210 reg = <0x280000 0x400000>;
211 }; 211 };
212 212
213 partition@680000 { 213 partition@680000 {
214 label = "ospi. 214 label = "ospi.env";
215 reg = <0x68000 215 reg = <0x680000 0x40000>;
216 }; 216 };
217 217
218 partition@6c0000 { 218 partition@6c0000 {
219 label = "ospi. 219 label = "ospi.env.backup";
220 reg = <0x6c000 220 reg = <0x6c0000 0x40000>;
221 }; 221 };
222 222
223 partition@800000 { 223 partition@800000 {
224 label = "ospi. 224 label = "ospi.rootfs";
225 reg = <0x80000 225 reg = <0x800000 0x37c0000>;
226 }; 226 };
227 227
228 partition@3fc0000 { 228 partition@3fc0000 {
229 bootph-pre-ram 229 bootph-pre-ram;
230 label = "ospi. 230 label = "ospi.phypattern";
231 reg = <0x3fc00 231 reg = <0x3fc0000 0x40000>;
232 }; 232 };
233 }; 233 };
234 }; 234 };
235 }; 235 };
236 236
237 &mailbox0_cluster0 { 237 &mailbox0_cluster0 {
238 status = "okay"; 238 status = "okay";
239 interrupts = <436>; 239 interrupts = <436>;
240 mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0 240 mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 {
241 ti,mbox-rx = <0 0 0>; 241 ti,mbox-rx = <0 0 0>;
242 ti,mbox-tx = <1 0 0>; 242 ti,mbox-tx = <1 0 0>;
243 }; 243 };
244 244
245 mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0 245 mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 {
246 ti,mbox-rx = <2 0 0>; 246 ti,mbox-rx = <2 0 0>;
247 ti,mbox-tx = <3 0 0>; 247 ti,mbox-tx = <3 0 0>;
248 }; 248 };
249 }; 249 };
250 250
251 &mailbox0_cluster1 { 251 &mailbox0_cluster1 {
252 status = "okay"; 252 status = "okay";
253 interrupts = <432>; 253 interrupts = <432>;
254 mbox_main_r5fss0_core0: mbox-main-r5fs 254 mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
255 ti,mbox-rx = <0 0 0>; 255 ti,mbox-rx = <0 0 0>;
256 ti,mbox-tx = <1 0 0>; 256 ti,mbox-tx = <1 0 0>;
257 }; 257 };
258 258
259 mbox_main_r5fss0_core1: mbox-main-r5fs 259 mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 {
260 ti,mbox-rx = <2 0 0>; 260 ti,mbox-rx = <2 0 0>;
261 ti,mbox-tx = <3 0 0>; 261 ti,mbox-tx = <3 0 0>;
262 }; 262 };
263 }; 263 };
264 264
265 &mailbox0_cluster2 { 265 &mailbox0_cluster2 {
266 status = "okay"; 266 status = "okay";
267 interrupts = <428>; 267 interrupts = <428>;
268 mbox_main_r5fss1_core0: mbox-main-r5fs 268 mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 {
269 ti,mbox-rx = <0 0 0>; 269 ti,mbox-rx = <0 0 0>;
270 ti,mbox-tx = <1 0 0>; 270 ti,mbox-tx = <1 0 0>;
271 }; 271 };
272 272
273 mbox_main_r5fss1_core1: mbox-main-r5fs 273 mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 {
274 ti,mbox-rx = <2 0 0>; 274 ti,mbox-rx = <2 0 0>;
275 ti,mbox-tx = <3 0 0>; 275 ti,mbox-tx = <3 0 0>;
276 }; 276 };
277 }; 277 };
278 278
279 &mailbox0_cluster4 { 279 &mailbox0_cluster4 {
280 status = "okay"; 280 status = "okay";
281 interrupts = <420>; 281 interrupts = <420>;
282 mbox_c71_0: mbox-c71-0 { 282 mbox_c71_0: mbox-c71-0 {
283 ti,mbox-rx = <0 0 0>; 283 ti,mbox-rx = <0 0 0>;
284 ti,mbox-tx = <1 0 0>; 284 ti,mbox-tx = <1 0 0>;
285 }; 285 };
286 286
287 mbox_c71_1: mbox-c71-1 { 287 mbox_c71_1: mbox-c71-1 {
288 ti,mbox-rx = <2 0 0>; 288 ti,mbox-rx = <2 0 0>;
289 ti,mbox-tx = <3 0 0>; 289 ti,mbox-tx = <3 0 0>;
290 }; 290 };
291 }; 291 };
292 292
293 &mcu_r5fss0_core0 { 293 &mcu_r5fss0_core0 {
294 mboxes = <&mailbox0_cluster0 &mbox_mcu 294 mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>;
295 memory-region = <&mcu_r5fss0_core0_dma 295 memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
296 <&mcu_r5fss0_core0_mem 296 <&mcu_r5fss0_core0_memory_region>;
297 }; 297 };
298 298
299 &mcu_r5fss0_core1 { 299 &mcu_r5fss0_core1 {
300 mboxes = <&mailbox0_cluster0 &mbox_mcu 300 mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>;
301 memory-region = <&mcu_r5fss0_core1_dma 301 memory-region = <&mcu_r5fss0_core1_dma_memory_region>,
302 <&mcu_r5fss0_core1_mem 302 <&mcu_r5fss0_core1_memory_region>;
303 }; 303 };
304 304
305 &main_r5fss0 { 305 &main_r5fss0 {
306 ti,cluster-mode = <0>; 306 ti,cluster-mode = <0>;
307 }; 307 };
308 308
309 &main_r5fss1 { 309 &main_r5fss1 {
310 ti,cluster-mode = <0>; 310 ti,cluster-mode = <0>;
311 }; 311 };
312 312
313 /* Timers are used by Remoteproc firmware */ 313 /* Timers are used by Remoteproc firmware */
314 &main_timer0 { 314 &main_timer0 {
315 status = "reserved"; 315 status = "reserved";
316 }; 316 };
317 317
318 &main_timer1 { 318 &main_timer1 {
319 status = "reserved"; 319 status = "reserved";
320 }; 320 };
321 321
322 &main_timer2 { 322 &main_timer2 {
323 status = "reserved"; 323 status = "reserved";
324 }; 324 };
325 325
326 &main_timer3 { 326 &main_timer3 {
327 status = "reserved"; 327 status = "reserved";
328 }; 328 };
329 329
330 &main_timer4 { 330 &main_timer4 {
331 status = "reserved"; 331 status = "reserved";
332 }; 332 };
333 333
334 &main_timer5 { 334 &main_timer5 {
335 status = "reserved"; 335 status = "reserved";
336 }; 336 };
337 337
338 &main_r5fss0_core0 { 338 &main_r5fss0_core0 {
339 mboxes = <&mailbox0_cluster1 &mbox_mai 339 mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>;
340 memory-region = <&main_r5fss0_core0_dm 340 memory-region = <&main_r5fss0_core0_dma_memory_region>,
341 <&main_r5fss0_core0_me 341 <&main_r5fss0_core0_memory_region>;
342 }; 342 };
343 343
344 &main_r5fss0_core1 { 344 &main_r5fss0_core1 {
345 mboxes = <&mailbox0_cluster1 &mbox_mai 345 mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>;
346 memory-region = <&main_r5fss0_core1_dm 346 memory-region = <&main_r5fss0_core1_dma_memory_region>,
347 <&main_r5fss0_core1_me 347 <&main_r5fss0_core1_memory_region>;
348 }; 348 };
349 349
350 &main_r5fss1_core0 { 350 &main_r5fss1_core0 {
351 mboxes = <&mailbox0_cluster2 &mbox_mai 351 mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core0>;
352 memory-region = <&main_r5fss1_core0_dm 352 memory-region = <&main_r5fss1_core0_dma_memory_region>,
353 <&main_r5fss1_core0_me 353 <&main_r5fss1_core0_memory_region>;
354 }; 354 };
355 355
356 &main_r5fss1_core1 { 356 &main_r5fss1_core1 {
357 mboxes = <&mailbox0_cluster2 &mbox_mai 357 mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core1>;
358 memory-region = <&main_r5fss1_core1_dm 358 memory-region = <&main_r5fss1_core1_dma_memory_region>,
359 <&main_r5fss1_core1_me 359 <&main_r5fss1_core1_memory_region>;
360 }; 360 };
361 361
362 &c71_0 { 362 &c71_0 {
363 status = "okay"; 363 status = "okay";
364 mboxes = <&mailbox0_cluster4 &mbox_c71 364 mboxes = <&mailbox0_cluster4 &mbox_c71_0>;
365 memory-region = <&c71_0_dma_memory_reg 365 memory-region = <&c71_0_dma_memory_region>,
366 <&c71_0_memory_region> 366 <&c71_0_memory_region>;
367 }; 367 };
368 368
369 &c71_1 { 369 &c71_1 {
370 status = "okay"; 370 status = "okay";
371 mboxes = <&mailbox0_cluster4 &mbox_c71 371 mboxes = <&mailbox0_cluster4 &mbox_c71_1>;
372 memory-region = <&c71_1_dma_memory_reg 372 memory-region = <&c71_1_dma_memory_region>,
373 <&c71_1_memory_region> 373 <&c71_1_memory_region>;
374 }; 374 };
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