1 // SPDX-License-Identifier: GPL-2.0-only OR MI !! 1 // SPDX-License-Identifier: GPL-2.0 2 /* 2 /* 3 * Copyright (C) 2023-2024 Texas Instruments I !! 3 * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ 4 */ 4 */ 5 5 6 /dts-v1/; 6 /dts-v1/; 7 7 8 #include "k3-j721s2.dtsi" 8 #include "k3-j721s2.dtsi" 9 #include <dt-bindings/gpio/gpio.h> 9 #include <dt-bindings/gpio/gpio.h> 10 10 11 / { 11 / { 12 memory@80000000 { 12 memory@80000000 { 13 device_type = "memory"; 13 device_type = "memory"; 14 bootph-all; << 15 /* 16 GB RAM */ 14 /* 16 GB RAM */ 16 reg = <0x00000000 0x80000000 0 !! 15 reg = <0x00 0x80000000 0x00 0x80000000>, 17 <0x00000008 0x80000000 0 !! 16 <0x08 0x80000000 0x03 0x80000000>; 18 }; 17 }; 19 18 20 reserved_memory: reserved-memory { 19 reserved_memory: reserved-memory { 21 #address-cells = <2>; 20 #address-cells = <2>; 22 #size-cells = <2>; 21 #size-cells = <2>; 23 ranges; 22 ranges; 24 23 25 secure_ddr: optee@9e800000 { 24 secure_ddr: optee@9e800000 { 26 reg = <0x00 0x9e800000 25 reg = <0x00 0x9e800000 0x00 0x01800000>; 27 no-map; 26 no-map; 28 }; 27 }; 29 << 30 mcu_r5fss0_core0_dma_memory_re << 31 compatible = "shared-d << 32 reg = <0x00 0xa0000000 << 33 no-map; << 34 }; << 35 << 36 mcu_r5fss0_core0_memory_region << 37 compatible = "shared-d << 38 reg = <0x00 0xa0100000 << 39 no-map; << 40 }; << 41 << 42 mcu_r5fss0_core1_dma_memory_re << 43 compatible = "shared-d << 44 reg = <0x00 0xa1000000 << 45 no-map; << 46 }; << 47 << 48 mcu_r5fss0_core1_memory_region << 49 compatible = "shared-d << 50 reg = <0x00 0xa1100000 << 51 no-map; << 52 }; << 53 << 54 main_r5fss0_core0_dma_memory_r << 55 compatible = "shared-d << 56 reg = <0x00 0xa2000000 << 57 no-map; << 58 }; << 59 << 60 main_r5fss0_core0_memory_regio << 61 compatible = "shared-d << 62 reg = <0x00 0xa2100000 << 63 no-map; << 64 }; << 65 << 66 main_r5fss0_core1_dma_memory_r << 67 compatible = "shared-d << 68 reg = <0x00 0xa3000000 << 69 no-map; << 70 }; << 71 << 72 main_r5fss0_core1_memory_regio << 73 compatible = "shared-d << 74 reg = <0x00 0xa3100000 << 75 no-map; << 76 }; << 77 << 78 main_r5fss1_core0_dma_memory_r << 79 compatible = "shared-d << 80 reg = <0x00 0xa4000000 << 81 no-map; << 82 }; << 83 << 84 main_r5fss1_core0_memory_regio << 85 compatible = "shared-d << 86 reg = <0x00 0xa4100000 << 87 no-map; << 88 }; << 89 << 90 main_r5fss1_core1_dma_memory_r << 91 compatible = "shared-d << 92 reg = <0x00 0xa5000000 << 93 no-map; << 94 }; << 95 << 96 main_r5fss1_core1_memory_regio << 97 compatible = "shared-d << 98 reg = <0x00 0xa5100000 << 99 no-map; << 100 }; << 101 << 102 c71_0_dma_memory_region: c71-d << 103 compatible = "shared-d << 104 reg = <0x00 0xa6000000 << 105 no-map; << 106 }; << 107 << 108 c71_0_memory_region: c71-memor << 109 compatible = "shared-d << 110 reg = <0x00 0xa6100000 << 111 no-map; << 112 }; << 113 << 114 c71_1_dma_memory_region: c71-d << 115 compatible = "shared-d << 116 reg = <0x00 0xa7000000 << 117 no-map; << 118 }; << 119 << 120 c71_1_memory_region: c71-memor << 121 compatible = "shared-d << 122 reg = <0x00 0xa7100000 << 123 no-map; << 124 }; << 125 << 126 rtos_ipc_memory_region: ipc-me << 127 reg = <0x00 0xa8000000 << 128 alignment = <0x1000>; << 129 no-map; << 130 }; << 131 }; 28 }; 132 }; << 133 << 134 &wkup_pmx0 { << 135 mcu_fss0_ospi0_pins_default: mcu-fss0- << 136 bootph-all; << 137 pinctrl-single,pins = < << 138 J721S2_WKUP_IOPAD(0x00 << 139 J721S2_WKUP_IOPAD(0x02 << 140 J721S2_WKUP_IOPAD(0x00 << 141 J721S2_WKUP_IOPAD(0x01 << 142 J721S2_WKUP_IOPAD(0x01 << 143 J721S2_WKUP_IOPAD(0x01 << 144 J721S2_WKUP_IOPAD(0x01 << 145 J721S2_WKUP_IOPAD(0x02 << 146 J721S2_WKUP_IOPAD(0x02 << 147 J721S2_WKUP_IOPAD(0x02 << 148 J721S2_WKUP_IOPAD(0x00 << 149 >; << 150 }; << 151 }; << 152 << 153 &wkup_pmx2 { << 154 wkup_i2c0_pins_default: wkup-i2c0-defa << 155 pinctrl-single,pins = < << 156 J721S2_WKUP_IOPAD(0x09 << 157 J721S2_WKUP_IOPAD(0x09 << 158 >; << 159 }; << 160 }; << 161 << 162 &wkup_i2c0 { << 163 status = "okay"; << 164 pinctrl-names = "default"; << 165 pinctrl-0 = <&wkup_i2c0_pins_default>; << 166 clock-frequency = <400000>; << 167 << 168 eeprom@51 { << 169 /* AT24C512C-MAHM-T */ << 170 compatible = "atmel,24c512"; << 171 reg = <0x51>; << 172 }; << 173 }; << 174 << 175 &ospi0 { << 176 status = "okay"; << 177 pinctrl-names = "default"; << 178 pinctrl-0 = <&mcu_fss0_ospi0_pins_defa << 179 << 180 flash@0 { << 181 compatible = "jedec,spi-nor"; << 182 reg = <0x0>; << 183 spi-tx-bus-width = <8>; << 184 spi-rx-bus-width = <8>; << 185 spi-max-frequency = <25000000> << 186 cdns,tshsl-ns = <60>; << 187 cdns,tsd2d-ns = <60>; << 188 cdns,tchsh-ns = <60>; << 189 cdns,tslch-ns = <60>; << 190 cdns,read-delay = <4>; << 191 << 192 partitions { << 193 bootph-all; << 194 compatible = "fixed-pa << 195 #address-cells = <1>; << 196 #size-cells = <1>; << 197 << 198 partition@0 { << 199 label = "ospi. << 200 reg = <0x0 0x8 << 201 }; << 202 << 203 partition@80000 { << 204 label = "ospi. << 205 reg = <0x80000 << 206 }; << 207 << 208 partition@280000 { << 209 label = "ospi. << 210 reg = <0x28000 << 211 }; << 212 << 213 partition@680000 { << 214 label = "ospi. << 215 reg = <0x68000 << 216 }; << 217 << 218 partition@6c0000 { << 219 label = "ospi. << 220 reg = <0x6c000 << 221 }; << 222 << 223 partition@800000 { << 224 label = "ospi. << 225 reg = <0x80000 << 226 }; << 227 << 228 partition@3fc0000 { << 229 bootph-pre-ram << 230 label = "ospi. << 231 reg = <0x3fc00 << 232 }; << 233 }; << 234 }; << 235 }; << 236 << 237 &mailbox0_cluster0 { << 238 status = "okay"; << 239 interrupts = <436>; << 240 mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0 << 241 ti,mbox-rx = <0 0 0>; << 242 ti,mbox-tx = <1 0 0>; << 243 }; << 244 << 245 mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0 << 246 ti,mbox-rx = <2 0 0>; << 247 ti,mbox-tx = <3 0 0>; << 248 }; << 249 }; << 250 << 251 &mailbox0_cluster1 { << 252 status = "okay"; << 253 interrupts = <432>; << 254 mbox_main_r5fss0_core0: mbox-main-r5fs << 255 ti,mbox-rx = <0 0 0>; << 256 ti,mbox-tx = <1 0 0>; << 257 }; << 258 << 259 mbox_main_r5fss0_core1: mbox-main-r5fs << 260 ti,mbox-rx = <2 0 0>; << 261 ti,mbox-tx = <3 0 0>; << 262 }; << 263 }; << 264 << 265 &mailbox0_cluster2 { << 266 status = "okay"; << 267 interrupts = <428>; << 268 mbox_main_r5fss1_core0: mbox-main-r5fs << 269 ti,mbox-rx = <0 0 0>; << 270 ti,mbox-tx = <1 0 0>; << 271 }; << 272 << 273 mbox_main_r5fss1_core1: mbox-main-r5fs << 274 ti,mbox-rx = <2 0 0>; << 275 ti,mbox-tx = <3 0 0>; << 276 }; << 277 }; << 278 << 279 &mailbox0_cluster4 { << 280 status = "okay"; << 281 interrupts = <420>; << 282 mbox_c71_0: mbox-c71-0 { << 283 ti,mbox-rx = <0 0 0>; << 284 ti,mbox-tx = <1 0 0>; << 285 }; << 286 << 287 mbox_c71_1: mbox-c71-1 { << 288 ti,mbox-rx = <2 0 0>; << 289 ti,mbox-tx = <3 0 0>; << 290 }; << 291 }; << 292 << 293 &mcu_r5fss0_core0 { << 294 mboxes = <&mailbox0_cluster0 &mbox_mcu << 295 memory-region = <&mcu_r5fss0_core0_dma << 296 <&mcu_r5fss0_core0_mem << 297 }; << 298 << 299 &mcu_r5fss0_core1 { << 300 mboxes = <&mailbox0_cluster0 &mbox_mcu << 301 memory-region = <&mcu_r5fss0_core1_dma << 302 <&mcu_r5fss0_core1_mem << 303 }; << 304 << 305 &main_r5fss0 { << 306 ti,cluster-mode = <0>; << 307 }; << 308 << 309 &main_r5fss1 { << 310 ti,cluster-mode = <0>; << 311 }; << 312 << 313 /* Timers are used by Remoteproc firmware */ << 314 &main_timer0 { << 315 status = "reserved"; << 316 }; << 317 << 318 &main_timer1 { << 319 status = "reserved"; << 320 }; << 321 << 322 &main_timer2 { << 323 status = "reserved"; << 324 }; << 325 << 326 &main_timer3 { << 327 status = "reserved"; << 328 }; << 329 << 330 &main_timer4 { << 331 status = "reserved"; << 332 }; << 333 << 334 &main_timer5 { << 335 status = "reserved"; << 336 }; << 337 << 338 &main_r5fss0_core0 { << 339 mboxes = <&mailbox0_cluster1 &mbox_mai << 340 memory-region = <&main_r5fss0_core0_dm << 341 <&main_r5fss0_core0_me << 342 }; << 343 << 344 &main_r5fss0_core1 { << 345 mboxes = <&mailbox0_cluster1 &mbox_mai << 346 memory-region = <&main_r5fss0_core1_dm << 347 <&main_r5fss0_core1_me << 348 }; << 349 << 350 &main_r5fss1_core0 { << 351 mboxes = <&mailbox0_cluster2 &mbox_mai << 352 memory-region = <&main_r5fss1_core0_dm << 353 <&main_r5fss1_core0_me << 354 }; << 355 << 356 &main_r5fss1_core1 { << 357 mboxes = <&mailbox0_cluster2 &mbox_mai << 358 memory-region = <&main_r5fss1_core1_dm << 359 <&main_r5fss1_core1_me << 360 }; << 361 << 362 &c71_0 { << 363 status = "okay"; << 364 mboxes = <&mailbox0_cluster4 &mbox_c71 << 365 memory-region = <&c71_0_dma_memory_reg << 366 <&c71_0_memory_region> << 367 }; << 368 << 369 &c71_1 { << 370 status = "okay"; << 371 mboxes = <&mailbox0_cluster4 &mbox_c71 << 372 memory-region = <&c71_1_dma_memory_reg << 373 <&c71_1_memory_region> << 374 }; 29 };
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