1 // SPDX-License-Identifier: GPL-2.0-only OR MI 1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
2 /* 2 /*
3 * Copyright (C) 2023-2024 Texas Instruments I 3 * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/
4 */ 4 */
5 5
6 /dts-v1/; 6 /dts-v1/;
7 7
8 #include "k3-j721s2.dtsi" 8 #include "k3-j721s2.dtsi"
9 #include <dt-bindings/gpio/gpio.h> 9 #include <dt-bindings/gpio/gpio.h>
10 10
11 / { 11 / {
12 memory@80000000 { 12 memory@80000000 {
13 device_type = "memory"; 13 device_type = "memory";
14 bootph-all; <<
15 /* 16 GB RAM */ 14 /* 16 GB RAM */
16 reg = <0x00000000 0x80000000 0 !! 15 reg = <0x00 0x80000000 0x00 0x80000000>,
17 <0x00000008 0x80000000 0 !! 16 <0x08 0x80000000 0x03 0x80000000>;
18 }; 17 };
19 18
20 reserved_memory: reserved-memory { 19 reserved_memory: reserved-memory {
21 #address-cells = <2>; 20 #address-cells = <2>;
22 #size-cells = <2>; 21 #size-cells = <2>;
23 ranges; 22 ranges;
24 23
25 secure_ddr: optee@9e800000 { 24 secure_ddr: optee@9e800000 {
26 reg = <0x00 0x9e800000 25 reg = <0x00 0x9e800000 0x00 0x01800000>;
27 no-map; 26 no-map;
28 }; 27 };
29 28
30 mcu_r5fss0_core0_dma_memory_re 29 mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 {
31 compatible = "shared-d 30 compatible = "shared-dma-pool";
32 reg = <0x00 0xa0000000 31 reg = <0x00 0xa0000000 0x00 0x100000>;
33 no-map; 32 no-map;
34 }; 33 };
35 34
36 mcu_r5fss0_core0_memory_region 35 mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 {
37 compatible = "shared-d 36 compatible = "shared-dma-pool";
38 reg = <0x00 0xa0100000 37 reg = <0x00 0xa0100000 0x00 0xf00000>;
39 no-map; 38 no-map;
40 }; 39 };
41 40
42 mcu_r5fss0_core1_dma_memory_re 41 mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 {
43 compatible = "shared-d 42 compatible = "shared-dma-pool";
44 reg = <0x00 0xa1000000 43 reg = <0x00 0xa1000000 0x00 0x100000>;
45 no-map; 44 no-map;
46 }; 45 };
47 46
48 mcu_r5fss0_core1_memory_region 47 mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 {
49 compatible = "shared-d 48 compatible = "shared-dma-pool";
50 reg = <0x00 0xa1100000 49 reg = <0x00 0xa1100000 0x00 0xf00000>;
51 no-map; 50 no-map;
52 }; 51 };
53 52
54 main_r5fss0_core0_dma_memory_r 53 main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a2000000 {
55 compatible = "shared-d 54 compatible = "shared-dma-pool";
56 reg = <0x00 0xa2000000 55 reg = <0x00 0xa2000000 0x00 0x100000>;
57 no-map; 56 no-map;
58 }; 57 };
59 58
60 main_r5fss0_core0_memory_regio 59 main_r5fss0_core0_memory_region: r5f-memory@a2100000 {
61 compatible = "shared-d 60 compatible = "shared-dma-pool";
62 reg = <0x00 0xa2100000 61 reg = <0x00 0xa2100000 0x00 0xf00000>;
63 no-map; 62 no-map;
64 }; 63 };
65 64
66 main_r5fss0_core1_dma_memory_r 65 main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a3000000 {
67 compatible = "shared-d 66 compatible = "shared-dma-pool";
68 reg = <0x00 0xa3000000 67 reg = <0x00 0xa3000000 0x00 0x100000>;
69 no-map; 68 no-map;
70 }; 69 };
71 70
72 main_r5fss0_core1_memory_regio 71 main_r5fss0_core1_memory_region: r5f-memory@a3100000 {
73 compatible = "shared-d 72 compatible = "shared-dma-pool";
74 reg = <0x00 0xa3100000 73 reg = <0x00 0xa3100000 0x00 0xf00000>;
75 no-map; 74 no-map;
76 }; 75 };
77 76
78 main_r5fss1_core0_dma_memory_r 77 main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a4000000 {
79 compatible = "shared-d 78 compatible = "shared-dma-pool";
80 reg = <0x00 0xa4000000 79 reg = <0x00 0xa4000000 0x00 0x100000>;
81 no-map; 80 no-map;
82 }; 81 };
83 82
84 main_r5fss1_core0_memory_regio 83 main_r5fss1_core0_memory_region: r5f-memory@a4100000 {
85 compatible = "shared-d 84 compatible = "shared-dma-pool";
86 reg = <0x00 0xa4100000 85 reg = <0x00 0xa4100000 0x00 0xf00000>;
87 no-map; 86 no-map;
88 }; 87 };
89 88
90 main_r5fss1_core1_dma_memory_r 89 main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a5000000 {
91 compatible = "shared-d 90 compatible = "shared-dma-pool";
92 reg = <0x00 0xa5000000 91 reg = <0x00 0xa5000000 0x00 0x100000>;
93 no-map; 92 no-map;
94 }; 93 };
95 94
96 main_r5fss1_core1_memory_regio 95 main_r5fss1_core1_memory_region: r5f-memory@a5100000 {
97 compatible = "shared-d 96 compatible = "shared-dma-pool";
98 reg = <0x00 0xa5100000 97 reg = <0x00 0xa5100000 0x00 0xf00000>;
99 no-map; 98 no-map;
100 }; 99 };
101 100
102 c71_0_dma_memory_region: c71-d 101 c71_0_dma_memory_region: c71-dma-memory@a6000000 {
103 compatible = "shared-d 102 compatible = "shared-dma-pool";
104 reg = <0x00 0xa6000000 103 reg = <0x00 0xa6000000 0x00 0x100000>;
105 no-map; 104 no-map;
106 }; 105 };
107 106
108 c71_0_memory_region: c71-memor 107 c71_0_memory_region: c71-memory@a6100000 {
109 compatible = "shared-d 108 compatible = "shared-dma-pool";
110 reg = <0x00 0xa6100000 109 reg = <0x00 0xa6100000 0x00 0xf00000>;
111 no-map; 110 no-map;
112 }; 111 };
113 112
114 c71_1_dma_memory_region: c71-d 113 c71_1_dma_memory_region: c71-dma-memory@a7000000 {
115 compatible = "shared-d 114 compatible = "shared-dma-pool";
116 reg = <0x00 0xa7000000 115 reg = <0x00 0xa7000000 0x00 0x100000>;
117 no-map; 116 no-map;
118 }; 117 };
119 118
120 c71_1_memory_region: c71-memor 119 c71_1_memory_region: c71-memory@a7100000 {
121 compatible = "shared-d 120 compatible = "shared-dma-pool";
122 reg = <0x00 0xa7100000 121 reg = <0x00 0xa7100000 0x00 0xf00000>;
123 no-map; 122 no-map;
124 }; 123 };
125 124
126 rtos_ipc_memory_region: ipc-me 125 rtos_ipc_memory_region: ipc-memories@a8000000 {
127 reg = <0x00 0xa8000000 126 reg = <0x00 0xa8000000 0x00 0x01c00000>;
128 alignment = <0x1000>; 127 alignment = <0x1000>;
129 no-map; 128 no-map;
130 }; 129 };
131 }; 130 };
132 }; 131 };
133 132
134 &wkup_pmx0 { <<
135 mcu_fss0_ospi0_pins_default: mcu-fss0- <<
136 bootph-all; <<
137 pinctrl-single,pins = < <<
138 J721S2_WKUP_IOPAD(0x00 <<
139 J721S2_WKUP_IOPAD(0x02 <<
140 J721S2_WKUP_IOPAD(0x00 <<
141 J721S2_WKUP_IOPAD(0x01 <<
142 J721S2_WKUP_IOPAD(0x01 <<
143 J721S2_WKUP_IOPAD(0x01 <<
144 J721S2_WKUP_IOPAD(0x01 <<
145 J721S2_WKUP_IOPAD(0x02 <<
146 J721S2_WKUP_IOPAD(0x02 <<
147 J721S2_WKUP_IOPAD(0x02 <<
148 J721S2_WKUP_IOPAD(0x00 <<
149 >; <<
150 }; <<
151 }; <<
152 <<
153 &wkup_pmx2 { 133 &wkup_pmx2 {
154 wkup_i2c0_pins_default: wkup-i2c0-defa 134 wkup_i2c0_pins_default: wkup-i2c0-default-pins {
155 pinctrl-single,pins = < 135 pinctrl-single,pins = <
156 J721S2_WKUP_IOPAD(0x09 136 J721S2_WKUP_IOPAD(0x098, PIN_INPUT, 0) /* (H24) WKUP_I2C0_SCL */
157 J721S2_WKUP_IOPAD(0x09 137 J721S2_WKUP_IOPAD(0x09c, PIN_INPUT, 0) /* (H27) WKUP_I2C0_SDA */
158 >; 138 >;
159 }; 139 };
160 }; 140 };
161 141
162 &wkup_i2c0 { 142 &wkup_i2c0 {
163 status = "okay"; 143 status = "okay";
164 pinctrl-names = "default"; 144 pinctrl-names = "default";
165 pinctrl-0 = <&wkup_i2c0_pins_default>; 145 pinctrl-0 = <&wkup_i2c0_pins_default>;
166 clock-frequency = <400000>; 146 clock-frequency = <400000>;
167 147
168 eeprom@51 { 148 eeprom@51 {
169 /* AT24C512C-MAHM-T */ 149 /* AT24C512C-MAHM-T */
170 compatible = "atmel,24c512"; 150 compatible = "atmel,24c512";
171 reg = <0x51>; 151 reg = <0x51>;
172 }; 152 };
173 }; 153 };
174 154
175 &ospi0 { <<
176 status = "okay"; <<
177 pinctrl-names = "default"; <<
178 pinctrl-0 = <&mcu_fss0_ospi0_pins_defa <<
179 <<
180 flash@0 { <<
181 compatible = "jedec,spi-nor"; <<
182 reg = <0x0>; <<
183 spi-tx-bus-width = <8>; <<
184 spi-rx-bus-width = <8>; <<
185 spi-max-frequency = <25000000> <<
186 cdns,tshsl-ns = <60>; <<
187 cdns,tsd2d-ns = <60>; <<
188 cdns,tchsh-ns = <60>; <<
189 cdns,tslch-ns = <60>; <<
190 cdns,read-delay = <4>; <<
191 <<
192 partitions { <<
193 bootph-all; <<
194 compatible = "fixed-pa <<
195 #address-cells = <1>; <<
196 #size-cells = <1>; <<
197 <<
198 partition@0 { <<
199 label = "ospi. <<
200 reg = <0x0 0x8 <<
201 }; <<
202 <<
203 partition@80000 { <<
204 label = "ospi. <<
205 reg = <0x80000 <<
206 }; <<
207 <<
208 partition@280000 { <<
209 label = "ospi. <<
210 reg = <0x28000 <<
211 }; <<
212 <<
213 partition@680000 { <<
214 label = "ospi. <<
215 reg = <0x68000 <<
216 }; <<
217 <<
218 partition@6c0000 { <<
219 label = "ospi. <<
220 reg = <0x6c000 <<
221 }; <<
222 <<
223 partition@800000 { <<
224 label = "ospi. <<
225 reg = <0x80000 <<
226 }; <<
227 <<
228 partition@3fc0000 { <<
229 bootph-pre-ram <<
230 label = "ospi. <<
231 reg = <0x3fc00 <<
232 }; <<
233 }; <<
234 }; <<
235 }; <<
236 <<
237 &mailbox0_cluster0 { 155 &mailbox0_cluster0 {
238 status = "okay"; 156 status = "okay";
239 interrupts = <436>; 157 interrupts = <436>;
240 mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0 158 mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 {
241 ti,mbox-rx = <0 0 0>; 159 ti,mbox-rx = <0 0 0>;
242 ti,mbox-tx = <1 0 0>; 160 ti,mbox-tx = <1 0 0>;
243 }; 161 };
244 162
245 mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0 163 mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 {
246 ti,mbox-rx = <2 0 0>; 164 ti,mbox-rx = <2 0 0>;
247 ti,mbox-tx = <3 0 0>; 165 ti,mbox-tx = <3 0 0>;
248 }; 166 };
249 }; 167 };
250 168
251 &mailbox0_cluster1 { 169 &mailbox0_cluster1 {
252 status = "okay"; 170 status = "okay";
253 interrupts = <432>; 171 interrupts = <432>;
254 mbox_main_r5fss0_core0: mbox-main-r5fs 172 mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
255 ti,mbox-rx = <0 0 0>; 173 ti,mbox-rx = <0 0 0>;
256 ti,mbox-tx = <1 0 0>; 174 ti,mbox-tx = <1 0 0>;
257 }; 175 };
258 176
259 mbox_main_r5fss0_core1: mbox-main-r5fs 177 mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 {
260 ti,mbox-rx = <2 0 0>; 178 ti,mbox-rx = <2 0 0>;
261 ti,mbox-tx = <3 0 0>; 179 ti,mbox-tx = <3 0 0>;
262 }; 180 };
263 }; 181 };
264 182
265 &mailbox0_cluster2 { 183 &mailbox0_cluster2 {
266 status = "okay"; 184 status = "okay";
267 interrupts = <428>; 185 interrupts = <428>;
268 mbox_main_r5fss1_core0: mbox-main-r5fs 186 mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 {
269 ti,mbox-rx = <0 0 0>; 187 ti,mbox-rx = <0 0 0>;
270 ti,mbox-tx = <1 0 0>; 188 ti,mbox-tx = <1 0 0>;
271 }; 189 };
272 190
273 mbox_main_r5fss1_core1: mbox-main-r5fs 191 mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 {
274 ti,mbox-rx = <2 0 0>; 192 ti,mbox-rx = <2 0 0>;
275 ti,mbox-tx = <3 0 0>; 193 ti,mbox-tx = <3 0 0>;
276 }; 194 };
277 }; 195 };
278 196
279 &mailbox0_cluster4 { 197 &mailbox0_cluster4 {
280 status = "okay"; 198 status = "okay";
281 interrupts = <420>; 199 interrupts = <420>;
282 mbox_c71_0: mbox-c71-0 { 200 mbox_c71_0: mbox-c71-0 {
283 ti,mbox-rx = <0 0 0>; 201 ti,mbox-rx = <0 0 0>;
284 ti,mbox-tx = <1 0 0>; 202 ti,mbox-tx = <1 0 0>;
285 }; 203 };
286 204
287 mbox_c71_1: mbox-c71-1 { 205 mbox_c71_1: mbox-c71-1 {
288 ti,mbox-rx = <2 0 0>; 206 ti,mbox-rx = <2 0 0>;
289 ti,mbox-tx = <3 0 0>; 207 ti,mbox-tx = <3 0 0>;
290 }; 208 };
291 }; 209 };
292 210
293 &mcu_r5fss0_core0 { 211 &mcu_r5fss0_core0 {
294 mboxes = <&mailbox0_cluster0 &mbox_mcu 212 mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>;
295 memory-region = <&mcu_r5fss0_core0_dma 213 memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
296 <&mcu_r5fss0_core0_mem 214 <&mcu_r5fss0_core0_memory_region>;
297 }; 215 };
298 216
299 &mcu_r5fss0_core1 { 217 &mcu_r5fss0_core1 {
300 mboxes = <&mailbox0_cluster0 &mbox_mcu 218 mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>;
301 memory-region = <&mcu_r5fss0_core1_dma 219 memory-region = <&mcu_r5fss0_core1_dma_memory_region>,
302 <&mcu_r5fss0_core1_mem 220 <&mcu_r5fss0_core1_memory_region>;
303 }; <<
304 <<
305 &main_r5fss0 { <<
306 ti,cluster-mode = <0>; <<
307 }; <<
308 <<
309 &main_r5fss1 { <<
310 ti,cluster-mode = <0>; <<
311 }; <<
312 <<
313 /* Timers are used by Remoteproc firmware */ <<
314 &main_timer0 { <<
315 status = "reserved"; <<
316 }; <<
317 <<
318 &main_timer1 { <<
319 status = "reserved"; <<
320 }; <<
321 <<
322 &main_timer2 { <<
323 status = "reserved"; <<
324 }; <<
325 <<
326 &main_timer3 { <<
327 status = "reserved"; <<
328 }; <<
329 <<
330 &main_timer4 { <<
331 status = "reserved"; <<
332 }; <<
333 <<
334 &main_timer5 { <<
335 status = "reserved"; <<
336 }; 221 };
337 222
338 &main_r5fss0_core0 { 223 &main_r5fss0_core0 {
339 mboxes = <&mailbox0_cluster1 &mbox_mai 224 mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>;
340 memory-region = <&main_r5fss0_core0_dm 225 memory-region = <&main_r5fss0_core0_dma_memory_region>,
341 <&main_r5fss0_core0_me 226 <&main_r5fss0_core0_memory_region>;
342 }; 227 };
343 228
344 &main_r5fss0_core1 { 229 &main_r5fss0_core1 {
345 mboxes = <&mailbox0_cluster1 &mbox_mai 230 mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>;
346 memory-region = <&main_r5fss0_core1_dm 231 memory-region = <&main_r5fss0_core1_dma_memory_region>,
347 <&main_r5fss0_core1_me 232 <&main_r5fss0_core1_memory_region>;
348 }; 233 };
349 234
350 &main_r5fss1_core0 { 235 &main_r5fss1_core0 {
351 mboxes = <&mailbox0_cluster2 &mbox_mai 236 mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core0>;
352 memory-region = <&main_r5fss1_core0_dm 237 memory-region = <&main_r5fss1_core0_dma_memory_region>,
353 <&main_r5fss1_core0_me 238 <&main_r5fss1_core0_memory_region>;
354 }; 239 };
355 240
356 &main_r5fss1_core1 { 241 &main_r5fss1_core1 {
357 mboxes = <&mailbox0_cluster2 &mbox_mai 242 mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core1>;
358 memory-region = <&main_r5fss1_core1_dm 243 memory-region = <&main_r5fss1_core1_dma_memory_region>,
359 <&main_r5fss1_core1_me 244 <&main_r5fss1_core1_memory_region>;
360 }; 245 };
361 246
362 &c71_0 { 247 &c71_0 {
363 status = "okay"; 248 status = "okay";
364 mboxes = <&mailbox0_cluster4 &mbox_c71 249 mboxes = <&mailbox0_cluster4 &mbox_c71_0>;
365 memory-region = <&c71_0_dma_memory_reg 250 memory-region = <&c71_0_dma_memory_region>,
366 <&c71_0_memory_region> 251 <&c71_0_memory_region>;
367 }; 252 };
368 253
369 &c71_1 { 254 &c71_1 {
370 status = "okay"; 255 status = "okay";
371 mboxes = <&mailbox0_cluster4 &mbox_c71 256 mboxes = <&mailbox0_cluster4 &mbox_c71_1>;
372 memory-region = <&c71_1_dma_memory_reg 257 memory-region = <&c71_1_dma_memory_region>,
373 <&c71_1_memory_region> 258 <&c71_1_memory_region>;
374 }; 259 };
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