1 // SPDX-License-Identifier: GPL-2.0-only OR MI !! 1 // SPDX-License-Identifier: GPL-2.0
2 /* 2 /*
3 * Device Tree Source for J7200 SoC Family Mai 3 * Device Tree Source for J7200 SoC Family Main Domain peripherals
4 * 4 *
5 * Copyright (C) 2020-2024 Texas Instruments I !! 5 * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/
6 */ 6 */
7 7
8 / { <<
9 serdes_refclk: serdes-refclk { <<
10 #clock-cells = <0>; <<
11 compatible = "fixed-clock"; <<
12 }; <<
13 }; <<
14 <<
15 &cbass_main { 8 &cbass_main {
16 msmc_ram: sram@70000000 { 9 msmc_ram: sram@70000000 {
17 compatible = "mmio-sram"; 10 compatible = "mmio-sram";
18 reg = <0x00 0x70000000 0x00 0x 11 reg = <0x00 0x70000000 0x00 0x100000>;
19 #address-cells = <1>; 12 #address-cells = <1>;
20 #size-cells = <1>; 13 #size-cells = <1>;
21 ranges = <0x00 0x00 0x70000000 14 ranges = <0x00 0x00 0x70000000 0x100000>;
22 15
23 atf-sram@0 { 16 atf-sram@0 {
24 reg = <0x00 0x20000>; 17 reg = <0x00 0x20000>;
25 }; 18 };
26 }; 19 };
27 20
28 scm_conf: scm-conf@100000 { 21 scm_conf: scm-conf@100000 {
29 compatible = "ti,j721e-system- 22 compatible = "ti,j721e-system-controller", "syscon", "simple-mfd";
30 reg = <0x00 0x00100000 0x00 0x 23 reg = <0x00 0x00100000 0x00 0x1c000>;
31 #address-cells = <1>; 24 #address-cells = <1>;
32 #size-cells = <1>; 25 #size-cells = <1>;
33 ranges = <0x00 0x00 0x00100000 26 ranges = <0x00 0x00 0x00100000 0x1c000>;
34 27
35 serdes_ln_ctrl: mux-controller 28 serdes_ln_ctrl: mux-controller@4080 {
36 compatible = "reg-mux" !! 29 compatible = "mmio-mux";
37 reg = <0x4080 0x20>; <<
38 #mux-control-cells = < 30 #mux-control-cells = <1>;
39 mux-reg-masks = <0x0 0 !! 31 mux-reg-masks = <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */
40 <0x8 0 !! 32 <0x4088 0x3>, <0x408c 0x3>; /* SERDES0 lane2/3 select */
41 }; <<
42 <<
43 cpsw0_phy_gmii_sel: phy@4044 { <<
44 compatible = "ti,j7200 <<
45 ti,qsgmii-main-ports = <<
46 reg = <0x4044 0x10>; <<
47 #phy-cells = <1>; <<
48 }; 33 };
49 34
50 usb_serdes_mux: mux-controller 35 usb_serdes_mux: mux-controller@4000 {
51 compatible = "reg-mux" !! 36 compatible = "mmio-mux";
52 reg = <0x4000 0x4>; <<
53 #mux-control-cells = < 37 #mux-control-cells = <1>;
54 mux-reg-masks = <0x0 0 !! 38 mux-reg-masks = <0x4000 0x8000000>; /* USB0 to SERDES0 lane 1/3 mux */
55 }; 39 };
56 }; 40 };
57 41
58 gic500: interrupt-controller@1800000 { 42 gic500: interrupt-controller@1800000 {
59 compatible = "arm,gic-v3"; 43 compatible = "arm,gic-v3";
60 #address-cells = <2>; 44 #address-cells = <2>;
61 #size-cells = <2>; 45 #size-cells = <2>;
62 ranges; 46 ranges;
63 #interrupt-cells = <3>; 47 #interrupt-cells = <3>;
64 interrupt-controller; 48 interrupt-controller;
65 reg = <0x00 0x01800000 0x00 0x 49 reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */
66 <0x00 0x01900000 0x00 0x 50 <0x00 0x01900000 0x00 0x100000>, /* GICR */
67 <0x00 0x6f000000 0x00 0x 51 <0x00 0x6f000000 0x00 0x2000>, /* GICC */
68 <0x00 0x6f010000 0x00 0x 52 <0x00 0x6f010000 0x00 0x1000>, /* GICH */
69 <0x00 0x6f020000 0x00 0x 53 <0x00 0x6f020000 0x00 0x2000>; /* GICV */
70 54
71 /* vcpumntirq: virtual CPU int 55 /* vcpumntirq: virtual CPU interface maintenance interrupt */
72 interrupts = <GIC_PPI 9 IRQ_TY 56 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
73 57
74 gic_its: msi-controller@182000 58 gic_its: msi-controller@1820000 {
75 compatible = "arm,gic- 59 compatible = "arm,gic-v3-its";
76 reg = <0x00 0x01820000 60 reg = <0x00 0x01820000 0x00 0x10000>;
77 socionext,synquacer-pr 61 socionext,synquacer-pre-its = <0x1000000 0x400000>;
78 msi-controller; 62 msi-controller;
79 #msi-cells = <1>; 63 #msi-cells = <1>;
80 }; 64 };
81 }; 65 };
82 66
83 main_gpio_intr: interrupt-controller@a !! 67 main_gpio_intr: interrupt-controller0 {
84 compatible = "ti,sci-intr"; 68 compatible = "ti,sci-intr";
85 reg = <0x00 0x00a00000 0x00 0x <<
86 ti,intr-trigger-type = <1>; 69 ti,intr-trigger-type = <1>;
87 interrupt-controller; 70 interrupt-controller;
88 interrupt-parent = <&gic500>; 71 interrupt-parent = <&gic500>;
89 #interrupt-cells = <1>; 72 #interrupt-cells = <1>;
90 ti,sci = <&dmsc>; 73 ti,sci = <&dmsc>;
91 ti,sci-dev-id = <131>; 74 ti,sci-dev-id = <131>;
92 ti,interrupt-ranges = <8 392 5 75 ti,interrupt-ranges = <8 392 56>;
93 }; 76 };
94 77
95 main_navss: bus@30000000 { 78 main_navss: bus@30000000 {
96 compatible = "simple-bus"; !! 79 compatible = "simple-mfd";
97 #address-cells = <2>; 80 #address-cells = <2>;
98 #size-cells = <2>; 81 #size-cells = <2>;
99 ranges = <0x00 0x30000000 0x00 82 ranges = <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>;
100 ti,sci-dev-id = <199>; 83 ti,sci-dev-id = <199>;
101 dma-coherent; 84 dma-coherent;
102 dma-ranges; 85 dma-ranges;
103 86
104 main_navss_intr: interrupt-con !! 87 main_navss_intr: interrupt-controller1 {
105 compatible = "ti,sci-i 88 compatible = "ti,sci-intr";
106 reg = <0x00 0x310e0000 <<
107 ti,intr-trigger-type = 89 ti,intr-trigger-type = <4>;
108 interrupt-controller; 90 interrupt-controller;
109 interrupt-parent = <&g 91 interrupt-parent = <&gic500>;
110 #interrupt-cells = <1> 92 #interrupt-cells = <1>;
111 ti,sci = <&dmsc>; 93 ti,sci = <&dmsc>;
112 ti,sci-dev-id = <213>; 94 ti,sci-dev-id = <213>;
113 ti,interrupt-ranges = 95 ti,interrupt-ranges = <0 64 64>,
114 96 <64 448 64>,
115 97 <128 672 64>;
116 }; 98 };
117 99
118 main_udmass_inta: msi-controll 100 main_udmass_inta: msi-controller@33d00000 {
119 compatible = "ti,sci-i 101 compatible = "ti,sci-inta";
120 reg = <0x00 0x33d00000 102 reg = <0x00 0x33d00000 0x00 0x100000>;
121 interrupt-controller; 103 interrupt-controller;
122 #interrupt-cells = <0> 104 #interrupt-cells = <0>;
123 interrupt-parent = <&m 105 interrupt-parent = <&main_navss_intr>;
124 msi-controller; 106 msi-controller;
125 ti,sci = <&dmsc>; 107 ti,sci = <&dmsc>;
126 ti,sci-dev-id = <209>; 108 ti,sci-dev-id = <209>;
127 ti,interrupt-ranges = 109 ti,interrupt-ranges = <0 0 256>;
128 }; 110 };
129 111
130 secure_proxy_main: mailbox@32c 112 secure_proxy_main: mailbox@32c00000 {
131 compatible = "ti,am654 113 compatible = "ti,am654-secure-proxy";
132 #mbox-cells = <1>; 114 #mbox-cells = <1>;
133 reg-names = "target_da 115 reg-names = "target_data", "rt", "scfg";
134 reg = <0x00 0x32c00000 116 reg = <0x00 0x32c00000 0x00 0x100000>,
135 <0x00 0x32400000 117 <0x00 0x32400000 0x00 0x100000>,
136 <0x00 0x32800000 118 <0x00 0x32800000 0x00 0x100000>;
137 interrupt-names = "rx_ 119 interrupt-names = "rx_011";
138 interrupts = <GIC_SPI 120 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
139 }; 121 };
140 122
141 hwspinlock: spinlock@30e00000 <<
142 compatible = "ti,am654 <<
143 reg = <0x00 0x30e00000 <<
144 #hwlock-cells = <1>; <<
145 }; <<
146 <<
147 mailbox0_cluster0: mailbox@31f <<
148 compatible = "ti,am654 <<
149 reg = <0x00 0x31f80000 <<
150 #mbox-cells = <1>; <<
151 ti,mbox-num-users = <4 <<
152 ti,mbox-num-fifos = <1 <<
153 interrupt-parent = <&m <<
154 status = "disabled"; <<
155 }; <<
156 <<
157 mailbox0_cluster1: mailbox@31f <<
158 compatible = "ti,am654 <<
159 reg = <0x00 0x31f81000 <<
160 #mbox-cells = <1>; <<
161 ti,mbox-num-users = <4 <<
162 ti,mbox-num-fifos = <1 <<
163 interrupt-parent = <&m <<
164 status = "disabled"; <<
165 }; <<
166 <<
167 mailbox0_cluster2: mailbox@31f <<
168 compatible = "ti,am654 <<
169 reg = <0x00 0x31f82000 <<
170 #mbox-cells = <1>; <<
171 ti,mbox-num-users = <4 <<
172 ti,mbox-num-fifos = <1 <<
173 interrupt-parent = <&m <<
174 status = "disabled"; <<
175 }; <<
176 <<
177 mailbox0_cluster3: mailbox@31f <<
178 compatible = "ti,am654 <<
179 reg = <0x00 0x31f83000 <<
180 #mbox-cells = <1>; <<
181 ti,mbox-num-users = <4 <<
182 ti,mbox-num-fifos = <1 <<
183 interrupt-parent = <&m <<
184 status = "disabled"; <<
185 }; <<
186 <<
187 mailbox0_cluster4: mailbox@31f <<
188 compatible = "ti,am654 <<
189 reg = <0x00 0x31f84000 <<
190 #mbox-cells = <1>; <<
191 ti,mbox-num-users = <4 <<
192 ti,mbox-num-fifos = <1 <<
193 interrupt-parent = <&m <<
194 status = "disabled"; <<
195 }; <<
196 <<
197 mailbox0_cluster5: mailbox@31f <<
198 compatible = "ti,am654 <<
199 reg = <0x00 0x31f85000 <<
200 #mbox-cells = <1>; <<
201 ti,mbox-num-users = <4 <<
202 ti,mbox-num-fifos = <1 <<
203 interrupt-parent = <&m <<
204 status = "disabled"; <<
205 }; <<
206 <<
207 mailbox0_cluster6: mailbox@31f <<
208 compatible = "ti,am654 <<
209 reg = <0x00 0x31f86000 <<
210 #mbox-cells = <1>; <<
211 ti,mbox-num-users = <4 <<
212 ti,mbox-num-fifos = <1 <<
213 interrupt-parent = <&m <<
214 status = "disabled"; <<
215 }; <<
216 <<
217 mailbox0_cluster7: mailbox@31f <<
218 compatible = "ti,am654 <<
219 reg = <0x00 0x31f87000 <<
220 #mbox-cells = <1>; <<
221 ti,mbox-num-users = <4 <<
222 ti,mbox-num-fifos = <1 <<
223 interrupt-parent = <&m <<
224 status = "disabled"; <<
225 }; <<
226 <<
227 mailbox0_cluster8: mailbox@31f <<
228 compatible = "ti,am654 <<
229 reg = <0x00 0x31f88000 <<
230 #mbox-cells = <1>; <<
231 ti,mbox-num-users = <4 <<
232 ti,mbox-num-fifos = <1 <<
233 interrupt-parent = <&m <<
234 status = "disabled"; <<
235 }; <<
236 <<
237 mailbox0_cluster9: mailbox@31f <<
238 compatible = "ti,am654 <<
239 reg = <0x00 0x31f89000 <<
240 #mbox-cells = <1>; <<
241 ti,mbox-num-users = <4 <<
242 ti,mbox-num-fifos = <1 <<
243 interrupt-parent = <&m <<
244 status = "disabled"; <<
245 }; <<
246 <<
247 mailbox0_cluster10: mailbox@31 <<
248 compatible = "ti,am654 <<
249 reg = <0x00 0x31f8a000 <<
250 #mbox-cells = <1>; <<
251 ti,mbox-num-users = <4 <<
252 ti,mbox-num-fifos = <1 <<
253 interrupt-parent = <&m <<
254 status = "disabled"; <<
255 }; <<
256 <<
257 mailbox0_cluster11: mailbox@31 <<
258 compatible = "ti,am654 <<
259 reg = <0x00 0x31f8b000 <<
260 #mbox-cells = <1>; <<
261 ti,mbox-num-users = <4 <<
262 ti,mbox-num-fifos = <1 <<
263 interrupt-parent = <&m <<
264 status = "disabled"; <<
265 }; <<
266 <<
267 main_ringacc: ringacc@3c000000 123 main_ringacc: ringacc@3c000000 {
268 compatible = "ti,am654 124 compatible = "ti,am654-navss-ringacc";
269 reg = <0x00 0x3c000000 !! 125 reg = <0x00 0x3c000000 0x00 0x400000>,
270 <0x00 0x38000000 !! 126 <0x00 0x38000000 0x00 0x400000>,
271 <0x00 0x31120000 !! 127 <0x00 0x31120000 0x00 0x100>,
272 <0x00 0x33000000 !! 128 <0x00 0x33000000 0x00 0x40000>;
273 <0x00 0x31080000 !! 129 reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target";
274 reg-names = "rt", "fif <<
275 ti,num-rings = <1024>; 130 ti,num-rings = <1024>;
276 ti,sci-rm-range-gp-rin 131 ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */
277 ti,sci = <&dmsc>; 132 ti,sci = <&dmsc>;
278 ti,sci-dev-id = <211>; 133 ti,sci-dev-id = <211>;
279 msi-parent = <&main_ud 134 msi-parent = <&main_udmass_inta>;
280 }; 135 };
281 136
282 main_udmap: dma-controller@311 137 main_udmap: dma-controller@31150000 {
283 compatible = "ti,j721e 138 compatible = "ti,j721e-navss-main-udmap";
284 reg = <0x00 0x31150000 !! 139 reg = <0x00 0x31150000 0x00 0x100>,
285 <0x00 0x34000000 !! 140 <0x00 0x34000000 0x00 0x100000>,
286 <0x00 0x35000000 !! 141 <0x00 0x35000000 0x00 0x100000>;
287 <0x00 0x30b00000 !! 142 reg-names = "gcfg", "rchanrt", "tchanrt";
288 <0x00 0x30c00000 <<
289 <0x00 0x30d00000 <<
290 reg-names = "gcfg", "r <<
291 "tchan", " <<
292 msi-parent = <&main_ud 143 msi-parent = <&main_udmass_inta>;
293 #dma-cells = <1>; 144 #dma-cells = <1>;
294 145
295 ti,sci = <&dmsc>; 146 ti,sci = <&dmsc>;
296 ti,sci-dev-id = <212>; 147 ti,sci-dev-id = <212>;
297 ti,ringacc = <&main_ri 148 ti,ringacc = <&main_ringacc>;
298 149
299 ti,sci-rm-range-tchan 150 ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */
300 151 <0x0f>, /* TX_HCHAN */
301 152 <0x10>; /* TX_UHCHAN */
302 ti,sci-rm-range-rchan 153 ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */
303 154 <0x0b>, /* RX_HCHAN */
304 155 <0x0c>; /* RX_UHCHAN */
305 ti,sci-rm-range-rflow 156 ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */
306 }; 157 };
307 158
308 cpts@310d0000 { 159 cpts@310d0000 {
309 compatible = "ti,j721e 160 compatible = "ti,j721e-cpts";
310 reg = <0x00 0x310d0000 161 reg = <0x00 0x310d0000 0x00 0x400>;
311 reg-names = "cpts"; 162 reg-names = "cpts";
312 clocks = <&k3_clks 201 163 clocks = <&k3_clks 201 1>;
313 clock-names = "cpts"; 164 clock-names = "cpts";
314 interrupts-extended = 165 interrupts-extended = <&main_navss_intr 391>;
315 interrupt-names = "cpt 166 interrupt-names = "cpts";
316 ti,cpts-periodic-outpu 167 ti,cpts-periodic-outputs = <6>;
317 ti,cpts-ext-ts-inputs 168 ti,cpts-ext-ts-inputs = <8>;
318 }; 169 };
319 }; 170 };
320 171
321 cpsw0: ethernet@c000000 { <<
322 compatible = "ti,j7200-cpswxg- <<
323 #address-cells = <2>; <<
324 #size-cells = <2>; <<
325 reg = <0x00 0xc000000 0x00 0x2 <<
326 reg-names = "cpsw_nuss"; <<
327 ranges = <0x00 0x00 0x00 0xc00 <<
328 clocks = <&k3_clks 19 33>; <<
329 clock-names = "fck"; <<
330 power-domains = <&k3_pds 19 TI <<
331 <<
332 dmas = <&main_udmap 0xca00>, <<
333 <&main_udmap 0xca01>, <<
334 <&main_udmap 0xca02>, <<
335 <&main_udmap 0xca03>, <<
336 <&main_udmap 0xca04>, <<
337 <&main_udmap 0xca05>, <<
338 <&main_udmap 0xca06>, <<
339 <&main_udmap 0xca07>, <<
340 <&main_udmap 0x4a00>; <<
341 dma-names = "tx0", "tx1", "tx2 <<
342 "tx4", "tx5", "tx6 <<
343 "rx"; <<
344 <<
345 status = "disabled"; <<
346 <<
347 ethernet-ports { <<
348 #address-cells = <1>; <<
349 #size-cells = <0>; <<
350 cpsw0_port1: port@1 { <<
351 reg = <1>; <<
352 ti,mac-only; <<
353 label = "port1 <<
354 status = "disa <<
355 }; <<
356 <<
357 cpsw0_port2: port@2 { <<
358 reg = <2>; <<
359 ti,mac-only; <<
360 label = "port2 <<
361 status = "disa <<
362 }; <<
363 <<
364 cpsw0_port3: port@3 { <<
365 reg = <3>; <<
366 ti,mac-only; <<
367 label = "port3 <<
368 status = "disa <<
369 }; <<
370 <<
371 cpsw0_port4: port@4 { <<
372 reg = <4>; <<
373 ti,mac-only; <<
374 label = "port4 <<
375 status = "disa <<
376 }; <<
377 }; <<
378 <<
379 cpsw5g_mdio: mdio@f00 { <<
380 compatible = "ti,cpsw- <<
381 reg = <0x00 0xf00 0x00 <<
382 #address-cells = <1>; <<
383 #size-cells = <0>; <<
384 clocks = <&k3_clks 19 <<
385 clock-names = "fck"; <<
386 bus_freq = <1000000>; <<
387 status = "disabled"; <<
388 }; <<
389 <<
390 cpts@3d000 { <<
391 compatible = "ti,j721e <<
392 reg = <0x00 0x3d000 0x <<
393 clocks = <&k3_clks 19 <<
394 clock-names = "cpts"; <<
395 interrupts-extended = <<
396 interrupt-names = "cpt <<
397 ti,cpts-ext-ts-inputs <<
398 ti,cpts-periodic-outpu <<
399 }; <<
400 }; <<
401 <<
402 /* TIMERIO pad input CTRLMMR_TIMER*_CT <<
403 main_timerio_input: pinctrl@104200 { <<
404 compatible = "ti,j7200-padconf <<
405 reg = <0x0 0x104200 0x0 0x50>; <<
406 #pinctrl-cells = <1>; <<
407 pinctrl-single,register-width <<
408 pinctrl-single,function-mask = <<
409 }; <<
410 <<
411 /* TIMERIO pad output CTCTRLMMR_TIMERI <<
412 main_timerio_output: pinctrl@104280 { <<
413 compatible = "ti,j7200-padconf <<
414 reg = <0x0 0x104280 0x0 0x20>; <<
415 #pinctrl-cells = <1>; <<
416 pinctrl-single,register-width <<
417 pinctrl-single,function-mask = <<
418 }; <<
419 <<
420 main_pmx0: pinctrl@11c000 { 172 main_pmx0: pinctrl@11c000 {
421 compatible = "ti,j7200-padconf !! 173 compatible = "pinctrl-single";
422 /* Proxy 0 addressing */ 174 /* Proxy 0 addressing */
423 reg = <0x00 0x11c000 0x00 0x10 !! 175 reg = <0x00 0x11c000 0x00 0x2b4>;
424 #pinctrl-cells = <1>; <<
425 pinctrl-single,register-width <<
426 pinctrl-single,function-mask = <<
427 }; <<
428 <<
429 main_pmx1: pinctrl@11c11c { <<
430 compatible = "ti,j7200-padconf <<
431 /* Proxy 0 addressing */ <<
432 reg = <0x00 0x11c11c 0x00 0xc> <<
433 #pinctrl-cells = <1>; 176 #pinctrl-cells = <1>;
434 pinctrl-single,register-width 177 pinctrl-single,register-width = <32>;
435 pinctrl-single,function-mask = 178 pinctrl-single,function-mask = <0xffffffff>;
436 }; 179 };
437 180
438 main_uart0: serial@2800000 { 181 main_uart0: serial@2800000 {
439 compatible = "ti,j721e-uart", 182 compatible = "ti,j721e-uart", "ti,am654-uart";
440 reg = <0x00 0x02800000 0x00 0x 183 reg = <0x00 0x02800000 0x00 0x100>;
>> 184 reg-shift = <2>;
>> 185 reg-io-width = <4>;
441 interrupts = <GIC_SPI 192 IRQ_ 186 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
442 clock-frequency = <48000000>; 187 clock-frequency = <48000000>;
>> 188 current-speed = <115200>;
443 power-domains = <&k3_pds 146 T 189 power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>;
444 clocks = <&k3_clks 146 2>; 190 clocks = <&k3_clks 146 2>;
445 clock-names = "fclk"; 191 clock-names = "fclk";
446 status = "disabled"; <<
447 }; 192 };
448 193
449 main_uart1: serial@2810000 { 194 main_uart1: serial@2810000 {
450 compatible = "ti,j721e-uart", 195 compatible = "ti,j721e-uart", "ti,am654-uart";
451 reg = <0x00 0x02810000 0x00 0x 196 reg = <0x00 0x02810000 0x00 0x100>;
>> 197 reg-shift = <2>;
>> 198 reg-io-width = <4>;
452 interrupts = <GIC_SPI 193 IRQ_ 199 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
453 clock-frequency = <48000000>; 200 clock-frequency = <48000000>;
>> 201 current-speed = <115200>;
454 power-domains = <&k3_pds 278 T 202 power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>;
455 clocks = <&k3_clks 278 2>; 203 clocks = <&k3_clks 278 2>;
456 clock-names = "fclk"; 204 clock-names = "fclk";
457 status = "disabled"; <<
458 }; 205 };
459 206
460 main_uart2: serial@2820000 { 207 main_uart2: serial@2820000 {
461 compatible = "ti,j721e-uart", 208 compatible = "ti,j721e-uart", "ti,am654-uart";
462 reg = <0x00 0x02820000 0x00 0x 209 reg = <0x00 0x02820000 0x00 0x100>;
>> 210 reg-shift = <2>;
>> 211 reg-io-width = <4>;
463 interrupts = <GIC_SPI 194 IRQ_ 212 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
464 clock-frequency = <48000000>; 213 clock-frequency = <48000000>;
>> 214 current-speed = <115200>;
465 power-domains = <&k3_pds 279 T 215 power-domains = <&k3_pds 279 TI_SCI_PD_EXCLUSIVE>;
466 clocks = <&k3_clks 279 2>; 216 clocks = <&k3_clks 279 2>;
467 clock-names = "fclk"; 217 clock-names = "fclk";
468 status = "disabled"; <<
469 }; 218 };
470 219
471 main_uart3: serial@2830000 { 220 main_uart3: serial@2830000 {
472 compatible = "ti,j721e-uart", 221 compatible = "ti,j721e-uart", "ti,am654-uart";
473 reg = <0x00 0x02830000 0x00 0x 222 reg = <0x00 0x02830000 0x00 0x100>;
>> 223 reg-shift = <2>;
>> 224 reg-io-width = <4>;
474 interrupts = <GIC_SPI 195 IRQ_ 225 interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>;
475 clock-frequency = <48000000>; 226 clock-frequency = <48000000>;
>> 227 current-speed = <115200>;
476 power-domains = <&k3_pds 280 T 228 power-domains = <&k3_pds 280 TI_SCI_PD_EXCLUSIVE>;
477 clocks = <&k3_clks 280 2>; 229 clocks = <&k3_clks 280 2>;
478 clock-names = "fclk"; 230 clock-names = "fclk";
479 status = "disabled"; <<
480 }; 231 };
481 232
482 main_uart4: serial@2840000 { 233 main_uart4: serial@2840000 {
483 compatible = "ti,j721e-uart", 234 compatible = "ti,j721e-uart", "ti,am654-uart";
484 reg = <0x00 0x02840000 0x00 0x 235 reg = <0x00 0x02840000 0x00 0x100>;
>> 236 reg-shift = <2>;
>> 237 reg-io-width = <4>;
485 interrupts = <GIC_SPI 196 IRQ_ 238 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;
486 clock-frequency = <48000000>; 239 clock-frequency = <48000000>;
>> 240 current-speed = <115200>;
487 power-domains = <&k3_pds 281 T 241 power-domains = <&k3_pds 281 TI_SCI_PD_EXCLUSIVE>;
488 clocks = <&k3_clks 281 2>; 242 clocks = <&k3_clks 281 2>;
489 clock-names = "fclk"; 243 clock-names = "fclk";
490 status = "disabled"; <<
491 }; 244 };
492 245
493 main_uart5: serial@2850000 { 246 main_uart5: serial@2850000 {
494 compatible = "ti,j721e-uart", 247 compatible = "ti,j721e-uart", "ti,am654-uart";
495 reg = <0x00 0x02850000 0x00 0x 248 reg = <0x00 0x02850000 0x00 0x100>;
>> 249 reg-shift = <2>;
>> 250 reg-io-width = <4>;
496 interrupts = <GIC_SPI 197 IRQ_ 251 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
497 clock-frequency = <48000000>; 252 clock-frequency = <48000000>;
>> 253 current-speed = <115200>;
498 power-domains = <&k3_pds 282 T 254 power-domains = <&k3_pds 282 TI_SCI_PD_EXCLUSIVE>;
499 clocks = <&k3_clks 282 2>; 255 clocks = <&k3_clks 282 2>;
500 clock-names = "fclk"; 256 clock-names = "fclk";
501 status = "disabled"; <<
502 }; 257 };
503 258
504 main_uart6: serial@2860000 { 259 main_uart6: serial@2860000 {
505 compatible = "ti,j721e-uart", 260 compatible = "ti,j721e-uart", "ti,am654-uart";
506 reg = <0x00 0x02860000 0x00 0x 261 reg = <0x00 0x02860000 0x00 0x100>;
>> 262 reg-shift = <2>;
>> 263 reg-io-width = <4>;
507 interrupts = <GIC_SPI 198 IRQ_ 264 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>;
508 clock-frequency = <48000000>; 265 clock-frequency = <48000000>;
>> 266 current-speed = <115200>;
509 power-domains = <&k3_pds 283 T 267 power-domains = <&k3_pds 283 TI_SCI_PD_EXCLUSIVE>;
510 clocks = <&k3_clks 283 2>; 268 clocks = <&k3_clks 283 2>;
511 clock-names = "fclk"; 269 clock-names = "fclk";
512 status = "disabled"; <<
513 }; 270 };
514 271
515 main_uart7: serial@2870000 { 272 main_uart7: serial@2870000 {
516 compatible = "ti,j721e-uart", 273 compatible = "ti,j721e-uart", "ti,am654-uart";
517 reg = <0x00 0x02870000 0x00 0x 274 reg = <0x00 0x02870000 0x00 0x100>;
>> 275 reg-shift = <2>;
>> 276 reg-io-width = <4>;
518 interrupts = <GIC_SPI 199 IRQ_ 277 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
519 clock-frequency = <48000000>; 278 clock-frequency = <48000000>;
>> 279 current-speed = <115200>;
520 power-domains = <&k3_pds 284 T 280 power-domains = <&k3_pds 284 TI_SCI_PD_EXCLUSIVE>;
521 clocks = <&k3_clks 284 2>; 281 clocks = <&k3_clks 284 2>;
522 clock-names = "fclk"; 282 clock-names = "fclk";
523 status = "disabled"; <<
524 }; 283 };
525 284
526 main_uart8: serial@2880000 { 285 main_uart8: serial@2880000 {
527 compatible = "ti,j721e-uart", 286 compatible = "ti,j721e-uart", "ti,am654-uart";
528 reg = <0x00 0x02880000 0x00 0x 287 reg = <0x00 0x02880000 0x00 0x100>;
>> 288 reg-shift = <2>;
>> 289 reg-io-width = <4>;
529 interrupts = <GIC_SPI 248 IRQ_ 290 interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>;
530 clock-frequency = <48000000>; 291 clock-frequency = <48000000>;
>> 292 current-speed = <115200>;
531 power-domains = <&k3_pds 285 T 293 power-domains = <&k3_pds 285 TI_SCI_PD_EXCLUSIVE>;
532 clocks = <&k3_clks 285 2>; 294 clocks = <&k3_clks 285 2>;
533 clock-names = "fclk"; 295 clock-names = "fclk";
534 status = "disabled"; <<
535 }; 296 };
536 297
537 main_uart9: serial@2890000 { 298 main_uart9: serial@2890000 {
538 compatible = "ti,j721e-uart", 299 compatible = "ti,j721e-uart", "ti,am654-uart";
539 reg = <0x00 0x02890000 0x00 0x 300 reg = <0x00 0x02890000 0x00 0x100>;
>> 301 reg-shift = <2>;
>> 302 reg-io-width = <4>;
540 interrupts = <GIC_SPI 249 IRQ_ 303 interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>;
541 clock-frequency = <48000000>; 304 clock-frequency = <48000000>;
>> 305 current-speed = <115200>;
542 power-domains = <&k3_pds 286 T 306 power-domains = <&k3_pds 286 TI_SCI_PD_EXCLUSIVE>;
543 clocks = <&k3_clks 286 2>; 307 clocks = <&k3_clks 286 2>;
544 clock-names = "fclk"; 308 clock-names = "fclk";
545 status = "disabled"; <<
546 }; 309 };
547 310
548 main_i2c0: i2c@2000000 { 311 main_i2c0: i2c@2000000 {
549 compatible = "ti,j721e-i2c", " 312 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
550 reg = <0x00 0x2000000 0x00 0x1 313 reg = <0x00 0x2000000 0x00 0x100>;
551 interrupts = <GIC_SPI 200 IRQ_ 314 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>;
552 #address-cells = <1>; 315 #address-cells = <1>;
553 #size-cells = <0>; 316 #size-cells = <0>;
554 clock-names = "fck"; 317 clock-names = "fck";
555 clocks = <&k3_clks 187 1>; 318 clocks = <&k3_clks 187 1>;
556 power-domains = <&k3_pds 187 T 319 power-domains = <&k3_pds 187 TI_SCI_PD_SHARED>;
557 status = "disabled"; <<
558 }; 320 };
559 321
560 main_i2c1: i2c@2010000 { 322 main_i2c1: i2c@2010000 {
561 compatible = "ti,j721e-i2c", " 323 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
562 reg = <0x00 0x2010000 0x00 0x1 324 reg = <0x00 0x2010000 0x00 0x100>;
563 interrupts = <GIC_SPI 201 IRQ_ 325 interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>;
564 #address-cells = <1>; 326 #address-cells = <1>;
565 #size-cells = <0>; 327 #size-cells = <0>;
566 clock-names = "fck"; 328 clock-names = "fck";
567 clocks = <&k3_clks 188 1>; 329 clocks = <&k3_clks 188 1>;
568 power-domains = <&k3_pds 188 T 330 power-domains = <&k3_pds 188 TI_SCI_PD_EXCLUSIVE>;
569 status = "disabled"; <<
570 }; 331 };
571 332
572 main_i2c2: i2c@2020000 { 333 main_i2c2: i2c@2020000 {
573 compatible = "ti,j721e-i2c", " 334 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
574 reg = <0x00 0x2020000 0x00 0x1 335 reg = <0x00 0x2020000 0x00 0x100>;
575 interrupts = <GIC_SPI 202 IRQ_ 336 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
576 #address-cells = <1>; 337 #address-cells = <1>;
577 #size-cells = <0>; 338 #size-cells = <0>;
578 clock-names = "fck"; 339 clock-names = "fck";
579 clocks = <&k3_clks 189 1>; 340 clocks = <&k3_clks 189 1>;
580 power-domains = <&k3_pds 189 T 341 power-domains = <&k3_pds 189 TI_SCI_PD_EXCLUSIVE>;
581 status = "disabled"; <<
582 }; 342 };
583 343
584 main_i2c3: i2c@2030000 { 344 main_i2c3: i2c@2030000 {
585 compatible = "ti,j721e-i2c", " 345 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
586 reg = <0x00 0x2030000 0x00 0x1 346 reg = <0x00 0x2030000 0x00 0x100>;
587 interrupts = <GIC_SPI 203 IRQ_ 347 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>;
588 #address-cells = <1>; 348 #address-cells = <1>;
589 #size-cells = <0>; 349 #size-cells = <0>;
590 clock-names = "fck"; 350 clock-names = "fck";
591 clocks = <&k3_clks 190 1>; 351 clocks = <&k3_clks 190 1>;
592 power-domains = <&k3_pds 190 T 352 power-domains = <&k3_pds 190 TI_SCI_PD_EXCLUSIVE>;
593 status = "disabled"; <<
594 }; 353 };
595 354
596 main_i2c4: i2c@2040000 { 355 main_i2c4: i2c@2040000 {
597 compatible = "ti,j721e-i2c", " 356 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
598 reg = <0x00 0x2040000 0x00 0x1 357 reg = <0x00 0x2040000 0x00 0x100>;
599 interrupts = <GIC_SPI 204 IRQ_ 358 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>;
600 #address-cells = <1>; 359 #address-cells = <1>;
601 #size-cells = <0>; 360 #size-cells = <0>;
602 clock-names = "fck"; 361 clock-names = "fck";
603 clocks = <&k3_clks 191 1>; 362 clocks = <&k3_clks 191 1>;
604 power-domains = <&k3_pds 191 T 363 power-domains = <&k3_pds 191 TI_SCI_PD_EXCLUSIVE>;
605 status = "disabled"; <<
606 }; 364 };
607 365
608 main_i2c5: i2c@2050000 { 366 main_i2c5: i2c@2050000 {
609 compatible = "ti,j721e-i2c", " 367 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
610 reg = <0x00 0x2050000 0x00 0x1 368 reg = <0x00 0x2050000 0x00 0x100>;
611 interrupts = <GIC_SPI 205 IRQ_ 369 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
612 #address-cells = <1>; 370 #address-cells = <1>;
613 #size-cells = <0>; 371 #size-cells = <0>;
614 clock-names = "fck"; 372 clock-names = "fck";
615 clocks = <&k3_clks 192 1>; 373 clocks = <&k3_clks 192 1>;
616 power-domains = <&k3_pds 192 T 374 power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>;
617 status = "disabled"; <<
618 }; 375 };
619 376
620 main_i2c6: i2c@2060000 { 377 main_i2c6: i2c@2060000 {
621 compatible = "ti,j721e-i2c", " 378 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
622 reg = <0x00 0x2060000 0x00 0x1 379 reg = <0x00 0x2060000 0x00 0x100>;
623 interrupts = <GIC_SPI 206 IRQ_ 380 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
624 #address-cells = <1>; 381 #address-cells = <1>;
625 #size-cells = <0>; 382 #size-cells = <0>;
626 clock-names = "fck"; 383 clock-names = "fck";
627 clocks = <&k3_clks 193 1>; 384 clocks = <&k3_clks 193 1>;
628 power-domains = <&k3_pds 193 T 385 power-domains = <&k3_pds 193 TI_SCI_PD_EXCLUSIVE>;
629 status = "disabled"; <<
630 }; 386 };
631 387
632 main_sdhci0: mmc@4f80000 { 388 main_sdhci0: mmc@4f80000 {
633 compatible = "ti,j7200-sdhci-8 389 compatible = "ti,j7200-sdhci-8bit", "ti,j721e-sdhci-8bit";
634 reg = <0x00 0x04f80000 0x00 0x 390 reg = <0x00 0x04f80000 0x00 0x260>, <0x00 0x4f88000 0x00 0x134>;
635 interrupts = <GIC_SPI 3 IRQ_TY 391 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
636 power-domains = <&k3_pds 91 TI 392 power-domains = <&k3_pds 91 TI_SCI_PD_EXCLUSIVE>;
637 clock-names = "clk_ahb", "clk_ !! 393 clock-names = "clk_xin", "clk_ahb";
638 clocks = <&k3_clks 91 0>, <&k3 !! 394 clocks = <&k3_clks 91 3>, <&k3_clks 91 0>;
639 ti,otap-del-sel-legacy = <0x0> 395 ti,otap-del-sel-legacy = <0x0>;
640 ti,otap-del-sel-mmc-hs = <0x0> 396 ti,otap-del-sel-mmc-hs = <0x0>;
641 ti,otap-del-sel-ddr52 = <0x6>; 397 ti,otap-del-sel-ddr52 = <0x6>;
642 ti,otap-del-sel-hs200 = <0x8>; 398 ti,otap-del-sel-hs200 = <0x8>;
643 ti,otap-del-sel-hs400 = <0x5>; !! 399 ti,otap-del-sel-hs400 = <0x0>;
644 ti,itap-del-sel-legacy = <0x10 <<
645 ti,itap-del-sel-mmc-hs = <0xa> <<
646 ti,itap-del-sel-ddr52 = <0x3>; <<
647 ti,strobe-sel = <0x77>; 400 ti,strobe-sel = <0x77>;
648 ti,clkbuf-sel = <0x7>; <<
649 ti,trm-icp = <0x8>; 401 ti,trm-icp = <0x8>;
650 bus-width = <8>; 402 bus-width = <8>;
651 mmc-ddr-1_8v; 403 mmc-ddr-1_8v;
652 mmc-hs200-1_8v; <<
653 mmc-hs400-1_8v; <<
654 dma-coherent; 404 dma-coherent;
655 status = "disabled"; <<
656 }; 405 };
657 406
658 main_sdhci1: mmc@4fb0000 { 407 main_sdhci1: mmc@4fb0000 {
659 compatible = "ti,j7200-sdhci-4 408 compatible = "ti,j7200-sdhci-4bit", "ti,j721e-sdhci-4bit";
660 reg = <0x00 0x04fb0000 0x00 0x 409 reg = <0x00 0x04fb0000 0x00 0x260>, <0x00 0x4fb8000 0x00 0x134>;
661 interrupts = <GIC_SPI 4 IRQ_TY 410 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
662 power-domains = <&k3_pds 92 TI 411 power-domains = <&k3_pds 92 TI_SCI_PD_EXCLUSIVE>;
663 clock-names = "clk_ahb", "clk_ !! 412 clock-names = "clk_xin", "clk_ahb";
664 clocks = <&k3_clks 92 1>, <&k3 !! 413 clocks = <&k3_clks 92 2>, <&k3_clks 92 1>;
665 ti,otap-del-sel-legacy = <0x0> 414 ti,otap-del-sel-legacy = <0x0>;
666 ti,otap-del-sel-sd-hs = <0x0>; 415 ti,otap-del-sel-sd-hs = <0x0>;
667 ti,otap-del-sel-sdr12 = <0xf>; 416 ti,otap-del-sel-sdr12 = <0xf>;
668 ti,otap-del-sel-sdr25 = <0xf>; 417 ti,otap-del-sel-sdr25 = <0xf>;
669 ti,otap-del-sel-sdr50 = <0xc>; 418 ti,otap-del-sel-sdr50 = <0xc>;
670 ti,otap-del-sel-sdr104 = <0x5> 419 ti,otap-del-sel-sdr104 = <0x5>;
671 ti,otap-del-sel-ddr50 = <0xc>; 420 ti,otap-del-sel-ddr50 = <0xc>;
672 ti,itap-del-sel-legacy = <0x0> !! 421 no-1-8-v;
673 ti,itap-del-sel-sd-hs = <0x0>; <<
674 ti,itap-del-sel-sdr12 = <0x0>; <<
675 ti,itap-del-sel-sdr25 = <0x0>; <<
676 ti,clkbuf-sel = <0x7>; <<
677 ti,trm-icp = <0x8>; <<
678 dma-coherent; 422 dma-coherent;
679 status = "disabled"; <<
680 }; <<
681 <<
682 serdes_wiz0: wiz@5060000 { <<
683 compatible = "ti,j721e-wiz-10g <<
684 #address-cells = <1>; <<
685 #size-cells = <1>; <<
686 power-domains = <&k3_pds 292 T <<
687 clocks = <&k3_clks 292 11>, <& <<
688 clock-names = "fck", "core_ref <<
689 num-lanes = <4>; <<
690 #reset-cells = <1>; <<
691 ranges = <0x5060000 0x0 0x5060 <<
692 <<
693 assigned-clocks = <&k3_clks 29 <<
694 assigned-clock-parents = <&k3_ <<
695 <<
696 wiz0_pll0_refclk: pll0-refclk <<
697 clocks = <&k3_clks 292 <<
698 clock-output-names = " <<
699 #clock-cells = <0>; <<
700 assigned-clocks = <&wi <<
701 assigned-clock-parents <<
702 }; <<
703 <<
704 wiz0_pll1_refclk: pll1-refclk <<
705 clocks = <&k3_clks 292 <<
706 clock-output-names = " <<
707 #clock-cells = <0>; <<
708 assigned-clocks = <&wi <<
709 assigned-clock-parents <<
710 }; <<
711 <<
712 wiz0_refclk_dig: refclk-dig { <<
713 clocks = <&k3_clks 292 <<
714 clock-output-names = " <<
715 #clock-cells = <0>; <<
716 assigned-clocks = <&wi <<
717 assigned-clock-parents <<
718 }; <<
719 <<
720 wiz0_cmn_refclk_dig_div: cmn-r <<
721 clocks = <&wiz0_refclk <<
722 #clock-cells = <0>; <<
723 }; <<
724 <<
725 serdes0: serdes@5060000 { <<
726 compatible = "ti,j721e <<
727 reg = <0x05060000 0x00 <<
728 reg-names = "torrent_p <<
729 resets = <&serdes_wiz0 <<
730 reset-names = "torrent <<
731 clocks = <&wiz0_pll0_r <<
732 clock-names = "refclk" <<
733 #address-cells = <1>; <<
734 #size-cells = <0>; <<
735 }; <<
736 }; <<
737 <<
738 pcie1_rc: pcie@2910000 { <<
739 compatible = "ti,j7200-pcie-ho <<
740 reg = <0x00 0x02910000 0x00 0x <<
741 <0x00 0x02917000 0x00 0x <<
742 <0x00 0x0d800000 0x00 0x <<
743 <0x00 0x18000000 0x00 0x <<
744 reg-names = "intd_cfg", "user_ <<
745 interrupt-names = "link_state" <<
746 interrupts = <GIC_SPI 330 IRQ_ <<
747 device_type = "pci"; <<
748 ti,syscon-pcie-ctrl = <&scm_co <<
749 max-link-speed = <3>; <<
750 num-lanes = <4>; <<
751 power-domains = <&k3_pds 240 T <<
752 clocks = <&k3_clks 240 6>; <<
753 clock-names = "fck"; <<
754 #address-cells = <3>; <<
755 #size-cells = <2>; <<
756 bus-range = <0x0 0xff>; <<
757 cdns,no-bar-match-nbits = <64> <<
758 vendor-id = <0x104c>; <<
759 device-id = <0xb00f>; <<
760 msi-map = <0x0 &gic_its 0x0 0x <<
761 dma-coherent; <<
762 ranges = <0x01000000 0x0 0x180 <<
763 <0x02000000 0x0 0x180 <<
764 dma-ranges = <0x02000000 0x0 0 <<
765 status = "disabled"; <<
766 }; 423 };
767 424
768 usbss0: cdns-usb@4104000 { 425 usbss0: cdns-usb@4104000 {
769 compatible = "ti,j721e-usb"; 426 compatible = "ti,j721e-usb";
770 reg = <0x00 0x4104000 0x00 0x1 427 reg = <0x00 0x4104000 0x00 0x100>;
771 dma-coherent; 428 dma-coherent;
772 power-domains = <&k3_pds 288 T 429 power-domains = <&k3_pds 288 TI_SCI_PD_EXCLUSIVE>;
773 clocks = <&k3_clks 288 12>, <& 430 clocks = <&k3_clks 288 12>, <&k3_clks 288 3>;
774 clock-names = "ref", "lpm"; 431 clock-names = "ref", "lpm";
775 assigned-clocks = <&k3_clks 28 432 assigned-clocks = <&k3_clks 288 12>; /* USB2_REFCLK */
776 assigned-clock-parents = <&k3_ 433 assigned-clock-parents = <&k3_clks 288 13>; /* HFOSC0 */
777 #address-cells = <2>; 434 #address-cells = <2>;
778 #size-cells = <2>; 435 #size-cells = <2>;
779 ranges; 436 ranges;
780 437
781 usb0: usb@6000000 { 438 usb0: usb@6000000 {
782 compatible = "cdns,usb 439 compatible = "cdns,usb3";
783 reg = <0x00 0x6000000 440 reg = <0x00 0x6000000 0x00 0x10000>,
784 <0x00 0x6010000 441 <0x00 0x6010000 0x00 0x10000>,
785 <0x00 0x6020000 442 <0x00 0x6020000 0x00 0x10000>;
786 reg-names = "otg", "xh 443 reg-names = "otg", "xhci", "dev";
787 interrupts = <GIC_SPI 444 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */
788 <GIC_SPI 445 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, /* irq.6 */
789 <GIC_SPI 446 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; /* otgirq.0 */
790 interrupt-names = "hos 447 interrupt-names = "host",
791 "per 448 "peripheral",
792 "otg 449 "otg";
793 maximum-speed = "super 450 maximum-speed = "super-speed";
794 dr_mode = "otg"; 451 dr_mode = "otg";
795 cdns,phyrst-a-enable; 452 cdns,phyrst-a-enable;
796 }; 453 };
797 }; <<
798 <<
799 main_gpio0: gpio@600000 { <<
800 compatible = "ti,j721e-gpio", <<
801 reg = <0x00 0x00600000 0x00 0x <<
802 gpio-controller; <<
803 #gpio-cells = <2>; <<
804 interrupt-parent = <&main_gpio <<
805 interrupts = <145>, <146>, <14 <<
806 <149>; <<
807 interrupt-controller; <<
808 #interrupt-cells = <2>; <<
809 ti,ngpio = <69>; <<
810 ti,davinci-gpio-unbanked = <0> <<
811 power-domains = <&k3_pds 105 T <<
812 clocks = <&k3_clks 105 0>; <<
813 clock-names = "gpio"; <<
814 status = "disabled"; <<
815 }; <<
816 <<
817 main_gpio2: gpio@610000 { <<
818 compatible = "ti,j721e-gpio", <<
819 reg = <0x00 0x00610000 0x00 0x <<
820 gpio-controller; <<
821 #gpio-cells = <2>; <<
822 interrupt-parent = <&main_gpio <<
823 interrupts = <154>, <155>, <15 <<
824 <158>; <<
825 interrupt-controller; <<
826 #interrupt-cells = <2>; <<
827 ti,ngpio = <69>; <<
828 ti,davinci-gpio-unbanked = <0> <<
829 power-domains = <&k3_pds 107 T <<
830 clocks = <&k3_clks 107 0>; <<
831 clock-names = "gpio"; <<
832 status = "disabled"; <<
833 }; <<
834 <<
835 main_gpio4: gpio@620000 { <<
836 compatible = "ti,j721e-gpio", <<
837 reg = <0x00 0x00620000 0x00 0x <<
838 gpio-controller; <<
839 #gpio-cells = <2>; <<
840 interrupt-parent = <&main_gpio <<
841 interrupts = <163>, <164>, <16 <<
842 <167>; <<
843 interrupt-controller; <<
844 #interrupt-cells = <2>; <<
845 ti,ngpio = <69>; <<
846 ti,davinci-gpio-unbanked = <0> <<
847 power-domains = <&k3_pds 109 T <<
848 clocks = <&k3_clks 109 0>; <<
849 clock-names = "gpio"; <<
850 status = "disabled"; <<
851 }; <<
852 <<
853 main_gpio6: gpio@630000 { <<
854 compatible = "ti,j721e-gpio", <<
855 reg = <0x00 0x00630000 0x00 0x <<
856 gpio-controller; <<
857 #gpio-cells = <2>; <<
858 interrupt-parent = <&main_gpio <<
859 interrupts = <172>, <173>, <17 <<
860 <176>; <<
861 interrupt-controller; <<
862 #interrupt-cells = <2>; <<
863 ti,ngpio = <69>; <<
864 ti,davinci-gpio-unbanked = <0> <<
865 power-domains = <&k3_pds 111 T <<
866 clocks = <&k3_clks 111 0>; <<
867 clock-names = "gpio"; <<
868 status = "disabled"; <<
869 }; <<
870 <<
871 main_mcan0: can@2701000 { <<
872 compatible = "bosch,m_can"; <<
873 reg = <0x00 0x02701000 0x00 0x <<
874 <0x00 0x02708000 0x00 0x <<
875 reg-names = "m_can", "message_ <<
876 power-domains = <&k3_pds 156 T <<
877 clocks = <&k3_clks 156 0>, <&k <<
878 clock-names = "hclk", "cclk"; <<
879 interrupts = <GIC_SPI 124 IRQ_ <<
880 <GIC_SPI 125 IRQ_ <<
881 interrupt-names = "int0", "int <<
882 bosch,mram-cfg = <0x0 128 64 6 <<
883 status = "disabled"; <<
884 }; <<
885 <<
886 main_mcan1: can@2711000 { <<
887 compatible = "bosch,m_can"; <<
888 reg = <0x00 0x02711000 0x00 0x <<
889 <0x00 0x02718000 0x00 0x <<
890 reg-names = "m_can", "message_ <<
891 power-domains = <&k3_pds 158 T <<
892 clocks = <&k3_clks 158 0>, <&k <<
893 clock-names = "hclk", "cclk"; <<
894 interrupts = <GIC_SPI 127 IRQ_ <<
895 <GIC_SPI 128 IRQ_ <<
896 interrupt-names = "int0", "int <<
897 bosch,mram-cfg = <0x0 128 64 6 <<
898 status = "disabled"; <<
899 }; <<
900 <<
901 main_mcan2: can@2721000 { <<
902 compatible = "bosch,m_can"; <<
903 reg = <0x00 0x02721000 0x00 0x <<
904 <0x00 0x02728000 0x00 0x <<
905 reg-names = "m_can", "message_ <<
906 power-domains = <&k3_pds 160 T <<
907 clocks = <&k3_clks 160 0>, <&k <<
908 clock-names = "hclk", "cclk"; <<
909 interrupts = <GIC_SPI 130 IRQ_ <<
910 <GIC_SPI 131 IRQ_ <<
911 interrupt-names = "int0", "int <<
912 bosch,mram-cfg = <0x0 128 64 6 <<
913 status = "disabled"; <<
914 }; <<
915 <<
916 main_mcan3: can@2731000 { <<
917 compatible = "bosch,m_can"; <<
918 reg = <0x00 0x02731000 0x00 0x <<
919 <0x00 0x02738000 0x00 0x <<
920 reg-names = "m_can", "message_ <<
921 power-domains = <&k3_pds 161 T <<
922 clocks = <&k3_clks 161 0>, <&k <<
923 clock-names = "hclk", "cclk"; <<
924 interrupts = <GIC_SPI 133 IRQ_ <<
925 <GIC_SPI 134 IRQ_ <<
926 interrupt-names = "int0", "int <<
927 bosch,mram-cfg = <0x0 128 64 6 <<
928 status = "disabled"; <<
929 }; <<
930 <<
931 main_mcan4: can@2741000 { <<
932 compatible = "bosch,m_can"; <<
933 reg = <0x00 0x02741000 0x00 0x <<
934 <0x00 0x02748000 0x00 0x <<
935 reg-names = "m_can", "message_ <<
936 power-domains = <&k3_pds 162 T <<
937 clocks = <&k3_clks 162 0>, <&k <<
938 clock-names = "hclk", "cclk"; <<
939 interrupts = <GIC_SPI 136 IRQ_ <<
940 <GIC_SPI 137 IRQ_ <<
941 interrupt-names = "int0", "int <<
942 bosch,mram-cfg = <0x0 128 64 6 <<
943 status = "disabled"; <<
944 }; <<
945 <<
946 main_mcan5: can@2751000 { <<
947 compatible = "bosch,m_can"; <<
948 reg = <0x00 0x02751000 0x00 0x <<
949 <0x00 0x02758000 0x00 0x <<
950 reg-names = "m_can", "message_ <<
951 power-domains = <&k3_pds 163 T <<
952 clocks = <&k3_clks 163 0>, <&k <<
953 clock-names = "hclk", "cclk"; <<
954 interrupts = <GIC_SPI 139 IRQ_ <<
955 <GIC_SPI 140 IRQ_ <<
956 interrupt-names = "int0", "int <<
957 bosch,mram-cfg = <0x0 128 64 6 <<
958 status = "disabled"; <<
959 }; <<
960 <<
961 main_mcan6: can@2761000 { <<
962 compatible = "bosch,m_can"; <<
963 reg = <0x00 0x02761000 0x00 0x <<
964 <0x00 0x02768000 0x00 0x <<
965 reg-names = "m_can", "message_ <<
966 power-domains = <&k3_pds 164 T <<
967 clocks = <&k3_clks 164 0>, <&k <<
968 clock-names = "hclk", "cclk"; <<
969 interrupts = <GIC_SPI 142 IRQ_ <<
970 <GIC_SPI 143 IRQ_ <<
971 interrupt-names = "int0", "int <<
972 bosch,mram-cfg = <0x0 128 64 6 <<
973 status = "disabled"; <<
974 }; <<
975 <<
976 main_mcan7: can@2771000 { <<
977 compatible = "bosch,m_can"; <<
978 reg = <0x00 0x02771000 0x00 0x <<
979 <0x00 0x02778000 0x00 0x <<
980 reg-names = "m_can", "message_ <<
981 power-domains = <&k3_pds 165 T <<
982 clocks = <&k3_clks 165 0>, <&k <<
983 clock-names = "hclk", "cclk"; <<
984 interrupts = <GIC_SPI 145 IRQ_ <<
985 <GIC_SPI 146 IRQ_ <<
986 interrupt-names = "int0", "int <<
987 bosch,mram-cfg = <0x0 128 64 6 <<
988 status = "disabled"; <<
989 }; <<
990 <<
991 main_mcan8: can@2781000 { <<
992 compatible = "bosch,m_can"; <<
993 reg = <0x00 0x02781000 0x00 0x <<
994 <0x00 0x02788000 0x00 0x <<
995 reg-names = "m_can", "message_ <<
996 power-domains = <&k3_pds 166 T <<
997 clocks = <&k3_clks 166 0>, <&k <<
998 clock-names = "hclk", "cclk"; <<
999 interrupts = <GIC_SPI 576 IRQ_ <<
1000 <GIC_SPI 577 IRQ <<
1001 interrupt-names = "int0", "in <<
1002 bosch,mram-cfg = <0x0 128 64 <<
1003 status = "disabled"; <<
1004 }; <<
1005 <<
1006 main_mcan9: can@2791000 { <<
1007 compatible = "bosch,m_can"; <<
1008 reg = <0x00 0x02791000 0x00 0 <<
1009 <0x00 0x02798000 0x00 0 <<
1010 reg-names = "m_can", "message <<
1011 power-domains = <&k3_pds 167 <<
1012 clocks = <&k3_clks 167 0>, <& <<
1013 clock-names = "hclk", "cclk"; <<
1014 interrupts = <GIC_SPI 579 IRQ <<
1015 <GIC_SPI 580 IRQ <<
1016 interrupt-names = "int0", "in <<
1017 bosch,mram-cfg = <0x0 128 64 <<
1018 status = "disabled"; <<
1019 }; <<
1020 <<
1021 main_mcan10: can@27a1000 { <<
1022 compatible = "bosch,m_can"; <<
1023 reg = <0x00 0x027a1000 0x00 0 <<
1024 <0x00 0x027a8000 0x00 0 <<
1025 reg-names = "m_can", "message <<
1026 power-domains = <&k3_pds 168 <<
1027 clocks = <&k3_clks 168 0>, <& <<
1028 clock-names = "hclk", "cclk"; <<
1029 interrupts = <GIC_SPI 582 IRQ <<
1030 <GIC_SPI 583 IRQ <<
1031 interrupt-names = "int0", "in <<
1032 bosch,mram-cfg = <0x0 128 64 <<
1033 status = "disabled"; <<
1034 }; <<
1035 <<
1036 main_mcan11: can@27b1000 { <<
1037 compatible = "bosch,m_can"; <<
1038 reg = <0x00 0x027b1000 0x00 0 <<
1039 <0x00 0x027b8000 0x00 0 <<
1040 reg-names = "m_can", "message <<
1041 power-domains = <&k3_pds 169 <<
1042 clocks = <&k3_clks 169 0>, <& <<
1043 clock-names = "hclk", "cclk"; <<
1044 interrupts = <GIC_SPI 585 IRQ <<
1045 <GIC_SPI 586 IRQ <<
1046 interrupt-names = "int0", "in <<
1047 bosch,mram-cfg = <0x0 128 64 <<
1048 status = "disabled"; <<
1049 }; <<
1050 <<
1051 main_mcan12: can@27c1000 { <<
1052 compatible = "bosch,m_can"; <<
1053 reg = <0x00 0x027c1000 0x00 0 <<
1054 <0x00 0x027c8000 0x00 0 <<
1055 reg-names = "m_can", "message <<
1056 power-domains = <&k3_pds 170 <<
1057 clocks = <&k3_clks 170 0>, <& <<
1058 clock-names = "hclk", "cclk"; <<
1059 interrupts = <GIC_SPI 588 IRQ <<
1060 <GIC_SPI 589 IRQ <<
1061 interrupt-names = "int0", "in <<
1062 bosch,mram-cfg = <0x0 128 64 <<
1063 status = "disabled"; <<
1064 }; <<
1065 <<
1066 main_mcan13: can@27d1000 { <<
1067 compatible = "bosch,m_can"; <<
1068 reg = <0x00 0x027d1000 0x00 0 <<
1069 <0x00 0x027d8000 0x00 0 <<
1070 reg-names = "m_can", "message <<
1071 power-domains = <&k3_pds 171 <<
1072 clocks = <&k3_clks 171 0>, <& <<
1073 clock-names = "hclk", "cclk"; <<
1074 interrupts = <GIC_SPI 591 IRQ <<
1075 <GIC_SPI 592 IRQ <<
1076 interrupt-names = "int0", "in <<
1077 bosch,mram-cfg = <0x0 128 64 <<
1078 status = "disabled"; <<
1079 }; <<
1080 <<
1081 main_mcan14: can@2681000 { <<
1082 compatible = "bosch,m_can"; <<
1083 reg = <0x00 0x02681000 0x00 0 <<
1084 <0x00 0x02688000 0x00 0 <<
1085 reg-names = "m_can", "message <<
1086 power-domains = <&k3_pds 150 <<
1087 clocks = <&k3_clks 150 0>, <& <<
1088 clock-names = "hclk", "cclk"; <<
1089 interrupts = <GIC_SPI 594 IRQ <<
1090 <GIC_SPI 595 IRQ <<
1091 interrupt-names = "int0", "in <<
1092 bosch,mram-cfg = <0x0 128 64 <<
1093 status = "disabled"; <<
1094 }; <<
1095 <<
1096 main_mcan15: can@2691000 { <<
1097 compatible = "bosch,m_can"; <<
1098 reg = <0x00 0x02691000 0x00 0 <<
1099 <0x00 0x02698000 0x00 0 <<
1100 reg-names = "m_can", "message <<
1101 power-domains = <&k3_pds 151 <<
1102 clocks = <&k3_clks 151 0>, <& <<
1103 clock-names = "hclk", "cclk"; <<
1104 interrupts = <GIC_SPI 597 IRQ <<
1105 <GIC_SPI 598 IRQ <<
1106 interrupt-names = "int0", "in <<
1107 bosch,mram-cfg = <0x0 128 64 <<
1108 status = "disabled"; <<
1109 }; <<
1110 <<
1111 main_mcan16: can@26a1000 { <<
1112 compatible = "bosch,m_can"; <<
1113 reg = <0x00 0x026a1000 0x00 0 <<
1114 <0x00 0x026a8000 0x00 0 <<
1115 reg-names = "m_can", "message <<
1116 power-domains = <&k3_pds 152 <<
1117 clocks = <&k3_clks 152 0>, <& <<
1118 clock-names = "hclk", "cclk"; <<
1119 interrupts = <GIC_SPI 784 IRQ <<
1120 <GIC_SPI 785 IRQ <<
1121 interrupt-names = "int0", "in <<
1122 bosch,mram-cfg = <0x0 128 64 <<
1123 status = "disabled"; <<
1124 }; <<
1125 <<
1126 main_mcan17: can@26b1000 { <<
1127 compatible = "bosch,m_can"; <<
1128 reg = <0x00 0x026b1000 0x00 0 <<
1129 <0x00 0x026b8000 0x00 0 <<
1130 reg-names = "m_can", "message <<
1131 power-domains = <&k3_pds 153 <<
1132 clocks = <&k3_clks 153 0>, <& <<
1133 clock-names = "hclk", "cclk"; <<
1134 interrupts = <GIC_SPI 787 IRQ <<
1135 <GIC_SPI 788 IRQ <<
1136 interrupt-names = "int0", "in <<
1137 bosch,mram-cfg = <0x0 128 64 <<
1138 status = "disabled"; <<
1139 }; <<
1140 <<
1141 main_spi0: spi@2100000 { <<
1142 compatible = "ti,am654-mcspi" <<
1143 reg = <0x00 0x02100000 0x00 0 <<
1144 interrupts = <GIC_SPI 184 IRQ <<
1145 #address-cells = <1>; <<
1146 #size-cells = <0>; <<
1147 power-domains = <&k3_pds 266 <<
1148 clocks = <&k3_clks 266 1>; <<
1149 status = "disabled"; <<
1150 }; <<
1151 <<
1152 main_spi1: spi@2110000 { <<
1153 compatible = "ti,am654-mcspi" <<
1154 reg = <0x00 0x02110000 0x00 0 <<
1155 interrupts = <GIC_SPI 185 IRQ <<
1156 #address-cells = <1>; <<
1157 #size-cells = <0>; <<
1158 power-domains = <&k3_pds 267 <<
1159 clocks = <&k3_clks 267 1>; <<
1160 status = "disabled"; <<
1161 }; <<
1162 <<
1163 main_spi2: spi@2120000 { <<
1164 compatible = "ti,am654-mcspi" <<
1165 reg = <0x00 0x02120000 0x00 0 <<
1166 interrupts = <GIC_SPI 186 IRQ <<
1167 #address-cells = <1>; <<
1168 #size-cells = <0>; <<
1169 power-domains = <&k3_pds 268 <<
1170 clocks = <&k3_clks 268 1>; <<
1171 status = "disabled"; <<
1172 }; <<
1173 <<
1174 main_spi3: spi@2130000 { <<
1175 compatible = "ti,am654-mcspi" <<
1176 reg = <0x00 0x02130000 0x00 0 <<
1177 interrupts = <GIC_SPI 187 IRQ <<
1178 #address-cells = <1>; <<
1179 #size-cells = <0>; <<
1180 power-domains = <&k3_pds 269 <<
1181 clocks = <&k3_clks 269 1>; <<
1182 status = "disabled"; <<
1183 }; <<
1184 <<
1185 main_spi4: spi@2140000 { <<
1186 compatible = "ti,am654-mcspi" <<
1187 reg = <0x00 0x02140000 0x00 0 <<
1188 interrupts = <GIC_SPI 188 IRQ <<
1189 #address-cells = <1>; <<
1190 #size-cells = <0>; <<
1191 power-domains = <&k3_pds 270 <<
1192 clocks = <&k3_clks 270 1>; <<
1193 status = "disabled"; <<
1194 }; <<
1195 <<
1196 main_spi5: spi@2150000 { <<
1197 compatible = "ti,am654-mcspi" <<
1198 reg = <0x00 0x02150000 0x00 0 <<
1199 interrupts = <GIC_SPI 189 IRQ <<
1200 #address-cells = <1>; <<
1201 #size-cells = <0>; <<
1202 power-domains = <&k3_pds 271 <<
1203 clocks = <&k3_clks 271 1>; <<
1204 status = "disabled"; <<
1205 }; <<
1206 <<
1207 main_spi6: spi@2160000 { <<
1208 compatible = "ti,am654-mcspi" <<
1209 reg = <0x00 0x02160000 0x00 0 <<
1210 interrupts = <GIC_SPI 190 IRQ <<
1211 #address-cells = <1>; <<
1212 #size-cells = <0>; <<
1213 power-domains = <&k3_pds 272 <<
1214 clocks = <&k3_clks 272 1>; <<
1215 status = "disabled"; <<
1216 }; <<
1217 <<
1218 main_spi7: spi@2170000 { <<
1219 compatible = "ti,am654-mcspi" <<
1220 reg = <0x00 0x02170000 0x00 0 <<
1221 interrupts = <GIC_SPI 191 IRQ <<
1222 #address-cells = <1>; <<
1223 #size-cells = <0>; <<
1224 power-domains = <&k3_pds 273 <<
1225 clocks = <&k3_clks 273 1>; <<
1226 status = "disabled"; <<
1227 }; <<
1228 <<
1229 watchdog0: watchdog@2200000 { <<
1230 compatible = "ti,j7-rti-wdt"; <<
1231 reg = <0x0 0x2200000 0x0 0x10 <<
1232 clocks = <&k3_clks 252 1>; <<
1233 power-domains = <&k3_pds 252 <<
1234 assigned-clocks = <&k3_clks 2 <<
1235 assigned-clock-parents = <&k3 <<
1236 }; <<
1237 <<
1238 watchdog1: watchdog@2210000 { <<
1239 compatible = "ti,j7-rti-wdt"; <<
1240 reg = <0x0 0x2210000 0x0 0x10 <<
1241 clocks = <&k3_clks 253 1>; <<
1242 power-domains = <&k3_pds 253 <<
1243 assigned-clocks = <&k3_clks 2 <<
1244 assigned-clock-parents = <&k3 <<
1245 }; <<
1246 <<
1247 main_timer0: timer@2400000 { <<
1248 compatible = "ti,am654-timer" <<
1249 reg = <0x00 0x2400000 0x00 0x <<
1250 interrupts = <GIC_SPI 224 IRQ <<
1251 clocks = <&k3_clks 49 1>; <<
1252 clock-names = "fck"; <<
1253 assigned-clocks = <&k3_clks 4 <<
1254 assigned-clock-parents = <&k3 <<
1255 power-domains = <&k3_pds 49 T <<
1256 ti,timer-pwm; <<
1257 }; <<
1258 <<
1259 main_timer1: timer@2410000 { <<
1260 compatible = "ti,am654-timer" <<
1261 reg = <0x00 0x2410000 0x00 0x <<
1262 interrupts = <GIC_SPI 225 IRQ <<
1263 clocks = <&k3_clks 50 1>; <<
1264 clock-names = "fck"; <<
1265 assigned-clocks = <&k3_clks 5 <<
1266 assigned-clock-parents = <&k3 <<
1267 power-domains = <&k3_pds 50 T <<
1268 ti,timer-pwm; <<
1269 }; <<
1270 <<
1271 main_timer2: timer@2420000 { <<
1272 compatible = "ti,am654-timer" <<
1273 reg = <0x00 0x2420000 0x00 0x <<
1274 interrupts = <GIC_SPI 226 IRQ <<
1275 clocks = <&k3_clks 51 1>; <<
1276 clock-names = "fck"; <<
1277 assigned-clocks = <&k3_clks 5 <<
1278 assigned-clock-parents = <&k3 <<
1279 power-domains = <&k3_pds 49 T <<
1280 ti,timer-pwm; <<
1281 }; <<
1282 <<
1283 main_timer3: timer@2430000 { <<
1284 compatible = "ti,am654-timer" <<
1285 reg = <0x00 0x2430000 0x00 0x <<
1286 interrupts = <GIC_SPI 227 IRQ <<
1287 clocks = <&k3_clks 52 1>; <<
1288 clock-names = "fck"; <<
1289 assigned-clocks = <&k3_clks 5 <<
1290 assigned-clock-parents = <&k3 <<
1291 power-domains = <&k3_pds 52 T <<
1292 ti,timer-pwm; <<
1293 }; <<
1294 <<
1295 main_timer4: timer@2440000 { <<
1296 compatible = "ti,am654-timer" <<
1297 reg = <0x00 0x2440000 0x00 0x <<
1298 interrupts = <GIC_SPI 228 IRQ <<
1299 clocks = <&k3_clks 53 1>; <<
1300 clock-names = "fck"; <<
1301 assigned-clocks = <&k3_clks 5 <<
1302 assigned-clock-parents = <&k3 <<
1303 power-domains = <&k3_pds 53 T <<
1304 ti,timer-pwm; <<
1305 }; <<
1306 <<
1307 main_timer5: timer@2450000 { <<
1308 compatible = "ti,am654-timer" <<
1309 reg = <0x00 0x2450000 0x00 0x <<
1310 interrupts = <GIC_SPI 229 IRQ <<
1311 clocks = <&k3_clks 54 1>; <<
1312 clock-names = "fck"; <<
1313 assigned-clocks = <&k3_clks 5 <<
1314 assigned-clock-parents = <&k3 <<
1315 power-domains = <&k3_pds 54 T <<
1316 ti,timer-pwm; <<
1317 }; <<
1318 <<
1319 main_timer6: timer@2460000 { <<
1320 compatible = "ti,am654-timer" <<
1321 reg = <0x00 0x2460000 0x00 0x <<
1322 interrupts = <GIC_SPI 230 IRQ <<
1323 clocks = <&k3_clks 55 1>; <<
1324 clock-names = "fck"; <<
1325 assigned-clocks = <&k3_clks 5 <<
1326 assigned-clock-parents = <&k3 <<
1327 power-domains = <&k3_pds 55 T <<
1328 ti,timer-pwm; <<
1329 }; <<
1330 <<
1331 main_timer7: timer@2470000 { <<
1332 compatible = "ti,am654-timer" <<
1333 reg = <0x00 0x2470000 0x00 0x <<
1334 interrupts = <GIC_SPI 231 IRQ <<
1335 clocks = <&k3_clks 57 1>; <<
1336 clock-names = "fck"; <<
1337 assigned-clocks = <&k3_clks 5 <<
1338 assigned-clock-parents = <&k3 <<
1339 power-domains = <&k3_pds 57 T <<
1340 ti,timer-pwm; <<
1341 }; <<
1342 <<
1343 main_timer8: timer@2480000 { <<
1344 compatible = "ti,am654-timer" <<
1345 reg = <0x00 0x2480000 0x00 0x <<
1346 interrupts = <GIC_SPI 232 IRQ <<
1347 clocks = <&k3_clks 58 1>; <<
1348 clock-names = "fck"; <<
1349 assigned-clocks = <&k3_clks 5 <<
1350 assigned-clock-parents = <&k3 <<
1351 power-domains = <&k3_pds 58 T <<
1352 ti,timer-pwm; <<
1353 }; <<
1354 <<
1355 main_timer9: timer@2490000 { <<
1356 compatible = "ti,am654-timer" <<
1357 reg = <0x00 0x2490000 0x00 0x <<
1358 interrupts = <GIC_SPI 233 IRQ <<
1359 clocks = <&k3_clks 59 1>; <<
1360 clock-names = "fck"; <<
1361 assigned-clocks = <&k3_clks 5 <<
1362 assigned-clock-parents = <&k3 <<
1363 power-domains = <&k3_pds 59 T <<
1364 ti,timer-pwm; <<
1365 }; <<
1366 <<
1367 main_timer10: timer@24a0000 { <<
1368 compatible = "ti,am654-timer" <<
1369 reg = <0x00 0x24a0000 0x00 0x <<
1370 interrupts = <GIC_SPI 234 IRQ <<
1371 clocks = <&k3_clks 60 1>; <<
1372 clock-names = "fck"; <<
1373 assigned-clocks = <&k3_clks 6 <<
1374 assigned-clock-parents = <&k3 <<
1375 power-domains = <&k3_pds 60 T <<
1376 ti,timer-pwm; <<
1377 }; <<
1378 <<
1379 main_timer11: timer@24b0000 { <<
1380 compatible = "ti,am654-timer" <<
1381 reg = <0x00 0x24b0000 0x00 0x <<
1382 interrupts = <GIC_SPI 235 IRQ <<
1383 clocks = <&k3_clks 62 1>; <<
1384 clock-names = "fck"; <<
1385 assigned-clocks = <&k3_clks 6 <<
1386 assigned-clock-parents = <&k3 <<
1387 power-domains = <&k3_pds 62 T <<
1388 ti,timer-pwm; <<
1389 }; <<
1390 <<
1391 main_timer12: timer@24c0000 { <<
1392 compatible = "ti,am654-timer" <<
1393 reg = <0x00 0x24c0000 0x00 0x <<
1394 interrupts = <GIC_SPI 236 IRQ <<
1395 clocks = <&k3_clks 63 1>; <<
1396 clock-names = "fck"; <<
1397 assigned-clocks = <&k3_clks 6 <<
1398 assigned-clock-parents = <&k3 <<
1399 power-domains = <&k3_pds 63 T <<
1400 ti,timer-pwm; <<
1401 }; <<
1402 <<
1403 main_timer13: timer@24d0000 { <<
1404 compatible = "ti,am654-timer" <<
1405 reg = <0x00 0x24d0000 0x00 0x <<
1406 interrupts = <GIC_SPI 237 IRQ <<
1407 clocks = <&k3_clks 64 1>; <<
1408 clock-names = "fck"; <<
1409 assigned-clocks = <&k3_clks 6 <<
1410 assigned-clock-parents = <&k3 <<
1411 power-domains = <&k3_pds 64 T <<
1412 ti,timer-pwm; <<
1413 }; <<
1414 <<
1415 main_timer14: timer@24e0000 { <<
1416 compatible = "ti,am654-timer" <<
1417 reg = <0x00 0x24e0000 0x00 0x <<
1418 interrupts = <GIC_SPI 238 IRQ <<
1419 clocks = <&k3_clks 65 1>; <<
1420 clock-names = "fck"; <<
1421 assigned-clocks = <&k3_clks 6 <<
1422 assigned-clock-parents = <&k3 <<
1423 power-domains = <&k3_pds 65 T <<
1424 ti,timer-pwm; <<
1425 }; <<
1426 <<
1427 main_timer15: timer@24f0000 { <<
1428 compatible = "ti,am654-timer" <<
1429 reg = <0x00 0x24f0000 0x00 0x <<
1430 interrupts = <GIC_SPI 239 IRQ <<
1431 clocks = <&k3_clks 66 1>; <<
1432 clock-names = "fck"; <<
1433 assigned-clocks = <&k3_clks 6 <<
1434 assigned-clock-parents = <&k3 <<
1435 power-domains = <&k3_pds 66 T <<
1436 ti,timer-pwm; <<
1437 }; <<
1438 <<
1439 main_timer16: timer@2500000 { <<
1440 compatible = "ti,am654-timer" <<
1441 reg = <0x00 0x2500000 0x00 0x <<
1442 interrupts = <GIC_SPI 240 IRQ <<
1443 clocks = <&k3_clks 67 1>; <<
1444 clock-names = "fck"; <<
1445 assigned-clocks = <&k3_clks 6 <<
1446 assigned-clock-parents = <&k3 <<
1447 power-domains = <&k3_pds 67 T <<
1448 ti,timer-pwm; <<
1449 }; <<
1450 <<
1451 main_timer17: timer@2510000 { <<
1452 compatible = "ti,am654-timer" <<
1453 reg = <0x00 0x2510000 0x00 0x <<
1454 interrupts = <GIC_SPI 241 IRQ <<
1455 clocks = <&k3_clks 68 1>; <<
1456 clock-names = "fck"; <<
1457 assigned-clocks = <&k3_clks 6 <<
1458 assigned-clock-parents = <&k3 <<
1459 power-domains = <&k3_pds 68 T <<
1460 ti,timer-pwm; <<
1461 }; <<
1462 <<
1463 main_timer18: timer@2520000 { <<
1464 compatible = "ti,am654-timer" <<
1465 reg = <0x00 0x2520000 0x00 0x <<
1466 interrupts = <GIC_SPI 242 IRQ <<
1467 clocks = <&k3_clks 69 1>; <<
1468 clock-names = "fck"; <<
1469 assigned-clocks = <&k3_clks 6 <<
1470 assigned-clock-parents = <&k3 <<
1471 power-domains = <&k3_pds 69 T <<
1472 ti,timer-pwm; <<
1473 }; <<
1474 <<
1475 main_timer19: timer@2530000 { <<
1476 compatible = "ti,am654-timer" <<
1477 reg = <0x00 0x2530000 0x00 0x <<
1478 interrupts = <GIC_SPI 243 IRQ <<
1479 clocks = <&k3_clks 70 1>; <<
1480 clock-names = "fck"; <<
1481 assigned-clocks = <&k3_clks 7 <<
1482 assigned-clock-parents = <&k3 <<
1483 power-domains = <&k3_pds 70 T <<
1484 ti,timer-pwm; <<
1485 }; <<
1486 <<
1487 main_r5fss0: r5fss@5c00000 { <<
1488 compatible = "ti,j7200-r5fss" <<
1489 ti,cluster-mode = <1>; <<
1490 #address-cells = <1>; <<
1491 #size-cells = <1>; <<
1492 ranges = <0x5c00000 0x00 0x5c <<
1493 <0x5d00000 0x00 0x5d <<
1494 power-domains = <&k3_pds 243 <<
1495 <<
1496 main_r5fss0_core0: r5f@5c0000 <<
1497 compatible = "ti,j720 <<
1498 reg = <0x5c00000 0x00 <<
1499 <0x5c10000 0x00 <<
1500 reg-names = "atcm", " <<
1501 ti,sci = <&dmsc>; <<
1502 ti,sci-dev-id = <245> <<
1503 ti,sci-proc-ids = <0x <<
1504 resets = <&k3_reset 2 <<
1505 firmware-name = "j720 <<
1506 ti,atcm-enable = <1>; <<
1507 ti,btcm-enable = <1>; <<
1508 ti,loczrama = <1>; <<
1509 }; <<
1510 <<
1511 main_r5fss0_core1: r5f@5d0000 <<
1512 compatible = "ti,j720 <<
1513 reg = <0x5d00000 0x00 <<
1514 <0x5d10000 0x00 <<
1515 reg-names = "atcm", " <<
1516 ti,sci = <&dmsc>; <<
1517 ti,sci-dev-id = <246> <<
1518 ti,sci-proc-ids = <0x <<
1519 resets = <&k3_reset 2 <<
1520 firmware-name = "j720 <<
1521 ti,atcm-enable = <1>; <<
1522 ti,btcm-enable = <1>; <<
1523 ti,loczrama = <1>; <<
1524 }; <<
1525 }; <<
1526 <<
1527 main_esm: esm@700000 { <<
1528 compatible = "ti,j721e-esm"; <<
1529 reg = <0x0 0x700000 0x0 0x100 <<
1530 ti,esm-pins = <656>, <657>; <<
1531 }; 454 };
1532 }; 455 };
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