1 // SPDX-License-Identifier: GPL-2.0-only OR MI !! 1 // SPDX-License-Identifier: GPL-2.0
2 /* 2 /*
3 * Device Tree Source for J7200 SoC Family Mai 3 * Device Tree Source for J7200 SoC Family Main Domain peripherals
4 * 4 *
5 * Copyright (C) 2020-2024 Texas Instruments I !! 5 * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
6 */ 6 */
7 7
8 / { 8 / {
9 serdes_refclk: serdes-refclk { 9 serdes_refclk: serdes-refclk {
10 #clock-cells = <0>; 10 #clock-cells = <0>;
11 compatible = "fixed-clock"; 11 compatible = "fixed-clock";
12 }; 12 };
13 }; 13 };
14 14
15 &cbass_main { 15 &cbass_main {
16 msmc_ram: sram@70000000 { 16 msmc_ram: sram@70000000 {
17 compatible = "mmio-sram"; 17 compatible = "mmio-sram";
18 reg = <0x00 0x70000000 0x00 0x 18 reg = <0x00 0x70000000 0x00 0x100000>;
19 #address-cells = <1>; 19 #address-cells = <1>;
20 #size-cells = <1>; 20 #size-cells = <1>;
21 ranges = <0x00 0x00 0x70000000 21 ranges = <0x00 0x00 0x70000000 0x100000>;
22 22
23 atf-sram@0 { 23 atf-sram@0 {
24 reg = <0x00 0x20000>; 24 reg = <0x00 0x20000>;
25 }; 25 };
26 }; 26 };
27 27
28 scm_conf: scm-conf@100000 { 28 scm_conf: scm-conf@100000 {
29 compatible = "ti,j721e-system- 29 compatible = "ti,j721e-system-controller", "syscon", "simple-mfd";
30 reg = <0x00 0x00100000 0x00 0x 30 reg = <0x00 0x00100000 0x00 0x1c000>;
31 #address-cells = <1>; 31 #address-cells = <1>;
32 #size-cells = <1>; 32 #size-cells = <1>;
33 ranges = <0x00 0x00 0x00100000 33 ranges = <0x00 0x00 0x00100000 0x1c000>;
34 34
35 serdes_ln_ctrl: mux-controller 35 serdes_ln_ctrl: mux-controller@4080 {
36 compatible = "reg-mux" !! 36 compatible = "mmio-mux";
37 reg = <0x4080 0x20>; <<
38 #mux-control-cells = < 37 #mux-control-cells = <1>;
39 mux-reg-masks = <0x0 0 !! 38 mux-reg-masks = <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */
40 <0x8 0 !! 39 <0x4088 0x3>, <0x408c 0x3>; /* SERDES0 lane2/3 select */
41 }; 40 };
42 41
43 cpsw0_phy_gmii_sel: phy@4044 { 42 cpsw0_phy_gmii_sel: phy@4044 {
44 compatible = "ti,j7200 43 compatible = "ti,j7200-cpsw5g-phy-gmii-sel";
45 ti,qsgmii-main-ports = 44 ti,qsgmii-main-ports = <1>;
46 reg = <0x4044 0x10>; 45 reg = <0x4044 0x10>;
47 #phy-cells = <1>; 46 #phy-cells = <1>;
48 }; 47 };
49 48
50 usb_serdes_mux: mux-controller 49 usb_serdes_mux: mux-controller@4000 {
51 compatible = "reg-mux" !! 50 compatible = "mmio-mux";
52 reg = <0x4000 0x4>; <<
53 #mux-control-cells = < 51 #mux-control-cells = <1>;
54 mux-reg-masks = <0x0 0 !! 52 mux-reg-masks = <0x4000 0x8000000>; /* USB0 to SERDES0 lane 1/3 mux */
55 }; 53 };
56 }; 54 };
57 55
58 gic500: interrupt-controller@1800000 { 56 gic500: interrupt-controller@1800000 {
59 compatible = "arm,gic-v3"; 57 compatible = "arm,gic-v3";
60 #address-cells = <2>; 58 #address-cells = <2>;
61 #size-cells = <2>; 59 #size-cells = <2>;
62 ranges; 60 ranges;
63 #interrupt-cells = <3>; 61 #interrupt-cells = <3>;
64 interrupt-controller; 62 interrupt-controller;
65 reg = <0x00 0x01800000 0x00 0x 63 reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */
66 <0x00 0x01900000 0x00 0x 64 <0x00 0x01900000 0x00 0x100000>, /* GICR */
67 <0x00 0x6f000000 0x00 0x 65 <0x00 0x6f000000 0x00 0x2000>, /* GICC */
68 <0x00 0x6f010000 0x00 0x 66 <0x00 0x6f010000 0x00 0x1000>, /* GICH */
69 <0x00 0x6f020000 0x00 0x 67 <0x00 0x6f020000 0x00 0x2000>; /* GICV */
70 68
71 /* vcpumntirq: virtual CPU int 69 /* vcpumntirq: virtual CPU interface maintenance interrupt */
72 interrupts = <GIC_PPI 9 IRQ_TY 70 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
73 71
74 gic_its: msi-controller@182000 72 gic_its: msi-controller@1820000 {
75 compatible = "arm,gic- 73 compatible = "arm,gic-v3-its";
76 reg = <0x00 0x01820000 74 reg = <0x00 0x01820000 0x00 0x10000>;
77 socionext,synquacer-pr 75 socionext,synquacer-pre-its = <0x1000000 0x400000>;
78 msi-controller; 76 msi-controller;
79 #msi-cells = <1>; 77 #msi-cells = <1>;
80 }; 78 };
81 }; 79 };
82 80
83 main_gpio_intr: interrupt-controller@a 81 main_gpio_intr: interrupt-controller@a00000 {
84 compatible = "ti,sci-intr"; 82 compatible = "ti,sci-intr";
85 reg = <0x00 0x00a00000 0x00 0x 83 reg = <0x00 0x00a00000 0x00 0x800>;
86 ti,intr-trigger-type = <1>; 84 ti,intr-trigger-type = <1>;
87 interrupt-controller; 85 interrupt-controller;
88 interrupt-parent = <&gic500>; 86 interrupt-parent = <&gic500>;
89 #interrupt-cells = <1>; 87 #interrupt-cells = <1>;
90 ti,sci = <&dmsc>; 88 ti,sci = <&dmsc>;
91 ti,sci-dev-id = <131>; 89 ti,sci-dev-id = <131>;
92 ti,interrupt-ranges = <8 392 5 90 ti,interrupt-ranges = <8 392 56>;
93 }; 91 };
94 92
95 main_navss: bus@30000000 { 93 main_navss: bus@30000000 {
96 compatible = "simple-bus"; 94 compatible = "simple-bus";
97 #address-cells = <2>; 95 #address-cells = <2>;
98 #size-cells = <2>; 96 #size-cells = <2>;
99 ranges = <0x00 0x30000000 0x00 97 ranges = <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>;
100 ti,sci-dev-id = <199>; 98 ti,sci-dev-id = <199>;
101 dma-coherent; 99 dma-coherent;
102 dma-ranges; 100 dma-ranges;
103 101
104 main_navss_intr: interrupt-con 102 main_navss_intr: interrupt-controller@310e0000 {
105 compatible = "ti,sci-i 103 compatible = "ti,sci-intr";
106 reg = <0x00 0x310e0000 104 reg = <0x00 0x310e0000 0x00 0x4000>;
107 ti,intr-trigger-type = 105 ti,intr-trigger-type = <4>;
108 interrupt-controller; 106 interrupt-controller;
109 interrupt-parent = <&g 107 interrupt-parent = <&gic500>;
110 #interrupt-cells = <1> 108 #interrupt-cells = <1>;
111 ti,sci = <&dmsc>; 109 ti,sci = <&dmsc>;
112 ti,sci-dev-id = <213>; 110 ti,sci-dev-id = <213>;
113 ti,interrupt-ranges = 111 ti,interrupt-ranges = <0 64 64>,
114 112 <64 448 64>,
115 113 <128 672 64>;
116 }; 114 };
117 115
118 main_udmass_inta: msi-controll 116 main_udmass_inta: msi-controller@33d00000 {
119 compatible = "ti,sci-i 117 compatible = "ti,sci-inta";
120 reg = <0x00 0x33d00000 118 reg = <0x00 0x33d00000 0x00 0x100000>;
121 interrupt-controller; 119 interrupt-controller;
122 #interrupt-cells = <0> 120 #interrupt-cells = <0>;
123 interrupt-parent = <&m 121 interrupt-parent = <&main_navss_intr>;
124 msi-controller; 122 msi-controller;
125 ti,sci = <&dmsc>; 123 ti,sci = <&dmsc>;
126 ti,sci-dev-id = <209>; 124 ti,sci-dev-id = <209>;
127 ti,interrupt-ranges = 125 ti,interrupt-ranges = <0 0 256>;
128 }; 126 };
129 127
130 secure_proxy_main: mailbox@32c 128 secure_proxy_main: mailbox@32c00000 {
131 compatible = "ti,am654 129 compatible = "ti,am654-secure-proxy";
132 #mbox-cells = <1>; 130 #mbox-cells = <1>;
133 reg-names = "target_da 131 reg-names = "target_data", "rt", "scfg";
134 reg = <0x00 0x32c00000 132 reg = <0x00 0x32c00000 0x00 0x100000>,
135 <0x00 0x32400000 133 <0x00 0x32400000 0x00 0x100000>,
136 <0x00 0x32800000 134 <0x00 0x32800000 0x00 0x100000>;
137 interrupt-names = "rx_ 135 interrupt-names = "rx_011";
138 interrupts = <GIC_SPI 136 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
139 }; 137 };
140 138
141 hwspinlock: spinlock@30e00000 139 hwspinlock: spinlock@30e00000 {
142 compatible = "ti,am654 140 compatible = "ti,am654-hwspinlock";
143 reg = <0x00 0x30e00000 141 reg = <0x00 0x30e00000 0x00 0x1000>;
144 #hwlock-cells = <1>; 142 #hwlock-cells = <1>;
145 }; 143 };
146 144
147 mailbox0_cluster0: mailbox@31f 145 mailbox0_cluster0: mailbox@31f80000 {
148 compatible = "ti,am654 146 compatible = "ti,am654-mailbox";
149 reg = <0x00 0x31f80000 147 reg = <0x00 0x31f80000 0x00 0x200>;
150 #mbox-cells = <1>; 148 #mbox-cells = <1>;
151 ti,mbox-num-users = <4 149 ti,mbox-num-users = <4>;
152 ti,mbox-num-fifos = <1 150 ti,mbox-num-fifos = <16>;
153 interrupt-parent = <&m 151 interrupt-parent = <&main_navss_intr>;
154 status = "disabled"; 152 status = "disabled";
155 }; 153 };
156 154
157 mailbox0_cluster1: mailbox@31f 155 mailbox0_cluster1: mailbox@31f81000 {
158 compatible = "ti,am654 156 compatible = "ti,am654-mailbox";
159 reg = <0x00 0x31f81000 157 reg = <0x00 0x31f81000 0x00 0x200>;
160 #mbox-cells = <1>; 158 #mbox-cells = <1>;
161 ti,mbox-num-users = <4 159 ti,mbox-num-users = <4>;
162 ti,mbox-num-fifos = <1 160 ti,mbox-num-fifos = <16>;
163 interrupt-parent = <&m 161 interrupt-parent = <&main_navss_intr>;
164 status = "disabled"; 162 status = "disabled";
165 }; 163 };
166 164
167 mailbox0_cluster2: mailbox@31f 165 mailbox0_cluster2: mailbox@31f82000 {
168 compatible = "ti,am654 166 compatible = "ti,am654-mailbox";
169 reg = <0x00 0x31f82000 167 reg = <0x00 0x31f82000 0x00 0x200>;
170 #mbox-cells = <1>; 168 #mbox-cells = <1>;
171 ti,mbox-num-users = <4 169 ti,mbox-num-users = <4>;
172 ti,mbox-num-fifos = <1 170 ti,mbox-num-fifos = <16>;
173 interrupt-parent = <&m 171 interrupt-parent = <&main_navss_intr>;
174 status = "disabled"; 172 status = "disabled";
175 }; 173 };
176 174
177 mailbox0_cluster3: mailbox@31f 175 mailbox0_cluster3: mailbox@31f83000 {
178 compatible = "ti,am654 176 compatible = "ti,am654-mailbox";
179 reg = <0x00 0x31f83000 177 reg = <0x00 0x31f83000 0x00 0x200>;
180 #mbox-cells = <1>; 178 #mbox-cells = <1>;
181 ti,mbox-num-users = <4 179 ti,mbox-num-users = <4>;
182 ti,mbox-num-fifos = <1 180 ti,mbox-num-fifos = <16>;
183 interrupt-parent = <&m 181 interrupt-parent = <&main_navss_intr>;
184 status = "disabled"; 182 status = "disabled";
185 }; 183 };
186 184
187 mailbox0_cluster4: mailbox@31f 185 mailbox0_cluster4: mailbox@31f84000 {
188 compatible = "ti,am654 186 compatible = "ti,am654-mailbox";
189 reg = <0x00 0x31f84000 187 reg = <0x00 0x31f84000 0x00 0x200>;
190 #mbox-cells = <1>; 188 #mbox-cells = <1>;
191 ti,mbox-num-users = <4 189 ti,mbox-num-users = <4>;
192 ti,mbox-num-fifos = <1 190 ti,mbox-num-fifos = <16>;
193 interrupt-parent = <&m 191 interrupt-parent = <&main_navss_intr>;
194 status = "disabled"; 192 status = "disabled";
195 }; 193 };
196 194
197 mailbox0_cluster5: mailbox@31f 195 mailbox0_cluster5: mailbox@31f85000 {
198 compatible = "ti,am654 196 compatible = "ti,am654-mailbox";
199 reg = <0x00 0x31f85000 197 reg = <0x00 0x31f85000 0x00 0x200>;
200 #mbox-cells = <1>; 198 #mbox-cells = <1>;
201 ti,mbox-num-users = <4 199 ti,mbox-num-users = <4>;
202 ti,mbox-num-fifos = <1 200 ti,mbox-num-fifos = <16>;
203 interrupt-parent = <&m 201 interrupt-parent = <&main_navss_intr>;
204 status = "disabled"; 202 status = "disabled";
205 }; 203 };
206 204
207 mailbox0_cluster6: mailbox@31f 205 mailbox0_cluster6: mailbox@31f86000 {
208 compatible = "ti,am654 206 compatible = "ti,am654-mailbox";
209 reg = <0x00 0x31f86000 207 reg = <0x00 0x31f86000 0x00 0x200>;
210 #mbox-cells = <1>; 208 #mbox-cells = <1>;
211 ti,mbox-num-users = <4 209 ti,mbox-num-users = <4>;
212 ti,mbox-num-fifos = <1 210 ti,mbox-num-fifos = <16>;
213 interrupt-parent = <&m 211 interrupt-parent = <&main_navss_intr>;
214 status = "disabled"; 212 status = "disabled";
215 }; 213 };
216 214
217 mailbox0_cluster7: mailbox@31f 215 mailbox0_cluster7: mailbox@31f87000 {
218 compatible = "ti,am654 216 compatible = "ti,am654-mailbox";
219 reg = <0x00 0x31f87000 217 reg = <0x00 0x31f87000 0x00 0x200>;
220 #mbox-cells = <1>; 218 #mbox-cells = <1>;
221 ti,mbox-num-users = <4 219 ti,mbox-num-users = <4>;
222 ti,mbox-num-fifos = <1 220 ti,mbox-num-fifos = <16>;
223 interrupt-parent = <&m 221 interrupt-parent = <&main_navss_intr>;
224 status = "disabled"; 222 status = "disabled";
225 }; 223 };
226 224
227 mailbox0_cluster8: mailbox@31f 225 mailbox0_cluster8: mailbox@31f88000 {
228 compatible = "ti,am654 226 compatible = "ti,am654-mailbox";
229 reg = <0x00 0x31f88000 227 reg = <0x00 0x31f88000 0x00 0x200>;
230 #mbox-cells = <1>; 228 #mbox-cells = <1>;
231 ti,mbox-num-users = <4 229 ti,mbox-num-users = <4>;
232 ti,mbox-num-fifos = <1 230 ti,mbox-num-fifos = <16>;
233 interrupt-parent = <&m 231 interrupt-parent = <&main_navss_intr>;
234 status = "disabled"; 232 status = "disabled";
235 }; 233 };
236 234
237 mailbox0_cluster9: mailbox@31f 235 mailbox0_cluster9: mailbox@31f89000 {
238 compatible = "ti,am654 236 compatible = "ti,am654-mailbox";
239 reg = <0x00 0x31f89000 237 reg = <0x00 0x31f89000 0x00 0x200>;
240 #mbox-cells = <1>; 238 #mbox-cells = <1>;
241 ti,mbox-num-users = <4 239 ti,mbox-num-users = <4>;
242 ti,mbox-num-fifos = <1 240 ti,mbox-num-fifos = <16>;
243 interrupt-parent = <&m 241 interrupt-parent = <&main_navss_intr>;
244 status = "disabled"; 242 status = "disabled";
245 }; 243 };
246 244
247 mailbox0_cluster10: mailbox@31 245 mailbox0_cluster10: mailbox@31f8a000 {
248 compatible = "ti,am654 246 compatible = "ti,am654-mailbox";
249 reg = <0x00 0x31f8a000 247 reg = <0x00 0x31f8a000 0x00 0x200>;
250 #mbox-cells = <1>; 248 #mbox-cells = <1>;
251 ti,mbox-num-users = <4 249 ti,mbox-num-users = <4>;
252 ti,mbox-num-fifos = <1 250 ti,mbox-num-fifos = <16>;
253 interrupt-parent = <&m 251 interrupt-parent = <&main_navss_intr>;
254 status = "disabled"; 252 status = "disabled";
255 }; 253 };
256 254
257 mailbox0_cluster11: mailbox@31 255 mailbox0_cluster11: mailbox@31f8b000 {
258 compatible = "ti,am654 256 compatible = "ti,am654-mailbox";
259 reg = <0x00 0x31f8b000 257 reg = <0x00 0x31f8b000 0x00 0x200>;
260 #mbox-cells = <1>; 258 #mbox-cells = <1>;
261 ti,mbox-num-users = <4 259 ti,mbox-num-users = <4>;
262 ti,mbox-num-fifos = <1 260 ti,mbox-num-fifos = <16>;
263 interrupt-parent = <&m 261 interrupt-parent = <&main_navss_intr>;
264 status = "disabled"; 262 status = "disabled";
265 }; 263 };
266 264
267 main_ringacc: ringacc@3c000000 265 main_ringacc: ringacc@3c000000 {
268 compatible = "ti,am654 266 compatible = "ti,am654-navss-ringacc";
269 reg = <0x00 0x3c000000 267 reg = <0x00 0x3c000000 0x00 0x400000>,
270 <0x00 0x38000000 268 <0x00 0x38000000 0x00 0x400000>,
271 <0x00 0x31120000 269 <0x00 0x31120000 0x00 0x100>,
272 <0x00 0x33000000 270 <0x00 0x33000000 0x00 0x40000>,
273 <0x00 0x31080000 271 <0x00 0x31080000 0x00 0x40000>;
274 reg-names = "rt", "fif 272 reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg";
275 ti,num-rings = <1024>; 273 ti,num-rings = <1024>;
276 ti,sci-rm-range-gp-rin 274 ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */
277 ti,sci = <&dmsc>; 275 ti,sci = <&dmsc>;
278 ti,sci-dev-id = <211>; 276 ti,sci-dev-id = <211>;
279 msi-parent = <&main_ud 277 msi-parent = <&main_udmass_inta>;
280 }; 278 };
281 279
282 main_udmap: dma-controller@311 280 main_udmap: dma-controller@31150000 {
283 compatible = "ti,j721e 281 compatible = "ti,j721e-navss-main-udmap";
284 reg = <0x00 0x31150000 282 reg = <0x00 0x31150000 0x00 0x100>,
285 <0x00 0x34000000 283 <0x00 0x34000000 0x00 0x100000>,
286 <0x00 0x35000000 284 <0x00 0x35000000 0x00 0x100000>,
287 <0x00 0x30b00000 285 <0x00 0x30b00000 0x00 0x4000>,
288 <0x00 0x30c00000 286 <0x00 0x30c00000 0x00 0x4000>,
289 <0x00 0x30d00000 287 <0x00 0x30d00000 0x00 0x4000>;
290 reg-names = "gcfg", "r 288 reg-names = "gcfg", "rchanrt", "tchanrt",
291 "tchan", " 289 "tchan", "rchan", "rflow";
292 msi-parent = <&main_ud 290 msi-parent = <&main_udmass_inta>;
293 #dma-cells = <1>; 291 #dma-cells = <1>;
294 292
295 ti,sci = <&dmsc>; 293 ti,sci = <&dmsc>;
296 ti,sci-dev-id = <212>; 294 ti,sci-dev-id = <212>;
297 ti,ringacc = <&main_ri 295 ti,ringacc = <&main_ringacc>;
298 296
299 ti,sci-rm-range-tchan 297 ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */
300 298 <0x0f>, /* TX_HCHAN */
301 299 <0x10>; /* TX_UHCHAN */
302 ti,sci-rm-range-rchan 300 ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */
303 301 <0x0b>, /* RX_HCHAN */
304 302 <0x0c>; /* RX_UHCHAN */
305 ti,sci-rm-range-rflow 303 ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */
306 }; 304 };
307 305
308 cpts@310d0000 { 306 cpts@310d0000 {
309 compatible = "ti,j721e 307 compatible = "ti,j721e-cpts";
310 reg = <0x00 0x310d0000 308 reg = <0x00 0x310d0000 0x00 0x400>;
311 reg-names = "cpts"; 309 reg-names = "cpts";
312 clocks = <&k3_clks 201 310 clocks = <&k3_clks 201 1>;
313 clock-names = "cpts"; 311 clock-names = "cpts";
314 interrupts-extended = 312 interrupts-extended = <&main_navss_intr 391>;
315 interrupt-names = "cpt 313 interrupt-names = "cpts";
316 ti,cpts-periodic-outpu 314 ti,cpts-periodic-outputs = <6>;
317 ti,cpts-ext-ts-inputs 315 ti,cpts-ext-ts-inputs = <8>;
318 }; 316 };
319 }; 317 };
320 318
321 cpsw0: ethernet@c000000 { 319 cpsw0: ethernet@c000000 {
322 compatible = "ti,j7200-cpswxg- 320 compatible = "ti,j7200-cpswxg-nuss";
323 #address-cells = <2>; 321 #address-cells = <2>;
324 #size-cells = <2>; 322 #size-cells = <2>;
325 reg = <0x00 0xc000000 0x00 0x2 323 reg = <0x00 0xc000000 0x00 0x200000>;
326 reg-names = "cpsw_nuss"; 324 reg-names = "cpsw_nuss";
327 ranges = <0x00 0x00 0x00 0xc00 325 ranges = <0x00 0x00 0x00 0xc000000 0x00 0x200000>;
328 clocks = <&k3_clks 19 33>; 326 clocks = <&k3_clks 19 33>;
329 clock-names = "fck"; 327 clock-names = "fck";
330 power-domains = <&k3_pds 19 TI 328 power-domains = <&k3_pds 19 TI_SCI_PD_EXCLUSIVE>;
331 329
332 dmas = <&main_udmap 0xca00>, 330 dmas = <&main_udmap 0xca00>,
333 <&main_udmap 0xca01>, 331 <&main_udmap 0xca01>,
334 <&main_udmap 0xca02>, 332 <&main_udmap 0xca02>,
335 <&main_udmap 0xca03>, 333 <&main_udmap 0xca03>,
336 <&main_udmap 0xca04>, 334 <&main_udmap 0xca04>,
337 <&main_udmap 0xca05>, 335 <&main_udmap 0xca05>,
338 <&main_udmap 0xca06>, 336 <&main_udmap 0xca06>,
339 <&main_udmap 0xca07>, 337 <&main_udmap 0xca07>,
340 <&main_udmap 0x4a00>; 338 <&main_udmap 0x4a00>;
341 dma-names = "tx0", "tx1", "tx2 339 dma-names = "tx0", "tx1", "tx2", "tx3",
342 "tx4", "tx5", "tx6 340 "tx4", "tx5", "tx6", "tx7",
343 "rx"; 341 "rx";
344 342
345 status = "disabled"; 343 status = "disabled";
346 344
347 ethernet-ports { 345 ethernet-ports {
348 #address-cells = <1>; 346 #address-cells = <1>;
349 #size-cells = <0>; 347 #size-cells = <0>;
350 cpsw0_port1: port@1 { 348 cpsw0_port1: port@1 {
351 reg = <1>; 349 reg = <1>;
352 ti,mac-only; 350 ti,mac-only;
353 label = "port1 351 label = "port1";
354 status = "disa 352 status = "disabled";
355 }; 353 };
356 354
357 cpsw0_port2: port@2 { 355 cpsw0_port2: port@2 {
358 reg = <2>; 356 reg = <2>;
359 ti,mac-only; 357 ti,mac-only;
360 label = "port2 358 label = "port2";
361 status = "disa 359 status = "disabled";
362 }; 360 };
363 361
364 cpsw0_port3: port@3 { 362 cpsw0_port3: port@3 {
365 reg = <3>; 363 reg = <3>;
366 ti,mac-only; 364 ti,mac-only;
367 label = "port3 365 label = "port3";
368 status = "disa 366 status = "disabled";
369 }; 367 };
370 368
371 cpsw0_port4: port@4 { 369 cpsw0_port4: port@4 {
372 reg = <4>; 370 reg = <4>;
373 ti,mac-only; 371 ti,mac-only;
374 label = "port4 372 label = "port4";
375 status = "disa 373 status = "disabled";
376 }; 374 };
377 }; 375 };
378 376
379 cpsw5g_mdio: mdio@f00 { 377 cpsw5g_mdio: mdio@f00 {
380 compatible = "ti,cpsw- 378 compatible = "ti,cpsw-mdio","ti,davinci_mdio";
381 reg = <0x00 0xf00 0x00 379 reg = <0x00 0xf00 0x00 0x100>;
382 #address-cells = <1>; 380 #address-cells = <1>;
383 #size-cells = <0>; 381 #size-cells = <0>;
384 clocks = <&k3_clks 19 382 clocks = <&k3_clks 19 33>;
385 clock-names = "fck"; 383 clock-names = "fck";
386 bus_freq = <1000000>; 384 bus_freq = <1000000>;
387 status = "disabled"; 385 status = "disabled";
388 }; 386 };
389 387
390 cpts@3d000 { 388 cpts@3d000 {
391 compatible = "ti,j721e 389 compatible = "ti,j721e-cpts";
392 reg = <0x00 0x3d000 0x 390 reg = <0x00 0x3d000 0x00 0x400>;
393 clocks = <&k3_clks 19 391 clocks = <&k3_clks 19 16>;
394 clock-names = "cpts"; 392 clock-names = "cpts";
395 interrupts-extended = 393 interrupts-extended = <&gic500 GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
396 interrupt-names = "cpt 394 interrupt-names = "cpts";
397 ti,cpts-ext-ts-inputs 395 ti,cpts-ext-ts-inputs = <4>;
398 ti,cpts-periodic-outpu 396 ti,cpts-periodic-outputs = <2>;
399 }; 397 };
400 }; 398 };
401 399
402 /* TIMERIO pad input CTRLMMR_TIMER*_CT 400 /* TIMERIO pad input CTRLMMR_TIMER*_CTRL registers */
403 main_timerio_input: pinctrl@104200 { 401 main_timerio_input: pinctrl@104200 {
404 compatible = "ti,j7200-padconf !! 402 compatible = "pinctrl-single";
405 reg = <0x0 0x104200 0x0 0x50>; 403 reg = <0x0 0x104200 0x0 0x50>;
406 #pinctrl-cells = <1>; 404 #pinctrl-cells = <1>;
407 pinctrl-single,register-width 405 pinctrl-single,register-width = <32>;
408 pinctrl-single,function-mask = 406 pinctrl-single,function-mask = <0x000001ff>;
409 }; 407 };
410 408
411 /* TIMERIO pad output CTCTRLMMR_TIMERI 409 /* TIMERIO pad output CTCTRLMMR_TIMERIO*_CTRL registers */
412 main_timerio_output: pinctrl@104280 { 410 main_timerio_output: pinctrl@104280 {
413 compatible = "ti,j7200-padconf !! 411 compatible = "pinctrl-single";
414 reg = <0x0 0x104280 0x0 0x20>; 412 reg = <0x0 0x104280 0x0 0x20>;
415 #pinctrl-cells = <1>; 413 #pinctrl-cells = <1>;
416 pinctrl-single,register-width 414 pinctrl-single,register-width = <32>;
417 pinctrl-single,function-mask = 415 pinctrl-single,function-mask = <0x0000001f>;
418 }; 416 };
419 417
420 main_pmx0: pinctrl@11c000 { 418 main_pmx0: pinctrl@11c000 {
421 compatible = "ti,j7200-padconf !! 419 compatible = "pinctrl-single";
422 /* Proxy 0 addressing */ 420 /* Proxy 0 addressing */
423 reg = <0x00 0x11c000 0x00 0x10 421 reg = <0x00 0x11c000 0x00 0x10c>;
424 #pinctrl-cells = <1>; 422 #pinctrl-cells = <1>;
425 pinctrl-single,register-width 423 pinctrl-single,register-width = <32>;
426 pinctrl-single,function-mask = 424 pinctrl-single,function-mask = <0xffffffff>;
427 }; 425 };
428 426
429 main_pmx1: pinctrl@11c11c { 427 main_pmx1: pinctrl@11c11c {
430 compatible = "ti,j7200-padconf !! 428 compatible = "pinctrl-single";
431 /* Proxy 0 addressing */ 429 /* Proxy 0 addressing */
432 reg = <0x00 0x11c11c 0x00 0xc> 430 reg = <0x00 0x11c11c 0x00 0xc>;
433 #pinctrl-cells = <1>; 431 #pinctrl-cells = <1>;
434 pinctrl-single,register-width 432 pinctrl-single,register-width = <32>;
435 pinctrl-single,function-mask = 433 pinctrl-single,function-mask = <0xffffffff>;
436 }; 434 };
437 435
438 main_uart0: serial@2800000 { 436 main_uart0: serial@2800000 {
439 compatible = "ti,j721e-uart", 437 compatible = "ti,j721e-uart", "ti,am654-uart";
440 reg = <0x00 0x02800000 0x00 0x 438 reg = <0x00 0x02800000 0x00 0x100>;
441 interrupts = <GIC_SPI 192 IRQ_ 439 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
442 clock-frequency = <48000000>; 440 clock-frequency = <48000000>;
>> 441 current-speed = <115200>;
443 power-domains = <&k3_pds 146 T 442 power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>;
444 clocks = <&k3_clks 146 2>; 443 clocks = <&k3_clks 146 2>;
445 clock-names = "fclk"; 444 clock-names = "fclk";
446 status = "disabled"; 445 status = "disabled";
447 }; 446 };
448 447
449 main_uart1: serial@2810000 { 448 main_uart1: serial@2810000 {
450 compatible = "ti,j721e-uart", 449 compatible = "ti,j721e-uart", "ti,am654-uart";
451 reg = <0x00 0x02810000 0x00 0x 450 reg = <0x00 0x02810000 0x00 0x100>;
452 interrupts = <GIC_SPI 193 IRQ_ 451 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
453 clock-frequency = <48000000>; 452 clock-frequency = <48000000>;
>> 453 current-speed = <115200>;
454 power-domains = <&k3_pds 278 T 454 power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>;
455 clocks = <&k3_clks 278 2>; 455 clocks = <&k3_clks 278 2>;
456 clock-names = "fclk"; 456 clock-names = "fclk";
457 status = "disabled"; 457 status = "disabled";
458 }; 458 };
459 459
460 main_uart2: serial@2820000 { 460 main_uart2: serial@2820000 {
461 compatible = "ti,j721e-uart", 461 compatible = "ti,j721e-uart", "ti,am654-uart";
462 reg = <0x00 0x02820000 0x00 0x 462 reg = <0x00 0x02820000 0x00 0x100>;
463 interrupts = <GIC_SPI 194 IRQ_ 463 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
464 clock-frequency = <48000000>; 464 clock-frequency = <48000000>;
>> 465 current-speed = <115200>;
465 power-domains = <&k3_pds 279 T 466 power-domains = <&k3_pds 279 TI_SCI_PD_EXCLUSIVE>;
466 clocks = <&k3_clks 279 2>; 467 clocks = <&k3_clks 279 2>;
467 clock-names = "fclk"; 468 clock-names = "fclk";
468 status = "disabled"; 469 status = "disabled";
469 }; 470 };
470 471
471 main_uart3: serial@2830000 { 472 main_uart3: serial@2830000 {
472 compatible = "ti,j721e-uart", 473 compatible = "ti,j721e-uart", "ti,am654-uart";
473 reg = <0x00 0x02830000 0x00 0x 474 reg = <0x00 0x02830000 0x00 0x100>;
474 interrupts = <GIC_SPI 195 IRQ_ 475 interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>;
475 clock-frequency = <48000000>; 476 clock-frequency = <48000000>;
>> 477 current-speed = <115200>;
476 power-domains = <&k3_pds 280 T 478 power-domains = <&k3_pds 280 TI_SCI_PD_EXCLUSIVE>;
477 clocks = <&k3_clks 280 2>; 479 clocks = <&k3_clks 280 2>;
478 clock-names = "fclk"; 480 clock-names = "fclk";
479 status = "disabled"; 481 status = "disabled";
480 }; 482 };
481 483
482 main_uart4: serial@2840000 { 484 main_uart4: serial@2840000 {
483 compatible = "ti,j721e-uart", 485 compatible = "ti,j721e-uart", "ti,am654-uart";
484 reg = <0x00 0x02840000 0x00 0x 486 reg = <0x00 0x02840000 0x00 0x100>;
485 interrupts = <GIC_SPI 196 IRQ_ 487 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;
486 clock-frequency = <48000000>; 488 clock-frequency = <48000000>;
>> 489 current-speed = <115200>;
487 power-domains = <&k3_pds 281 T 490 power-domains = <&k3_pds 281 TI_SCI_PD_EXCLUSIVE>;
488 clocks = <&k3_clks 281 2>; 491 clocks = <&k3_clks 281 2>;
489 clock-names = "fclk"; 492 clock-names = "fclk";
490 status = "disabled"; 493 status = "disabled";
491 }; 494 };
492 495
493 main_uart5: serial@2850000 { 496 main_uart5: serial@2850000 {
494 compatible = "ti,j721e-uart", 497 compatible = "ti,j721e-uart", "ti,am654-uart";
495 reg = <0x00 0x02850000 0x00 0x 498 reg = <0x00 0x02850000 0x00 0x100>;
496 interrupts = <GIC_SPI 197 IRQ_ 499 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
497 clock-frequency = <48000000>; 500 clock-frequency = <48000000>;
>> 501 current-speed = <115200>;
498 power-domains = <&k3_pds 282 T 502 power-domains = <&k3_pds 282 TI_SCI_PD_EXCLUSIVE>;
499 clocks = <&k3_clks 282 2>; 503 clocks = <&k3_clks 282 2>;
500 clock-names = "fclk"; 504 clock-names = "fclk";
501 status = "disabled"; 505 status = "disabled";
502 }; 506 };
503 507
504 main_uart6: serial@2860000 { 508 main_uart6: serial@2860000 {
505 compatible = "ti,j721e-uart", 509 compatible = "ti,j721e-uart", "ti,am654-uart";
506 reg = <0x00 0x02860000 0x00 0x 510 reg = <0x00 0x02860000 0x00 0x100>;
507 interrupts = <GIC_SPI 198 IRQ_ 511 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>;
508 clock-frequency = <48000000>; 512 clock-frequency = <48000000>;
>> 513 current-speed = <115200>;
509 power-domains = <&k3_pds 283 T 514 power-domains = <&k3_pds 283 TI_SCI_PD_EXCLUSIVE>;
510 clocks = <&k3_clks 283 2>; 515 clocks = <&k3_clks 283 2>;
511 clock-names = "fclk"; 516 clock-names = "fclk";
512 status = "disabled"; 517 status = "disabled";
513 }; 518 };
514 519
515 main_uart7: serial@2870000 { 520 main_uart7: serial@2870000 {
516 compatible = "ti,j721e-uart", 521 compatible = "ti,j721e-uart", "ti,am654-uart";
517 reg = <0x00 0x02870000 0x00 0x 522 reg = <0x00 0x02870000 0x00 0x100>;
518 interrupts = <GIC_SPI 199 IRQ_ 523 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
519 clock-frequency = <48000000>; 524 clock-frequency = <48000000>;
>> 525 current-speed = <115200>;
520 power-domains = <&k3_pds 284 T 526 power-domains = <&k3_pds 284 TI_SCI_PD_EXCLUSIVE>;
521 clocks = <&k3_clks 284 2>; 527 clocks = <&k3_clks 284 2>;
522 clock-names = "fclk"; 528 clock-names = "fclk";
523 status = "disabled"; 529 status = "disabled";
524 }; 530 };
525 531
526 main_uart8: serial@2880000 { 532 main_uart8: serial@2880000 {
527 compatible = "ti,j721e-uart", 533 compatible = "ti,j721e-uart", "ti,am654-uart";
528 reg = <0x00 0x02880000 0x00 0x 534 reg = <0x00 0x02880000 0x00 0x100>;
529 interrupts = <GIC_SPI 248 IRQ_ 535 interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>;
530 clock-frequency = <48000000>; 536 clock-frequency = <48000000>;
>> 537 current-speed = <115200>;
531 power-domains = <&k3_pds 285 T 538 power-domains = <&k3_pds 285 TI_SCI_PD_EXCLUSIVE>;
532 clocks = <&k3_clks 285 2>; 539 clocks = <&k3_clks 285 2>;
533 clock-names = "fclk"; 540 clock-names = "fclk";
534 status = "disabled"; 541 status = "disabled";
535 }; 542 };
536 543
537 main_uart9: serial@2890000 { 544 main_uart9: serial@2890000 {
538 compatible = "ti,j721e-uart", 545 compatible = "ti,j721e-uart", "ti,am654-uart";
539 reg = <0x00 0x02890000 0x00 0x 546 reg = <0x00 0x02890000 0x00 0x100>;
540 interrupts = <GIC_SPI 249 IRQ_ 547 interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>;
541 clock-frequency = <48000000>; 548 clock-frequency = <48000000>;
>> 549 current-speed = <115200>;
542 power-domains = <&k3_pds 286 T 550 power-domains = <&k3_pds 286 TI_SCI_PD_EXCLUSIVE>;
543 clocks = <&k3_clks 286 2>; 551 clocks = <&k3_clks 286 2>;
544 clock-names = "fclk"; 552 clock-names = "fclk";
545 status = "disabled"; 553 status = "disabled";
546 }; 554 };
547 555
548 main_i2c0: i2c@2000000 { 556 main_i2c0: i2c@2000000 {
549 compatible = "ti,j721e-i2c", " 557 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
550 reg = <0x00 0x2000000 0x00 0x1 558 reg = <0x00 0x2000000 0x00 0x100>;
551 interrupts = <GIC_SPI 200 IRQ_ 559 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>;
552 #address-cells = <1>; 560 #address-cells = <1>;
553 #size-cells = <0>; 561 #size-cells = <0>;
554 clock-names = "fck"; 562 clock-names = "fck";
555 clocks = <&k3_clks 187 1>; 563 clocks = <&k3_clks 187 1>;
556 power-domains = <&k3_pds 187 T 564 power-domains = <&k3_pds 187 TI_SCI_PD_SHARED>;
557 status = "disabled"; 565 status = "disabled";
558 }; 566 };
559 567
560 main_i2c1: i2c@2010000 { 568 main_i2c1: i2c@2010000 {
561 compatible = "ti,j721e-i2c", " 569 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
562 reg = <0x00 0x2010000 0x00 0x1 570 reg = <0x00 0x2010000 0x00 0x100>;
563 interrupts = <GIC_SPI 201 IRQ_ 571 interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>;
564 #address-cells = <1>; 572 #address-cells = <1>;
565 #size-cells = <0>; 573 #size-cells = <0>;
566 clock-names = "fck"; 574 clock-names = "fck";
567 clocks = <&k3_clks 188 1>; 575 clocks = <&k3_clks 188 1>;
568 power-domains = <&k3_pds 188 T 576 power-domains = <&k3_pds 188 TI_SCI_PD_EXCLUSIVE>;
569 status = "disabled"; 577 status = "disabled";
570 }; 578 };
571 579
572 main_i2c2: i2c@2020000 { 580 main_i2c2: i2c@2020000 {
573 compatible = "ti,j721e-i2c", " 581 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
574 reg = <0x00 0x2020000 0x00 0x1 582 reg = <0x00 0x2020000 0x00 0x100>;
575 interrupts = <GIC_SPI 202 IRQ_ 583 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
576 #address-cells = <1>; 584 #address-cells = <1>;
577 #size-cells = <0>; 585 #size-cells = <0>;
578 clock-names = "fck"; 586 clock-names = "fck";
579 clocks = <&k3_clks 189 1>; 587 clocks = <&k3_clks 189 1>;
580 power-domains = <&k3_pds 189 T 588 power-domains = <&k3_pds 189 TI_SCI_PD_EXCLUSIVE>;
581 status = "disabled"; 589 status = "disabled";
582 }; 590 };
583 591
584 main_i2c3: i2c@2030000 { 592 main_i2c3: i2c@2030000 {
585 compatible = "ti,j721e-i2c", " 593 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
586 reg = <0x00 0x2030000 0x00 0x1 594 reg = <0x00 0x2030000 0x00 0x100>;
587 interrupts = <GIC_SPI 203 IRQ_ 595 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>;
588 #address-cells = <1>; 596 #address-cells = <1>;
589 #size-cells = <0>; 597 #size-cells = <0>;
590 clock-names = "fck"; 598 clock-names = "fck";
591 clocks = <&k3_clks 190 1>; 599 clocks = <&k3_clks 190 1>;
592 power-domains = <&k3_pds 190 T 600 power-domains = <&k3_pds 190 TI_SCI_PD_EXCLUSIVE>;
593 status = "disabled"; 601 status = "disabled";
594 }; 602 };
595 603
596 main_i2c4: i2c@2040000 { 604 main_i2c4: i2c@2040000 {
597 compatible = "ti,j721e-i2c", " 605 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
598 reg = <0x00 0x2040000 0x00 0x1 606 reg = <0x00 0x2040000 0x00 0x100>;
599 interrupts = <GIC_SPI 204 IRQ_ 607 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>;
600 #address-cells = <1>; 608 #address-cells = <1>;
601 #size-cells = <0>; 609 #size-cells = <0>;
602 clock-names = "fck"; 610 clock-names = "fck";
603 clocks = <&k3_clks 191 1>; 611 clocks = <&k3_clks 191 1>;
604 power-domains = <&k3_pds 191 T 612 power-domains = <&k3_pds 191 TI_SCI_PD_EXCLUSIVE>;
605 status = "disabled"; 613 status = "disabled";
606 }; 614 };
607 615
608 main_i2c5: i2c@2050000 { 616 main_i2c5: i2c@2050000 {
609 compatible = "ti,j721e-i2c", " 617 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
610 reg = <0x00 0x2050000 0x00 0x1 618 reg = <0x00 0x2050000 0x00 0x100>;
611 interrupts = <GIC_SPI 205 IRQ_ 619 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
612 #address-cells = <1>; 620 #address-cells = <1>;
613 #size-cells = <0>; 621 #size-cells = <0>;
614 clock-names = "fck"; 622 clock-names = "fck";
615 clocks = <&k3_clks 192 1>; 623 clocks = <&k3_clks 192 1>;
616 power-domains = <&k3_pds 192 T 624 power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>;
617 status = "disabled"; 625 status = "disabled";
618 }; 626 };
619 627
620 main_i2c6: i2c@2060000 { 628 main_i2c6: i2c@2060000 {
621 compatible = "ti,j721e-i2c", " 629 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
622 reg = <0x00 0x2060000 0x00 0x1 630 reg = <0x00 0x2060000 0x00 0x100>;
623 interrupts = <GIC_SPI 206 IRQ_ 631 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
624 #address-cells = <1>; 632 #address-cells = <1>;
625 #size-cells = <0>; 633 #size-cells = <0>;
626 clock-names = "fck"; 634 clock-names = "fck";
627 clocks = <&k3_clks 193 1>; 635 clocks = <&k3_clks 193 1>;
628 power-domains = <&k3_pds 193 T 636 power-domains = <&k3_pds 193 TI_SCI_PD_EXCLUSIVE>;
629 status = "disabled"; 637 status = "disabled";
630 }; 638 };
631 639
632 main_sdhci0: mmc@4f80000 { 640 main_sdhci0: mmc@4f80000 {
633 compatible = "ti,j7200-sdhci-8 641 compatible = "ti,j7200-sdhci-8bit", "ti,j721e-sdhci-8bit";
634 reg = <0x00 0x04f80000 0x00 0x 642 reg = <0x00 0x04f80000 0x00 0x260>, <0x00 0x4f88000 0x00 0x134>;
635 interrupts = <GIC_SPI 3 IRQ_TY 643 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
636 power-domains = <&k3_pds 91 TI 644 power-domains = <&k3_pds 91 TI_SCI_PD_EXCLUSIVE>;
637 clock-names = "clk_ahb", "clk_ 645 clock-names = "clk_ahb", "clk_xin";
638 clocks = <&k3_clks 91 0>, <&k3 646 clocks = <&k3_clks 91 0>, <&k3_clks 91 3>;
639 ti,otap-del-sel-legacy = <0x0> 647 ti,otap-del-sel-legacy = <0x0>;
640 ti,otap-del-sel-mmc-hs = <0x0> 648 ti,otap-del-sel-mmc-hs = <0x0>;
641 ti,otap-del-sel-ddr52 = <0x6>; 649 ti,otap-del-sel-ddr52 = <0x6>;
642 ti,otap-del-sel-hs200 = <0x8>; 650 ti,otap-del-sel-hs200 = <0x8>;
643 ti,otap-del-sel-hs400 = <0x5>; 651 ti,otap-del-sel-hs400 = <0x5>;
644 ti,itap-del-sel-legacy = <0x10 652 ti,itap-del-sel-legacy = <0x10>;
645 ti,itap-del-sel-mmc-hs = <0xa> 653 ti,itap-del-sel-mmc-hs = <0xa>;
646 ti,itap-del-sel-ddr52 = <0x3>; 654 ti,itap-del-sel-ddr52 = <0x3>;
647 ti,strobe-sel = <0x77>; 655 ti,strobe-sel = <0x77>;
648 ti,clkbuf-sel = <0x7>; 656 ti,clkbuf-sel = <0x7>;
649 ti,trm-icp = <0x8>; 657 ti,trm-icp = <0x8>;
650 bus-width = <8>; 658 bus-width = <8>;
651 mmc-ddr-1_8v; 659 mmc-ddr-1_8v;
652 mmc-hs200-1_8v; 660 mmc-hs200-1_8v;
653 mmc-hs400-1_8v; 661 mmc-hs400-1_8v;
654 dma-coherent; 662 dma-coherent;
655 status = "disabled"; 663 status = "disabled";
656 }; 664 };
657 665
658 main_sdhci1: mmc@4fb0000 { 666 main_sdhci1: mmc@4fb0000 {
659 compatible = "ti,j7200-sdhci-4 667 compatible = "ti,j7200-sdhci-4bit", "ti,j721e-sdhci-4bit";
660 reg = <0x00 0x04fb0000 0x00 0x 668 reg = <0x00 0x04fb0000 0x00 0x260>, <0x00 0x4fb8000 0x00 0x134>;
661 interrupts = <GIC_SPI 4 IRQ_TY 669 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
662 power-domains = <&k3_pds 92 TI 670 power-domains = <&k3_pds 92 TI_SCI_PD_EXCLUSIVE>;
663 clock-names = "clk_ahb", "clk_ 671 clock-names = "clk_ahb", "clk_xin";
664 clocks = <&k3_clks 92 1>, <&k3 672 clocks = <&k3_clks 92 1>, <&k3_clks 92 2>;
665 ti,otap-del-sel-legacy = <0x0> 673 ti,otap-del-sel-legacy = <0x0>;
666 ti,otap-del-sel-sd-hs = <0x0>; 674 ti,otap-del-sel-sd-hs = <0x0>;
667 ti,otap-del-sel-sdr12 = <0xf>; 675 ti,otap-del-sel-sdr12 = <0xf>;
668 ti,otap-del-sel-sdr25 = <0xf>; 676 ti,otap-del-sel-sdr25 = <0xf>;
669 ti,otap-del-sel-sdr50 = <0xc>; 677 ti,otap-del-sel-sdr50 = <0xc>;
670 ti,otap-del-sel-sdr104 = <0x5> 678 ti,otap-del-sel-sdr104 = <0x5>;
671 ti,otap-del-sel-ddr50 = <0xc>; 679 ti,otap-del-sel-ddr50 = <0xc>;
672 ti,itap-del-sel-legacy = <0x0> 680 ti,itap-del-sel-legacy = <0x0>;
673 ti,itap-del-sel-sd-hs = <0x0>; 681 ti,itap-del-sel-sd-hs = <0x0>;
674 ti,itap-del-sel-sdr12 = <0x0>; 682 ti,itap-del-sel-sdr12 = <0x0>;
675 ti,itap-del-sel-sdr25 = <0x0>; 683 ti,itap-del-sel-sdr25 = <0x0>;
676 ti,clkbuf-sel = <0x7>; 684 ti,clkbuf-sel = <0x7>;
677 ti,trm-icp = <0x8>; 685 ti,trm-icp = <0x8>;
678 dma-coherent; 686 dma-coherent;
679 status = "disabled"; 687 status = "disabled";
680 }; 688 };
681 689
682 serdes_wiz0: wiz@5060000 { 690 serdes_wiz0: wiz@5060000 {
683 compatible = "ti,j721e-wiz-10g 691 compatible = "ti,j721e-wiz-10g";
684 #address-cells = <1>; 692 #address-cells = <1>;
685 #size-cells = <1>; 693 #size-cells = <1>;
686 power-domains = <&k3_pds 292 T 694 power-domains = <&k3_pds 292 TI_SCI_PD_EXCLUSIVE>;
687 clocks = <&k3_clks 292 11>, <& 695 clocks = <&k3_clks 292 11>, <&k3_clks 292 85>, <&serdes_refclk>;
688 clock-names = "fck", "core_ref 696 clock-names = "fck", "core_ref_clk", "ext_ref_clk";
689 num-lanes = <4>; 697 num-lanes = <4>;
690 #reset-cells = <1>; 698 #reset-cells = <1>;
691 ranges = <0x5060000 0x0 0x5060 699 ranges = <0x5060000 0x0 0x5060000 0x10000>;
692 700
693 assigned-clocks = <&k3_clks 29 701 assigned-clocks = <&k3_clks 292 85>;
694 assigned-clock-parents = <&k3_ 702 assigned-clock-parents = <&k3_clks 292 89>;
695 703
696 wiz0_pll0_refclk: pll0-refclk 704 wiz0_pll0_refclk: pll0-refclk {
697 clocks = <&k3_clks 292 705 clocks = <&k3_clks 292 85>, <&serdes_refclk>;
698 clock-output-names = " 706 clock-output-names = "wiz0_pll0_refclk";
699 #clock-cells = <0>; 707 #clock-cells = <0>;
700 assigned-clocks = <&wi 708 assigned-clocks = <&wiz0_pll0_refclk>;
701 assigned-clock-parents 709 assigned-clock-parents = <&k3_clks 292 85>;
702 }; 710 };
703 711
704 wiz0_pll1_refclk: pll1-refclk 712 wiz0_pll1_refclk: pll1-refclk {
705 clocks = <&k3_clks 292 713 clocks = <&k3_clks 292 85>, <&serdes_refclk>;
706 clock-output-names = " 714 clock-output-names = "wiz0_pll1_refclk";
707 #clock-cells = <0>; 715 #clock-cells = <0>;
708 assigned-clocks = <&wi 716 assigned-clocks = <&wiz0_pll1_refclk>;
709 assigned-clock-parents 717 assigned-clock-parents = <&k3_clks 292 85>;
710 }; 718 };
711 719
712 wiz0_refclk_dig: refclk-dig { 720 wiz0_refclk_dig: refclk-dig {
713 clocks = <&k3_clks 292 721 clocks = <&k3_clks 292 85>, <&serdes_refclk>;
714 clock-output-names = " 722 clock-output-names = "wiz0_refclk_dig";
715 #clock-cells = <0>; 723 #clock-cells = <0>;
716 assigned-clocks = <&wi 724 assigned-clocks = <&wiz0_refclk_dig>;
717 assigned-clock-parents 725 assigned-clock-parents = <&k3_clks 292 85>;
718 }; 726 };
719 727
720 wiz0_cmn_refclk_dig_div: cmn-r 728 wiz0_cmn_refclk_dig_div: cmn-refclk-dig-div {
721 clocks = <&wiz0_refclk 729 clocks = <&wiz0_refclk_dig>;
722 #clock-cells = <0>; 730 #clock-cells = <0>;
723 }; 731 };
724 732
725 serdes0: serdes@5060000 { 733 serdes0: serdes@5060000 {
726 compatible = "ti,j721e 734 compatible = "ti,j721e-serdes-10g";
727 reg = <0x05060000 0x00 735 reg = <0x05060000 0x00010000>;
728 reg-names = "torrent_p 736 reg-names = "torrent_phy";
729 resets = <&serdes_wiz0 737 resets = <&serdes_wiz0 0>;
730 reset-names = "torrent 738 reset-names = "torrent_reset";
731 clocks = <&wiz0_pll0_r 739 clocks = <&wiz0_pll0_refclk>;
732 clock-names = "refclk" 740 clock-names = "refclk";
733 #address-cells = <1>; 741 #address-cells = <1>;
734 #size-cells = <0>; 742 #size-cells = <0>;
735 }; 743 };
736 }; 744 };
737 745
738 pcie1_rc: pcie@2910000 { 746 pcie1_rc: pcie@2910000 {
739 compatible = "ti,j7200-pcie-ho 747 compatible = "ti,j7200-pcie-host", "ti,j721e-pcie-host";
740 reg = <0x00 0x02910000 0x00 0x 748 reg = <0x00 0x02910000 0x00 0x1000>,
741 <0x00 0x02917000 0x00 0x 749 <0x00 0x02917000 0x00 0x400>,
742 <0x00 0x0d800000 0x00 0x 750 <0x00 0x0d800000 0x00 0x00800000>,
743 <0x00 0x18000000 0x00 0x 751 <0x00 0x18000000 0x00 0x00001000>;
744 reg-names = "intd_cfg", "user_ 752 reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
745 interrupt-names = "link_state" 753 interrupt-names = "link_state";
746 interrupts = <GIC_SPI 330 IRQ_ 754 interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>;
747 device_type = "pci"; 755 device_type = "pci";
748 ti,syscon-pcie-ctrl = <&scm_co 756 ti,syscon-pcie-ctrl = <&scm_conf 0x4074>;
749 max-link-speed = <3>; 757 max-link-speed = <3>;
750 num-lanes = <4>; 758 num-lanes = <4>;
751 power-domains = <&k3_pds 240 T 759 power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>;
752 clocks = <&k3_clks 240 6>; 760 clocks = <&k3_clks 240 6>;
753 clock-names = "fck"; 761 clock-names = "fck";
754 #address-cells = <3>; 762 #address-cells = <3>;
755 #size-cells = <2>; 763 #size-cells = <2>;
756 bus-range = <0x0 0xff>; 764 bus-range = <0x0 0xff>;
757 cdns,no-bar-match-nbits = <64> 765 cdns,no-bar-match-nbits = <64>;
758 vendor-id = <0x104c>; 766 vendor-id = <0x104c>;
759 device-id = <0xb00f>; 767 device-id = <0xb00f>;
760 msi-map = <0x0 &gic_its 0x0 0x 768 msi-map = <0x0 &gic_its 0x0 0x10000>;
761 dma-coherent; 769 dma-coherent;
762 ranges = <0x01000000 0x0 0x180 770 ranges = <0x01000000 0x0 0x18001000 0x00 0x18001000 0x0 0x0010000>,
763 <0x02000000 0x0 0x180 771 <0x02000000 0x0 0x18011000 0x00 0x18011000 0x0 0x7fef000>;
764 dma-ranges = <0x02000000 0x0 0 772 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
765 status = "disabled"; !! 773 };
>> 774
>> 775 pcie1_ep: pcie-ep@2910000 {
>> 776 compatible = "ti,j7200-pcie-ep", "ti,j721e-pcie-ep";
>> 777 reg = <0x00 0x02910000 0x00 0x1000>,
>> 778 <0x00 0x02917000 0x00 0x400>,
>> 779 <0x00 0x0d800000 0x00 0x00800000>,
>> 780 <0x00 0x18000000 0x00 0x08000000>;
>> 781 reg-names = "intd_cfg", "user_cfg", "reg", "mem";
>> 782 interrupt-names = "link_state";
>> 783 interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>;
>> 784 ti,syscon-pcie-ctrl = <&scm_conf 0x4074>;
>> 785 max-link-speed = <3>;
>> 786 num-lanes = <4>;
>> 787 power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>;
>> 788 clocks = <&k3_clks 240 6>;
>> 789 clock-names = "fck";
>> 790 max-functions = /bits/ 8 <6>;
>> 791 max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>;
>> 792 dma-coherent;
766 }; 793 };
767 794
768 usbss0: cdns-usb@4104000 { 795 usbss0: cdns-usb@4104000 {
769 compatible = "ti,j721e-usb"; 796 compatible = "ti,j721e-usb";
770 reg = <0x00 0x4104000 0x00 0x1 797 reg = <0x00 0x4104000 0x00 0x100>;
771 dma-coherent; 798 dma-coherent;
772 power-domains = <&k3_pds 288 T 799 power-domains = <&k3_pds 288 TI_SCI_PD_EXCLUSIVE>;
773 clocks = <&k3_clks 288 12>, <& 800 clocks = <&k3_clks 288 12>, <&k3_clks 288 3>;
774 clock-names = "ref", "lpm"; 801 clock-names = "ref", "lpm";
775 assigned-clocks = <&k3_clks 28 802 assigned-clocks = <&k3_clks 288 12>; /* USB2_REFCLK */
776 assigned-clock-parents = <&k3_ 803 assigned-clock-parents = <&k3_clks 288 13>; /* HFOSC0 */
777 #address-cells = <2>; 804 #address-cells = <2>;
778 #size-cells = <2>; 805 #size-cells = <2>;
779 ranges; 806 ranges;
780 807
781 usb0: usb@6000000 { 808 usb0: usb@6000000 {
782 compatible = "cdns,usb 809 compatible = "cdns,usb3";
783 reg = <0x00 0x6000000 810 reg = <0x00 0x6000000 0x00 0x10000>,
784 <0x00 0x6010000 811 <0x00 0x6010000 0x00 0x10000>,
785 <0x00 0x6020000 812 <0x00 0x6020000 0x00 0x10000>;
786 reg-names = "otg", "xh 813 reg-names = "otg", "xhci", "dev";
787 interrupts = <GIC_SPI 814 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */
788 <GIC_SPI 815 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, /* irq.6 */
789 <GIC_SPI 816 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; /* otgirq.0 */
790 interrupt-names = "hos 817 interrupt-names = "host",
791 "per 818 "peripheral",
792 "otg 819 "otg";
793 maximum-speed = "super 820 maximum-speed = "super-speed";
794 dr_mode = "otg"; 821 dr_mode = "otg";
795 cdns,phyrst-a-enable; 822 cdns,phyrst-a-enable;
796 }; 823 };
797 }; 824 };
798 825
799 main_gpio0: gpio@600000 { 826 main_gpio0: gpio@600000 {
800 compatible = "ti,j721e-gpio", 827 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
801 reg = <0x00 0x00600000 0x00 0x 828 reg = <0x00 0x00600000 0x00 0x100>;
802 gpio-controller; 829 gpio-controller;
803 #gpio-cells = <2>; 830 #gpio-cells = <2>;
804 interrupt-parent = <&main_gpio 831 interrupt-parent = <&main_gpio_intr>;
805 interrupts = <145>, <146>, <14 832 interrupts = <145>, <146>, <147>, <148>,
806 <149>; 833 <149>;
807 interrupt-controller; 834 interrupt-controller;
808 #interrupt-cells = <2>; 835 #interrupt-cells = <2>;
809 ti,ngpio = <69>; 836 ti,ngpio = <69>;
810 ti,davinci-gpio-unbanked = <0> 837 ti,davinci-gpio-unbanked = <0>;
811 power-domains = <&k3_pds 105 T 838 power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>;
812 clocks = <&k3_clks 105 0>; 839 clocks = <&k3_clks 105 0>;
813 clock-names = "gpio"; 840 clock-names = "gpio";
814 status = "disabled"; 841 status = "disabled";
815 }; 842 };
816 843
817 main_gpio2: gpio@610000 { 844 main_gpio2: gpio@610000 {
818 compatible = "ti,j721e-gpio", 845 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
819 reg = <0x00 0x00610000 0x00 0x 846 reg = <0x00 0x00610000 0x00 0x100>;
820 gpio-controller; 847 gpio-controller;
821 #gpio-cells = <2>; 848 #gpio-cells = <2>;
822 interrupt-parent = <&main_gpio 849 interrupt-parent = <&main_gpio_intr>;
823 interrupts = <154>, <155>, <15 850 interrupts = <154>, <155>, <156>, <157>,
824 <158>; 851 <158>;
825 interrupt-controller; 852 interrupt-controller;
826 #interrupt-cells = <2>; 853 #interrupt-cells = <2>;
827 ti,ngpio = <69>; 854 ti,ngpio = <69>;
828 ti,davinci-gpio-unbanked = <0> 855 ti,davinci-gpio-unbanked = <0>;
829 power-domains = <&k3_pds 107 T 856 power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>;
830 clocks = <&k3_clks 107 0>; 857 clocks = <&k3_clks 107 0>;
831 clock-names = "gpio"; 858 clock-names = "gpio";
832 status = "disabled"; 859 status = "disabled";
833 }; 860 };
834 861
835 main_gpio4: gpio@620000 { 862 main_gpio4: gpio@620000 {
836 compatible = "ti,j721e-gpio", 863 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
837 reg = <0x00 0x00620000 0x00 0x 864 reg = <0x00 0x00620000 0x00 0x100>;
838 gpio-controller; 865 gpio-controller;
839 #gpio-cells = <2>; 866 #gpio-cells = <2>;
840 interrupt-parent = <&main_gpio 867 interrupt-parent = <&main_gpio_intr>;
841 interrupts = <163>, <164>, <16 868 interrupts = <163>, <164>, <165>, <166>,
842 <167>; 869 <167>;
843 interrupt-controller; 870 interrupt-controller;
844 #interrupt-cells = <2>; 871 #interrupt-cells = <2>;
845 ti,ngpio = <69>; 872 ti,ngpio = <69>;
846 ti,davinci-gpio-unbanked = <0> 873 ti,davinci-gpio-unbanked = <0>;
847 power-domains = <&k3_pds 109 T 874 power-domains = <&k3_pds 109 TI_SCI_PD_EXCLUSIVE>;
848 clocks = <&k3_clks 109 0>; 875 clocks = <&k3_clks 109 0>;
849 clock-names = "gpio"; 876 clock-names = "gpio";
850 status = "disabled"; 877 status = "disabled";
851 }; 878 };
852 879
853 main_gpio6: gpio@630000 { 880 main_gpio6: gpio@630000 {
854 compatible = "ti,j721e-gpio", 881 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
855 reg = <0x00 0x00630000 0x00 0x 882 reg = <0x00 0x00630000 0x00 0x100>;
856 gpio-controller; 883 gpio-controller;
857 #gpio-cells = <2>; 884 #gpio-cells = <2>;
858 interrupt-parent = <&main_gpio 885 interrupt-parent = <&main_gpio_intr>;
859 interrupts = <172>, <173>, <17 886 interrupts = <172>, <173>, <174>, <175>,
860 <176>; 887 <176>;
861 interrupt-controller; 888 interrupt-controller;
862 #interrupt-cells = <2>; 889 #interrupt-cells = <2>;
863 ti,ngpio = <69>; 890 ti,ngpio = <69>;
864 ti,davinci-gpio-unbanked = <0> 891 ti,davinci-gpio-unbanked = <0>;
865 power-domains = <&k3_pds 111 T 892 power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>;
866 clocks = <&k3_clks 111 0>; 893 clocks = <&k3_clks 111 0>;
867 clock-names = "gpio"; 894 clock-names = "gpio";
868 status = "disabled"; <<
869 }; <<
870 <<
871 main_mcan0: can@2701000 { <<
872 compatible = "bosch,m_can"; <<
873 reg = <0x00 0x02701000 0x00 0x <<
874 <0x00 0x02708000 0x00 0x <<
875 reg-names = "m_can", "message_ <<
876 power-domains = <&k3_pds 156 T <<
877 clocks = <&k3_clks 156 0>, <&k <<
878 clock-names = "hclk", "cclk"; <<
879 interrupts = <GIC_SPI 124 IRQ_ <<
880 <GIC_SPI 125 IRQ_ <<
881 interrupt-names = "int0", "int <<
882 bosch,mram-cfg = <0x0 128 64 6 <<
883 status = "disabled"; <<
884 }; <<
885 <<
886 main_mcan1: can@2711000 { <<
887 compatible = "bosch,m_can"; <<
888 reg = <0x00 0x02711000 0x00 0x <<
889 <0x00 0x02718000 0x00 0x <<
890 reg-names = "m_can", "message_ <<
891 power-domains = <&k3_pds 158 T <<
892 clocks = <&k3_clks 158 0>, <&k <<
893 clock-names = "hclk", "cclk"; <<
894 interrupts = <GIC_SPI 127 IRQ_ <<
895 <GIC_SPI 128 IRQ_ <<
896 interrupt-names = "int0", "int <<
897 bosch,mram-cfg = <0x0 128 64 6 <<
898 status = "disabled"; <<
899 }; <<
900 <<
901 main_mcan2: can@2721000 { <<
902 compatible = "bosch,m_can"; <<
903 reg = <0x00 0x02721000 0x00 0x <<
904 <0x00 0x02728000 0x00 0x <<
905 reg-names = "m_can", "message_ <<
906 power-domains = <&k3_pds 160 T <<
907 clocks = <&k3_clks 160 0>, <&k <<
908 clock-names = "hclk", "cclk"; <<
909 interrupts = <GIC_SPI 130 IRQ_ <<
910 <GIC_SPI 131 IRQ_ <<
911 interrupt-names = "int0", "int <<
912 bosch,mram-cfg = <0x0 128 64 6 <<
913 status = "disabled"; <<
914 }; <<
915 <<
916 main_mcan3: can@2731000 { <<
917 compatible = "bosch,m_can"; <<
918 reg = <0x00 0x02731000 0x00 0x <<
919 <0x00 0x02738000 0x00 0x <<
920 reg-names = "m_can", "message_ <<
921 power-domains = <&k3_pds 161 T <<
922 clocks = <&k3_clks 161 0>, <&k <<
923 clock-names = "hclk", "cclk"; <<
924 interrupts = <GIC_SPI 133 IRQ_ <<
925 <GIC_SPI 134 IRQ_ <<
926 interrupt-names = "int0", "int <<
927 bosch,mram-cfg = <0x0 128 64 6 <<
928 status = "disabled"; <<
929 }; <<
930 <<
931 main_mcan4: can@2741000 { <<
932 compatible = "bosch,m_can"; <<
933 reg = <0x00 0x02741000 0x00 0x <<
934 <0x00 0x02748000 0x00 0x <<
935 reg-names = "m_can", "message_ <<
936 power-domains = <&k3_pds 162 T <<
937 clocks = <&k3_clks 162 0>, <&k <<
938 clock-names = "hclk", "cclk"; <<
939 interrupts = <GIC_SPI 136 IRQ_ <<
940 <GIC_SPI 137 IRQ_ <<
941 interrupt-names = "int0", "int <<
942 bosch,mram-cfg = <0x0 128 64 6 <<
943 status = "disabled"; <<
944 }; <<
945 <<
946 main_mcan5: can@2751000 { <<
947 compatible = "bosch,m_can"; <<
948 reg = <0x00 0x02751000 0x00 0x <<
949 <0x00 0x02758000 0x00 0x <<
950 reg-names = "m_can", "message_ <<
951 power-domains = <&k3_pds 163 T <<
952 clocks = <&k3_clks 163 0>, <&k <<
953 clock-names = "hclk", "cclk"; <<
954 interrupts = <GIC_SPI 139 IRQ_ <<
955 <GIC_SPI 140 IRQ_ <<
956 interrupt-names = "int0", "int <<
957 bosch,mram-cfg = <0x0 128 64 6 <<
958 status = "disabled"; <<
959 }; <<
960 <<
961 main_mcan6: can@2761000 { <<
962 compatible = "bosch,m_can"; <<
963 reg = <0x00 0x02761000 0x00 0x <<
964 <0x00 0x02768000 0x00 0x <<
965 reg-names = "m_can", "message_ <<
966 power-domains = <&k3_pds 164 T <<
967 clocks = <&k3_clks 164 0>, <&k <<
968 clock-names = "hclk", "cclk"; <<
969 interrupts = <GIC_SPI 142 IRQ_ <<
970 <GIC_SPI 143 IRQ_ <<
971 interrupt-names = "int0", "int <<
972 bosch,mram-cfg = <0x0 128 64 6 <<
973 status = "disabled"; <<
974 }; <<
975 <<
976 main_mcan7: can@2771000 { <<
977 compatible = "bosch,m_can"; <<
978 reg = <0x00 0x02771000 0x00 0x <<
979 <0x00 0x02778000 0x00 0x <<
980 reg-names = "m_can", "message_ <<
981 power-domains = <&k3_pds 165 T <<
982 clocks = <&k3_clks 165 0>, <&k <<
983 clock-names = "hclk", "cclk"; <<
984 interrupts = <GIC_SPI 145 IRQ_ <<
985 <GIC_SPI 146 IRQ_ <<
986 interrupt-names = "int0", "int <<
987 bosch,mram-cfg = <0x0 128 64 6 <<
988 status = "disabled"; <<
989 }; <<
990 <<
991 main_mcan8: can@2781000 { <<
992 compatible = "bosch,m_can"; <<
993 reg = <0x00 0x02781000 0x00 0x <<
994 <0x00 0x02788000 0x00 0x <<
995 reg-names = "m_can", "message_ <<
996 power-domains = <&k3_pds 166 T <<
997 clocks = <&k3_clks 166 0>, <&k <<
998 clock-names = "hclk", "cclk"; <<
999 interrupts = <GIC_SPI 576 IRQ_ <<
1000 <GIC_SPI 577 IRQ <<
1001 interrupt-names = "int0", "in <<
1002 bosch,mram-cfg = <0x0 128 64 <<
1003 status = "disabled"; <<
1004 }; <<
1005 <<
1006 main_mcan9: can@2791000 { <<
1007 compatible = "bosch,m_can"; <<
1008 reg = <0x00 0x02791000 0x00 0 <<
1009 <0x00 0x02798000 0x00 0 <<
1010 reg-names = "m_can", "message <<
1011 power-domains = <&k3_pds 167 <<
1012 clocks = <&k3_clks 167 0>, <& <<
1013 clock-names = "hclk", "cclk"; <<
1014 interrupts = <GIC_SPI 579 IRQ <<
1015 <GIC_SPI 580 IRQ <<
1016 interrupt-names = "int0", "in <<
1017 bosch,mram-cfg = <0x0 128 64 <<
1018 status = "disabled"; <<
1019 }; <<
1020 <<
1021 main_mcan10: can@27a1000 { <<
1022 compatible = "bosch,m_can"; <<
1023 reg = <0x00 0x027a1000 0x00 0 <<
1024 <0x00 0x027a8000 0x00 0 <<
1025 reg-names = "m_can", "message <<
1026 power-domains = <&k3_pds 168 <<
1027 clocks = <&k3_clks 168 0>, <& <<
1028 clock-names = "hclk", "cclk"; <<
1029 interrupts = <GIC_SPI 582 IRQ <<
1030 <GIC_SPI 583 IRQ <<
1031 interrupt-names = "int0", "in <<
1032 bosch,mram-cfg = <0x0 128 64 <<
1033 status = "disabled"; <<
1034 }; <<
1035 <<
1036 main_mcan11: can@27b1000 { <<
1037 compatible = "bosch,m_can"; <<
1038 reg = <0x00 0x027b1000 0x00 0 <<
1039 <0x00 0x027b8000 0x00 0 <<
1040 reg-names = "m_can", "message <<
1041 power-domains = <&k3_pds 169 <<
1042 clocks = <&k3_clks 169 0>, <& <<
1043 clock-names = "hclk", "cclk"; <<
1044 interrupts = <GIC_SPI 585 IRQ <<
1045 <GIC_SPI 586 IRQ <<
1046 interrupt-names = "int0", "in <<
1047 bosch,mram-cfg = <0x0 128 64 <<
1048 status = "disabled"; <<
1049 }; <<
1050 <<
1051 main_mcan12: can@27c1000 { <<
1052 compatible = "bosch,m_can"; <<
1053 reg = <0x00 0x027c1000 0x00 0 <<
1054 <0x00 0x027c8000 0x00 0 <<
1055 reg-names = "m_can", "message <<
1056 power-domains = <&k3_pds 170 <<
1057 clocks = <&k3_clks 170 0>, <& <<
1058 clock-names = "hclk", "cclk"; <<
1059 interrupts = <GIC_SPI 588 IRQ <<
1060 <GIC_SPI 589 IRQ <<
1061 interrupt-names = "int0", "in <<
1062 bosch,mram-cfg = <0x0 128 64 <<
1063 status = "disabled"; <<
1064 }; <<
1065 <<
1066 main_mcan13: can@27d1000 { <<
1067 compatible = "bosch,m_can"; <<
1068 reg = <0x00 0x027d1000 0x00 0 <<
1069 <0x00 0x027d8000 0x00 0 <<
1070 reg-names = "m_can", "message <<
1071 power-domains = <&k3_pds 171 <<
1072 clocks = <&k3_clks 171 0>, <& <<
1073 clock-names = "hclk", "cclk"; <<
1074 interrupts = <GIC_SPI 591 IRQ <<
1075 <GIC_SPI 592 IRQ <<
1076 interrupt-names = "int0", "in <<
1077 bosch,mram-cfg = <0x0 128 64 <<
1078 status = "disabled"; <<
1079 }; <<
1080 <<
1081 main_mcan14: can@2681000 { <<
1082 compatible = "bosch,m_can"; <<
1083 reg = <0x00 0x02681000 0x00 0 <<
1084 <0x00 0x02688000 0x00 0 <<
1085 reg-names = "m_can", "message <<
1086 power-domains = <&k3_pds 150 <<
1087 clocks = <&k3_clks 150 0>, <& <<
1088 clock-names = "hclk", "cclk"; <<
1089 interrupts = <GIC_SPI 594 IRQ <<
1090 <GIC_SPI 595 IRQ <<
1091 interrupt-names = "int0", "in <<
1092 bosch,mram-cfg = <0x0 128 64 <<
1093 status = "disabled"; <<
1094 }; <<
1095 <<
1096 main_mcan15: can@2691000 { <<
1097 compatible = "bosch,m_can"; <<
1098 reg = <0x00 0x02691000 0x00 0 <<
1099 <0x00 0x02698000 0x00 0 <<
1100 reg-names = "m_can", "message <<
1101 power-domains = <&k3_pds 151 <<
1102 clocks = <&k3_clks 151 0>, <& <<
1103 clock-names = "hclk", "cclk"; <<
1104 interrupts = <GIC_SPI 597 IRQ <<
1105 <GIC_SPI 598 IRQ <<
1106 interrupt-names = "int0", "in <<
1107 bosch,mram-cfg = <0x0 128 64 <<
1108 status = "disabled"; <<
1109 }; <<
1110 <<
1111 main_mcan16: can@26a1000 { <<
1112 compatible = "bosch,m_can"; <<
1113 reg = <0x00 0x026a1000 0x00 0 <<
1114 <0x00 0x026a8000 0x00 0 <<
1115 reg-names = "m_can", "message <<
1116 power-domains = <&k3_pds 152 <<
1117 clocks = <&k3_clks 152 0>, <& <<
1118 clock-names = "hclk", "cclk"; <<
1119 interrupts = <GIC_SPI 784 IRQ <<
1120 <GIC_SPI 785 IRQ <<
1121 interrupt-names = "int0", "in <<
1122 bosch,mram-cfg = <0x0 128 64 <<
1123 status = "disabled"; <<
1124 }; <<
1125 <<
1126 main_mcan17: can@26b1000 { <<
1127 compatible = "bosch,m_can"; <<
1128 reg = <0x00 0x026b1000 0x00 0 <<
1129 <0x00 0x026b8000 0x00 0 <<
1130 reg-names = "m_can", "message <<
1131 power-domains = <&k3_pds 153 <<
1132 clocks = <&k3_clks 153 0>, <& <<
1133 clock-names = "hclk", "cclk"; <<
1134 interrupts = <GIC_SPI 787 IRQ <<
1135 <GIC_SPI 788 IRQ <<
1136 interrupt-names = "int0", "in <<
1137 bosch,mram-cfg = <0x0 128 64 <<
1138 status = "disabled"; 895 status = "disabled";
1139 }; 896 };
1140 897
1141 main_spi0: spi@2100000 { 898 main_spi0: spi@2100000 {
1142 compatible = "ti,am654-mcspi" 899 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
1143 reg = <0x00 0x02100000 0x00 0 900 reg = <0x00 0x02100000 0x00 0x400>;
1144 interrupts = <GIC_SPI 184 IRQ 901 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
1145 #address-cells = <1>; 902 #address-cells = <1>;
1146 #size-cells = <0>; 903 #size-cells = <0>;
1147 power-domains = <&k3_pds 266 904 power-domains = <&k3_pds 266 TI_SCI_PD_EXCLUSIVE>;
1148 clocks = <&k3_clks 266 1>; 905 clocks = <&k3_clks 266 1>;
1149 status = "disabled"; 906 status = "disabled";
1150 }; 907 };
1151 908
1152 main_spi1: spi@2110000 { 909 main_spi1: spi@2110000 {
1153 compatible = "ti,am654-mcspi" 910 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
1154 reg = <0x00 0x02110000 0x00 0 911 reg = <0x00 0x02110000 0x00 0x400>;
1155 interrupts = <GIC_SPI 185 IRQ 912 interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
1156 #address-cells = <1>; 913 #address-cells = <1>;
1157 #size-cells = <0>; 914 #size-cells = <0>;
1158 power-domains = <&k3_pds 267 915 power-domains = <&k3_pds 267 TI_SCI_PD_EXCLUSIVE>;
1159 clocks = <&k3_clks 267 1>; 916 clocks = <&k3_clks 267 1>;
1160 status = "disabled"; 917 status = "disabled";
1161 }; 918 };
1162 919
1163 main_spi2: spi@2120000 { 920 main_spi2: spi@2120000 {
1164 compatible = "ti,am654-mcspi" 921 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
1165 reg = <0x00 0x02120000 0x00 0 922 reg = <0x00 0x02120000 0x00 0x400>;
1166 interrupts = <GIC_SPI 186 IRQ 923 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
1167 #address-cells = <1>; 924 #address-cells = <1>;
1168 #size-cells = <0>; 925 #size-cells = <0>;
1169 power-domains = <&k3_pds 268 926 power-domains = <&k3_pds 268 TI_SCI_PD_EXCLUSIVE>;
1170 clocks = <&k3_clks 268 1>; 927 clocks = <&k3_clks 268 1>;
1171 status = "disabled"; 928 status = "disabled";
1172 }; 929 };
1173 930
1174 main_spi3: spi@2130000 { 931 main_spi3: spi@2130000 {
1175 compatible = "ti,am654-mcspi" 932 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
1176 reg = <0x00 0x02130000 0x00 0 933 reg = <0x00 0x02130000 0x00 0x400>;
1177 interrupts = <GIC_SPI 187 IRQ 934 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
1178 #address-cells = <1>; 935 #address-cells = <1>;
1179 #size-cells = <0>; 936 #size-cells = <0>;
1180 power-domains = <&k3_pds 269 937 power-domains = <&k3_pds 269 TI_SCI_PD_EXCLUSIVE>;
1181 clocks = <&k3_clks 269 1>; 938 clocks = <&k3_clks 269 1>;
1182 status = "disabled"; 939 status = "disabled";
1183 }; 940 };
1184 941
1185 main_spi4: spi@2140000 { 942 main_spi4: spi@2140000 {
1186 compatible = "ti,am654-mcspi" 943 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
1187 reg = <0x00 0x02140000 0x00 0 944 reg = <0x00 0x02140000 0x00 0x400>;
1188 interrupts = <GIC_SPI 188 IRQ 945 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
1189 #address-cells = <1>; 946 #address-cells = <1>;
1190 #size-cells = <0>; 947 #size-cells = <0>;
1191 power-domains = <&k3_pds 270 948 power-domains = <&k3_pds 270 TI_SCI_PD_EXCLUSIVE>;
1192 clocks = <&k3_clks 270 1>; 949 clocks = <&k3_clks 270 1>;
1193 status = "disabled"; 950 status = "disabled";
1194 }; 951 };
1195 952
1196 main_spi5: spi@2150000 { 953 main_spi5: spi@2150000 {
1197 compatible = "ti,am654-mcspi" 954 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
1198 reg = <0x00 0x02150000 0x00 0 955 reg = <0x00 0x02150000 0x00 0x400>;
1199 interrupts = <GIC_SPI 189 IRQ 956 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
1200 #address-cells = <1>; 957 #address-cells = <1>;
1201 #size-cells = <0>; 958 #size-cells = <0>;
1202 power-domains = <&k3_pds 271 959 power-domains = <&k3_pds 271 TI_SCI_PD_EXCLUSIVE>;
1203 clocks = <&k3_clks 271 1>; 960 clocks = <&k3_clks 271 1>;
1204 status = "disabled"; 961 status = "disabled";
1205 }; 962 };
1206 963
1207 main_spi6: spi@2160000 { 964 main_spi6: spi@2160000 {
1208 compatible = "ti,am654-mcspi" 965 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
1209 reg = <0x00 0x02160000 0x00 0 966 reg = <0x00 0x02160000 0x00 0x400>;
1210 interrupts = <GIC_SPI 190 IRQ 967 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
1211 #address-cells = <1>; 968 #address-cells = <1>;
1212 #size-cells = <0>; 969 #size-cells = <0>;
1213 power-domains = <&k3_pds 272 970 power-domains = <&k3_pds 272 TI_SCI_PD_EXCLUSIVE>;
1214 clocks = <&k3_clks 272 1>; 971 clocks = <&k3_clks 272 1>;
1215 status = "disabled"; 972 status = "disabled";
1216 }; 973 };
1217 974
1218 main_spi7: spi@2170000 { 975 main_spi7: spi@2170000 {
1219 compatible = "ti,am654-mcspi" 976 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
1220 reg = <0x00 0x02170000 0x00 0 977 reg = <0x00 0x02170000 0x00 0x400>;
1221 interrupts = <GIC_SPI 191 IRQ 978 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
1222 #address-cells = <1>; 979 #address-cells = <1>;
1223 #size-cells = <0>; 980 #size-cells = <0>;
1224 power-domains = <&k3_pds 273 981 power-domains = <&k3_pds 273 TI_SCI_PD_EXCLUSIVE>;
1225 clocks = <&k3_clks 273 1>; 982 clocks = <&k3_clks 273 1>;
1226 status = "disabled"; 983 status = "disabled";
1227 }; 984 };
1228 985
1229 watchdog0: watchdog@2200000 { 986 watchdog0: watchdog@2200000 {
1230 compatible = "ti,j7-rti-wdt"; 987 compatible = "ti,j7-rti-wdt";
1231 reg = <0x0 0x2200000 0x0 0x10 988 reg = <0x0 0x2200000 0x0 0x100>;
1232 clocks = <&k3_clks 252 1>; 989 clocks = <&k3_clks 252 1>;
1233 power-domains = <&k3_pds 252 990 power-domains = <&k3_pds 252 TI_SCI_PD_EXCLUSIVE>;
1234 assigned-clocks = <&k3_clks 2 991 assigned-clocks = <&k3_clks 252 1>;
1235 assigned-clock-parents = <&k3 992 assigned-clock-parents = <&k3_clks 252 5>;
1236 }; 993 };
1237 994
1238 watchdog1: watchdog@2210000 { 995 watchdog1: watchdog@2210000 {
1239 compatible = "ti,j7-rti-wdt"; 996 compatible = "ti,j7-rti-wdt";
1240 reg = <0x0 0x2210000 0x0 0x10 997 reg = <0x0 0x2210000 0x0 0x100>;
1241 clocks = <&k3_clks 253 1>; 998 clocks = <&k3_clks 253 1>;
1242 power-domains = <&k3_pds 253 999 power-domains = <&k3_pds 253 TI_SCI_PD_EXCLUSIVE>;
1243 assigned-clocks = <&k3_clks 2 1000 assigned-clocks = <&k3_clks 253 1>;
1244 assigned-clock-parents = <&k3 1001 assigned-clock-parents = <&k3_clks 253 5>;
1245 }; 1002 };
1246 1003
1247 main_timer0: timer@2400000 { 1004 main_timer0: timer@2400000 {
1248 compatible = "ti,am654-timer" 1005 compatible = "ti,am654-timer";
1249 reg = <0x00 0x2400000 0x00 0x 1006 reg = <0x00 0x2400000 0x00 0x400>;
1250 interrupts = <GIC_SPI 224 IRQ 1007 interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
1251 clocks = <&k3_clks 49 1>; 1008 clocks = <&k3_clks 49 1>;
1252 clock-names = "fck"; 1009 clock-names = "fck";
1253 assigned-clocks = <&k3_clks 4 1010 assigned-clocks = <&k3_clks 49 1>;
1254 assigned-clock-parents = <&k3 1011 assigned-clock-parents = <&k3_clks 49 2>;
1255 power-domains = <&k3_pds 49 T 1012 power-domains = <&k3_pds 49 TI_SCI_PD_EXCLUSIVE>;
1256 ti,timer-pwm; 1013 ti,timer-pwm;
1257 }; 1014 };
1258 1015
1259 main_timer1: timer@2410000 { 1016 main_timer1: timer@2410000 {
1260 compatible = "ti,am654-timer" 1017 compatible = "ti,am654-timer";
1261 reg = <0x00 0x2410000 0x00 0x 1018 reg = <0x00 0x2410000 0x00 0x400>;
1262 interrupts = <GIC_SPI 225 IRQ 1019 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
1263 clocks = <&k3_clks 50 1>; 1020 clocks = <&k3_clks 50 1>;
1264 clock-names = "fck"; 1021 clock-names = "fck";
1265 assigned-clocks = <&k3_clks 5 1022 assigned-clocks = <&k3_clks 50 1>, <&k3_clks 313 0>;
1266 assigned-clock-parents = <&k3 1023 assigned-clock-parents = <&k3_clks 50 2>, <&k3_clks 313 1>;
1267 power-domains = <&k3_pds 50 T 1024 power-domains = <&k3_pds 50 TI_SCI_PD_EXCLUSIVE>;
1268 ti,timer-pwm; 1025 ti,timer-pwm;
1269 }; 1026 };
1270 1027
1271 main_timer2: timer@2420000 { 1028 main_timer2: timer@2420000 {
1272 compatible = "ti,am654-timer" 1029 compatible = "ti,am654-timer";
1273 reg = <0x00 0x2420000 0x00 0x 1030 reg = <0x00 0x2420000 0x00 0x400>;
1274 interrupts = <GIC_SPI 226 IRQ 1031 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
1275 clocks = <&k3_clks 51 1>; 1032 clocks = <&k3_clks 51 1>;
1276 clock-names = "fck"; 1033 clock-names = "fck";
1277 assigned-clocks = <&k3_clks 5 1034 assigned-clocks = <&k3_clks 51 1>;
1278 assigned-clock-parents = <&k3 1035 assigned-clock-parents = <&k3_clks 51 2>;
1279 power-domains = <&k3_pds 49 T 1036 power-domains = <&k3_pds 49 TI_SCI_PD_EXCLUSIVE>;
1280 ti,timer-pwm; 1037 ti,timer-pwm;
1281 }; 1038 };
1282 1039
1283 main_timer3: timer@2430000 { 1040 main_timer3: timer@2430000 {
1284 compatible = "ti,am654-timer" 1041 compatible = "ti,am654-timer";
1285 reg = <0x00 0x2430000 0x00 0x 1042 reg = <0x00 0x2430000 0x00 0x400>;
1286 interrupts = <GIC_SPI 227 IRQ 1043 interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
1287 clocks = <&k3_clks 52 1>; 1044 clocks = <&k3_clks 52 1>;
1288 clock-names = "fck"; 1045 clock-names = "fck";
1289 assigned-clocks = <&k3_clks 5 1046 assigned-clocks = <&k3_clks 52 1>, <&k3_clks 314 0>;
1290 assigned-clock-parents = <&k3 1047 assigned-clock-parents = <&k3_clks 52 2>, <&k3_clks 314 1>;
1291 power-domains = <&k3_pds 52 T 1048 power-domains = <&k3_pds 52 TI_SCI_PD_EXCLUSIVE>;
1292 ti,timer-pwm; 1049 ti,timer-pwm;
1293 }; 1050 };
1294 1051
1295 main_timer4: timer@2440000 { 1052 main_timer4: timer@2440000 {
1296 compatible = "ti,am654-timer" 1053 compatible = "ti,am654-timer";
1297 reg = <0x00 0x2440000 0x00 0x 1054 reg = <0x00 0x2440000 0x00 0x400>;
1298 interrupts = <GIC_SPI 228 IRQ 1055 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>;
1299 clocks = <&k3_clks 53 1>; 1056 clocks = <&k3_clks 53 1>;
1300 clock-names = "fck"; 1057 clock-names = "fck";
1301 assigned-clocks = <&k3_clks 5 1058 assigned-clocks = <&k3_clks 53 1>;
1302 assigned-clock-parents = <&k3 1059 assigned-clock-parents = <&k3_clks 53 2>;
1303 power-domains = <&k3_pds 53 T 1060 power-domains = <&k3_pds 53 TI_SCI_PD_EXCLUSIVE>;
1304 ti,timer-pwm; 1061 ti,timer-pwm;
1305 }; 1062 };
1306 1063
1307 main_timer5: timer@2450000 { 1064 main_timer5: timer@2450000 {
1308 compatible = "ti,am654-timer" 1065 compatible = "ti,am654-timer";
1309 reg = <0x00 0x2450000 0x00 0x 1066 reg = <0x00 0x2450000 0x00 0x400>;
1310 interrupts = <GIC_SPI 229 IRQ 1067 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
1311 clocks = <&k3_clks 54 1>; 1068 clocks = <&k3_clks 54 1>;
1312 clock-names = "fck"; 1069 clock-names = "fck";
1313 assigned-clocks = <&k3_clks 5 1070 assigned-clocks = <&k3_clks 54 1>, <&k3_clks 315 0>;
1314 assigned-clock-parents = <&k3 1071 assigned-clock-parents = <&k3_clks 54 2>, <&k3_clks 315 1>;
1315 power-domains = <&k3_pds 54 T 1072 power-domains = <&k3_pds 54 TI_SCI_PD_EXCLUSIVE>;
1316 ti,timer-pwm; 1073 ti,timer-pwm;
1317 }; 1074 };
1318 1075
1319 main_timer6: timer@2460000 { 1076 main_timer6: timer@2460000 {
1320 compatible = "ti,am654-timer" 1077 compatible = "ti,am654-timer";
1321 reg = <0x00 0x2460000 0x00 0x 1078 reg = <0x00 0x2460000 0x00 0x400>;
1322 interrupts = <GIC_SPI 230 IRQ 1079 interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>;
1323 clocks = <&k3_clks 55 1>; 1080 clocks = <&k3_clks 55 1>;
1324 clock-names = "fck"; 1081 clock-names = "fck";
1325 assigned-clocks = <&k3_clks 5 1082 assigned-clocks = <&k3_clks 55 1>;
1326 assigned-clock-parents = <&k3 1083 assigned-clock-parents = <&k3_clks 55 2>;
1327 power-domains = <&k3_pds 55 T 1084 power-domains = <&k3_pds 55 TI_SCI_PD_EXCLUSIVE>;
1328 ti,timer-pwm; 1085 ti,timer-pwm;
1329 }; 1086 };
1330 1087
1331 main_timer7: timer@2470000 { 1088 main_timer7: timer@2470000 {
1332 compatible = "ti,am654-timer" 1089 compatible = "ti,am654-timer";
1333 reg = <0x00 0x2470000 0x00 0x 1090 reg = <0x00 0x2470000 0x00 0x400>;
1334 interrupts = <GIC_SPI 231 IRQ 1091 interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>;
1335 clocks = <&k3_clks 57 1>; 1092 clocks = <&k3_clks 57 1>;
1336 clock-names = "fck"; 1093 clock-names = "fck";
1337 assigned-clocks = <&k3_clks 5 1094 assigned-clocks = <&k3_clks 57 1>, <&k3_clks 316 0>;
1338 assigned-clock-parents = <&k3 1095 assigned-clock-parents = <&k3_clks 57 2>, <&k3_clks 316 1>;
1339 power-domains = <&k3_pds 57 T 1096 power-domains = <&k3_pds 57 TI_SCI_PD_EXCLUSIVE>;
1340 ti,timer-pwm; 1097 ti,timer-pwm;
1341 }; 1098 };
1342 1099
1343 main_timer8: timer@2480000 { 1100 main_timer8: timer@2480000 {
1344 compatible = "ti,am654-timer" 1101 compatible = "ti,am654-timer";
1345 reg = <0x00 0x2480000 0x00 0x 1102 reg = <0x00 0x2480000 0x00 0x400>;
1346 interrupts = <GIC_SPI 232 IRQ 1103 interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>;
1347 clocks = <&k3_clks 58 1>; 1104 clocks = <&k3_clks 58 1>;
1348 clock-names = "fck"; 1105 clock-names = "fck";
1349 assigned-clocks = <&k3_clks 5 1106 assigned-clocks = <&k3_clks 58 1>;
1350 assigned-clock-parents = <&k3 1107 assigned-clock-parents = <&k3_clks 58 2>;
1351 power-domains = <&k3_pds 58 T 1108 power-domains = <&k3_pds 58 TI_SCI_PD_EXCLUSIVE>;
1352 ti,timer-pwm; 1109 ti,timer-pwm;
1353 }; 1110 };
1354 1111
1355 main_timer9: timer@2490000 { 1112 main_timer9: timer@2490000 {
1356 compatible = "ti,am654-timer" 1113 compatible = "ti,am654-timer";
1357 reg = <0x00 0x2490000 0x00 0x 1114 reg = <0x00 0x2490000 0x00 0x400>;
1358 interrupts = <GIC_SPI 233 IRQ 1115 interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>;
1359 clocks = <&k3_clks 59 1>; 1116 clocks = <&k3_clks 59 1>;
1360 clock-names = "fck"; 1117 clock-names = "fck";
1361 assigned-clocks = <&k3_clks 5 1118 assigned-clocks = <&k3_clks 59 1>, <&k3_clks 317 0>;
1362 assigned-clock-parents = <&k3 1119 assigned-clock-parents = <&k3_clks 59 2>, <&k3_clks 317 1>;
1363 power-domains = <&k3_pds 59 T 1120 power-domains = <&k3_pds 59 TI_SCI_PD_EXCLUSIVE>;
1364 ti,timer-pwm; 1121 ti,timer-pwm;
1365 }; 1122 };
1366 1123
1367 main_timer10: timer@24a0000 { 1124 main_timer10: timer@24a0000 {
1368 compatible = "ti,am654-timer" 1125 compatible = "ti,am654-timer";
1369 reg = <0x00 0x24a0000 0x00 0x 1126 reg = <0x00 0x24a0000 0x00 0x400>;
1370 interrupts = <GIC_SPI 234 IRQ 1127 interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>;
1371 clocks = <&k3_clks 60 1>; 1128 clocks = <&k3_clks 60 1>;
1372 clock-names = "fck"; 1129 clock-names = "fck";
1373 assigned-clocks = <&k3_clks 6 1130 assigned-clocks = <&k3_clks 60 1>;
1374 assigned-clock-parents = <&k3 1131 assigned-clock-parents = <&k3_clks 60 2>;
1375 power-domains = <&k3_pds 60 T 1132 power-domains = <&k3_pds 60 TI_SCI_PD_EXCLUSIVE>;
1376 ti,timer-pwm; 1133 ti,timer-pwm;
1377 }; 1134 };
1378 1135
1379 main_timer11: timer@24b0000 { 1136 main_timer11: timer@24b0000 {
1380 compatible = "ti,am654-timer" 1137 compatible = "ti,am654-timer";
1381 reg = <0x00 0x24b0000 0x00 0x 1138 reg = <0x00 0x24b0000 0x00 0x400>;
1382 interrupts = <GIC_SPI 235 IRQ 1139 interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>;
1383 clocks = <&k3_clks 62 1>; 1140 clocks = <&k3_clks 62 1>;
1384 clock-names = "fck"; 1141 clock-names = "fck";
1385 assigned-clocks = <&k3_clks 6 1142 assigned-clocks = <&k3_clks 62 1>, <&k3_clks 318 0>;
1386 assigned-clock-parents = <&k3 1143 assigned-clock-parents = <&k3_clks 62 2>, <&k3_clks 318 1>;
1387 power-domains = <&k3_pds 62 T 1144 power-domains = <&k3_pds 62 TI_SCI_PD_EXCLUSIVE>;
1388 ti,timer-pwm; 1145 ti,timer-pwm;
1389 }; 1146 };
1390 1147
1391 main_timer12: timer@24c0000 { 1148 main_timer12: timer@24c0000 {
1392 compatible = "ti,am654-timer" 1149 compatible = "ti,am654-timer";
1393 reg = <0x00 0x24c0000 0x00 0x 1150 reg = <0x00 0x24c0000 0x00 0x400>;
1394 interrupts = <GIC_SPI 236 IRQ 1151 interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>;
1395 clocks = <&k3_clks 63 1>; 1152 clocks = <&k3_clks 63 1>;
1396 clock-names = "fck"; 1153 clock-names = "fck";
1397 assigned-clocks = <&k3_clks 6 1154 assigned-clocks = <&k3_clks 63 1>;
1398 assigned-clock-parents = <&k3 1155 assigned-clock-parents = <&k3_clks 63 2>;
1399 power-domains = <&k3_pds 63 T 1156 power-domains = <&k3_pds 63 TI_SCI_PD_EXCLUSIVE>;
1400 ti,timer-pwm; 1157 ti,timer-pwm;
1401 }; 1158 };
1402 1159
1403 main_timer13: timer@24d0000 { 1160 main_timer13: timer@24d0000 {
1404 compatible = "ti,am654-timer" 1161 compatible = "ti,am654-timer";
1405 reg = <0x00 0x24d0000 0x00 0x 1162 reg = <0x00 0x24d0000 0x00 0x400>;
1406 interrupts = <GIC_SPI 237 IRQ 1163 interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>;
1407 clocks = <&k3_clks 64 1>; 1164 clocks = <&k3_clks 64 1>;
1408 clock-names = "fck"; 1165 clock-names = "fck";
1409 assigned-clocks = <&k3_clks 6 1166 assigned-clocks = <&k3_clks 64 1>, <&k3_clks 319 0>;
1410 assigned-clock-parents = <&k3 1167 assigned-clock-parents = <&k3_clks 64 2>, <&k3_clks 319 1>;
1411 power-domains = <&k3_pds 64 T 1168 power-domains = <&k3_pds 64 TI_SCI_PD_EXCLUSIVE>;
1412 ti,timer-pwm; 1169 ti,timer-pwm;
1413 }; 1170 };
1414 1171
1415 main_timer14: timer@24e0000 { 1172 main_timer14: timer@24e0000 {
1416 compatible = "ti,am654-timer" 1173 compatible = "ti,am654-timer";
1417 reg = <0x00 0x24e0000 0x00 0x 1174 reg = <0x00 0x24e0000 0x00 0x400>;
1418 interrupts = <GIC_SPI 238 IRQ 1175 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
1419 clocks = <&k3_clks 65 1>; 1176 clocks = <&k3_clks 65 1>;
1420 clock-names = "fck"; 1177 clock-names = "fck";
1421 assigned-clocks = <&k3_clks 6 1178 assigned-clocks = <&k3_clks 65 1>;
1422 assigned-clock-parents = <&k3 1179 assigned-clock-parents = <&k3_clks 65 2>;
1423 power-domains = <&k3_pds 65 T 1180 power-domains = <&k3_pds 65 TI_SCI_PD_EXCLUSIVE>;
1424 ti,timer-pwm; 1181 ti,timer-pwm;
1425 }; 1182 };
1426 1183
1427 main_timer15: timer@24f0000 { 1184 main_timer15: timer@24f0000 {
1428 compatible = "ti,am654-timer" 1185 compatible = "ti,am654-timer";
1429 reg = <0x00 0x24f0000 0x00 0x 1186 reg = <0x00 0x24f0000 0x00 0x400>;
1430 interrupts = <GIC_SPI 239 IRQ 1187 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
1431 clocks = <&k3_clks 66 1>; 1188 clocks = <&k3_clks 66 1>;
1432 clock-names = "fck"; 1189 clock-names = "fck";
1433 assigned-clocks = <&k3_clks 6 1190 assigned-clocks = <&k3_clks 66 1>, <&k3_clks 320 0>;
1434 assigned-clock-parents = <&k3 1191 assigned-clock-parents = <&k3_clks 66 2>, <&k3_clks 320 1>;
1435 power-domains = <&k3_pds 66 T 1192 power-domains = <&k3_pds 66 TI_SCI_PD_EXCLUSIVE>;
1436 ti,timer-pwm; 1193 ti,timer-pwm;
1437 }; 1194 };
1438 1195
1439 main_timer16: timer@2500000 { 1196 main_timer16: timer@2500000 {
1440 compatible = "ti,am654-timer" 1197 compatible = "ti,am654-timer";
1441 reg = <0x00 0x2500000 0x00 0x 1198 reg = <0x00 0x2500000 0x00 0x400>;
1442 interrupts = <GIC_SPI 240 IRQ 1199 interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
1443 clocks = <&k3_clks 67 1>; 1200 clocks = <&k3_clks 67 1>;
1444 clock-names = "fck"; 1201 clock-names = "fck";
1445 assigned-clocks = <&k3_clks 6 1202 assigned-clocks = <&k3_clks 67 1>;
1446 assigned-clock-parents = <&k3 1203 assigned-clock-parents = <&k3_clks 67 2>;
1447 power-domains = <&k3_pds 67 T 1204 power-domains = <&k3_pds 67 TI_SCI_PD_EXCLUSIVE>;
1448 ti,timer-pwm; 1205 ti,timer-pwm;
1449 }; 1206 };
1450 1207
1451 main_timer17: timer@2510000 { 1208 main_timer17: timer@2510000 {
1452 compatible = "ti,am654-timer" 1209 compatible = "ti,am654-timer";
1453 reg = <0x00 0x2510000 0x00 0x 1210 reg = <0x00 0x2510000 0x00 0x400>;
1454 interrupts = <GIC_SPI 241 IRQ 1211 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
1455 clocks = <&k3_clks 68 1>; 1212 clocks = <&k3_clks 68 1>;
1456 clock-names = "fck"; 1213 clock-names = "fck";
1457 assigned-clocks = <&k3_clks 6 1214 assigned-clocks = <&k3_clks 68 1>, <&k3_clks 321 0>;
1458 assigned-clock-parents = <&k3 1215 assigned-clock-parents = <&k3_clks 68 2>, <&k3_clks 321 1>;
1459 power-domains = <&k3_pds 68 T 1216 power-domains = <&k3_pds 68 TI_SCI_PD_EXCLUSIVE>;
1460 ti,timer-pwm; 1217 ti,timer-pwm;
1461 }; 1218 };
1462 1219
1463 main_timer18: timer@2520000 { 1220 main_timer18: timer@2520000 {
1464 compatible = "ti,am654-timer" 1221 compatible = "ti,am654-timer";
1465 reg = <0x00 0x2520000 0x00 0x 1222 reg = <0x00 0x2520000 0x00 0x400>;
1466 interrupts = <GIC_SPI 242 IRQ 1223 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>;
1467 clocks = <&k3_clks 69 1>; 1224 clocks = <&k3_clks 69 1>;
1468 clock-names = "fck"; 1225 clock-names = "fck";
1469 assigned-clocks = <&k3_clks 6 1226 assigned-clocks = <&k3_clks 69 1>;
1470 assigned-clock-parents = <&k3 1227 assigned-clock-parents = <&k3_clks 69 2>;
1471 power-domains = <&k3_pds 69 T 1228 power-domains = <&k3_pds 69 TI_SCI_PD_EXCLUSIVE>;
1472 ti,timer-pwm; 1229 ti,timer-pwm;
1473 }; 1230 };
1474 1231
1475 main_timer19: timer@2530000 { 1232 main_timer19: timer@2530000 {
1476 compatible = "ti,am654-timer" 1233 compatible = "ti,am654-timer";
1477 reg = <0x00 0x2530000 0x00 0x 1234 reg = <0x00 0x2530000 0x00 0x400>;
1478 interrupts = <GIC_SPI 243 IRQ 1235 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
1479 clocks = <&k3_clks 70 1>; 1236 clocks = <&k3_clks 70 1>;
1480 clock-names = "fck"; 1237 clock-names = "fck";
1481 assigned-clocks = <&k3_clks 7 1238 assigned-clocks = <&k3_clks 70 1>, <&k3_clks 322 0>;
1482 assigned-clock-parents = <&k3 1239 assigned-clock-parents = <&k3_clks 70 2>, <&k3_clks 322 1>;
1483 power-domains = <&k3_pds 70 T 1240 power-domains = <&k3_pds 70 TI_SCI_PD_EXCLUSIVE>;
1484 ti,timer-pwm; 1241 ti,timer-pwm;
1485 }; 1242 };
1486 1243
1487 main_r5fss0: r5fss@5c00000 { 1244 main_r5fss0: r5fss@5c00000 {
1488 compatible = "ti,j7200-r5fss" 1245 compatible = "ti,j7200-r5fss";
1489 ti,cluster-mode = <1>; 1246 ti,cluster-mode = <1>;
1490 #address-cells = <1>; 1247 #address-cells = <1>;
1491 #size-cells = <1>; 1248 #size-cells = <1>;
1492 ranges = <0x5c00000 0x00 0x5c 1249 ranges = <0x5c00000 0x00 0x5c00000 0x20000>,
1493 <0x5d00000 0x00 0x5d 1250 <0x5d00000 0x00 0x5d00000 0x20000>;
1494 power-domains = <&k3_pds 243 1251 power-domains = <&k3_pds 243 TI_SCI_PD_EXCLUSIVE>;
1495 1252
1496 main_r5fss0_core0: r5f@5c0000 1253 main_r5fss0_core0: r5f@5c00000 {
1497 compatible = "ti,j720 1254 compatible = "ti,j7200-r5f";
1498 reg = <0x5c00000 0x00 1255 reg = <0x5c00000 0x00010000>,
1499 <0x5c10000 0x00 1256 <0x5c10000 0x00010000>;
1500 reg-names = "atcm", " 1257 reg-names = "atcm", "btcm";
1501 ti,sci = <&dmsc>; 1258 ti,sci = <&dmsc>;
1502 ti,sci-dev-id = <245> 1259 ti,sci-dev-id = <245>;
1503 ti,sci-proc-ids = <0x 1260 ti,sci-proc-ids = <0x06 0xff>;
1504 resets = <&k3_reset 2 1261 resets = <&k3_reset 245 1>;
1505 firmware-name = "j720 1262 firmware-name = "j7200-main-r5f0_0-fw";
1506 ti,atcm-enable = <1>; 1263 ti,atcm-enable = <1>;
1507 ti,btcm-enable = <1>; 1264 ti,btcm-enable = <1>;
1508 ti,loczrama = <1>; 1265 ti,loczrama = <1>;
1509 }; 1266 };
1510 1267
1511 main_r5fss0_core1: r5f@5d0000 1268 main_r5fss0_core1: r5f@5d00000 {
1512 compatible = "ti,j720 1269 compatible = "ti,j7200-r5f";
1513 reg = <0x5d00000 0x00 1270 reg = <0x5d00000 0x00008000>,
1514 <0x5d10000 0x00 1271 <0x5d10000 0x00008000>;
1515 reg-names = "atcm", " 1272 reg-names = "atcm", "btcm";
1516 ti,sci = <&dmsc>; 1273 ti,sci = <&dmsc>;
1517 ti,sci-dev-id = <246> 1274 ti,sci-dev-id = <246>;
1518 ti,sci-proc-ids = <0x 1275 ti,sci-proc-ids = <0x07 0xff>;
1519 resets = <&k3_reset 2 1276 resets = <&k3_reset 246 1>;
1520 firmware-name = "j720 1277 firmware-name = "j7200-main-r5f0_1-fw";
1521 ti,atcm-enable = <1>; 1278 ti,atcm-enable = <1>;
1522 ti,btcm-enable = <1>; 1279 ti,btcm-enable = <1>;
1523 ti,loczrama = <1>; 1280 ti,loczrama = <1>;
1524 }; 1281 };
1525 }; 1282 };
1526 1283
1527 main_esm: esm@700000 { 1284 main_esm: esm@700000 {
1528 compatible = "ti,j721e-esm"; 1285 compatible = "ti,j721e-esm";
1529 reg = <0x0 0x700000 0x0 0x100 1286 reg = <0x0 0x700000 0x0 0x1000>;
1530 ti,esm-pins = <656>, <657>; 1287 ti,esm-pins = <656>, <657>;
1531 }; 1288 };
1532 }; 1289 };
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