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Linux/scripts/dtc/include-prefixes/arm64/ti/k3-j7200.dtsi

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Diff markup

Differences between /scripts/dtc/include-prefixes/arm64/ti/k3-j7200.dtsi (Version linux-6.12-rc7) and /scripts/dtc/include-prefixes/arm64/ti/k3-j7200.dtsi (Version linux-2.6.0)


  1 // SPDX-License-Identifier: GPL-2.0-only OR MI    
  2 /*                                                
  3  * Device Tree Source for J7200 SoC Family        
  4  *                                                
  5  * Copyright (C) 2020-2024 Texas Instruments I    
  6  */                                               
  7                                                   
  8 #include <dt-bindings/interrupt-controller/irq    
  9 #include <dt-bindings/interrupt-controller/arm    
 10 #include <dt-bindings/soc/ti,sci_pm_domain.h>     
 11                                                   
 12 #include "k3-pinctrl.h"                           
 13                                                   
 14 / {                                               
 15         model = "Texas Instruments K3 J7200 So    
 16         compatible = "ti,j7200";                  
 17         interrupt-parent = <&gic500>;             
 18         #address-cells = <2>;                     
 19         #size-cells = <2>;                        
 20                                                   
 21         chosen { };                               
 22                                                   
 23         cpus {                                    
 24                 #address-cells = <1>;             
 25                 #size-cells = <0>;                
 26                 cpu-map {                         
 27                         cluster0: cluster0 {      
 28                                 core0 {           
 29                                         cpu =     
 30                                 };                
 31                                                   
 32                                 core1 {           
 33                                         cpu =     
 34                                 };                
 35                         };                        
 36                                                   
 37                 };                                
 38                                                   
 39                 cpu0: cpu@0 {                     
 40                         compatible = "arm,cort    
 41                         reg = <0x000>;            
 42                         device_type = "cpu";      
 43                         enable-method = "psci"    
 44                         i-cache-size = <0xc000    
 45                         i-cache-line-size = <6    
 46                         i-cache-sets = <256>;     
 47                         d-cache-size = <0x8000    
 48                         d-cache-line-size = <6    
 49                         d-cache-sets = <256>;     
 50                         next-level-cache = <&L    
 51                 };                                
 52                                                   
 53                 cpu1: cpu@1 {                     
 54                         compatible = "arm,cort    
 55                         reg = <0x001>;            
 56                         device_type = "cpu";      
 57                         enable-method = "psci"    
 58                         i-cache-size = <0xc000    
 59                         i-cache-line-size = <6    
 60                         i-cache-sets = <256>;     
 61                         d-cache-size = <0x8000    
 62                         d-cache-line-size = <6    
 63                         d-cache-sets = <256>;     
 64                         next-level-cache = <&L    
 65                 };                                
 66         };                                        
 67                                                   
 68         L2_0: l2-cache0 {                         
 69                 compatible = "cache";             
 70                 cache-level = <2>;                
 71                 cache-unified;                    
 72                 cache-size = <0x100000>;          
 73                 cache-line-size = <64>;           
 74                 cache-sets = <1024>;              
 75                 next-level-cache = <&msmc_l3>;    
 76         };                                        
 77                                                   
 78         msmc_l3: l3-cache0 {                      
 79                 compatible = "cache";             
 80                 cache-level = <3>;                
 81                 cache-unified;                    
 82         };                                        
 83                                                   
 84         firmware {                                
 85                 optee {                           
 86                         compatible = "linaro,o    
 87                         method = "smc";           
 88                 };                                
 89                                                   
 90                 psci: psci {                      
 91                         compatible = "arm,psci    
 92                         method = "smc";           
 93                 };                                
 94         };                                        
 95                                                   
 96         a72_timer0: timer-cl0-cpu0 {              
 97                 compatible = "arm,armv8-timer"    
 98                 interrupts = <GIC_PPI 13 IRQ_T    
 99                              <GIC_PPI 14 IRQ_T    
100                              <GIC_PPI 11 IRQ_T    
101                              <GIC_PPI 10 IRQ_T    
102         };                                        
103                                                   
104         pmu: pmu {                                
105                 compatible = "arm,cortex-a72-p    
106                 interrupts = <GIC_PPI 7 IRQ_TY    
107         };                                        
108                                                   
109         cbass_main: bus@100000 {                  
110                 compatible = "simple-bus";        
111                 #address-cells = <2>;             
112                 #size-cells = <2>;                
113                 ranges = <0x00 0x00100000 0x00    
114                          <0x00 0x00600000 0x00    
115                          <0x00 0x00700000 0x00    
116                          <0x00 0x00a40000 0x00    
117                          <0x00 0x01000000 0x00    
118                          <0x00 0x30000000 0x00    
119                          <0x00 0x6f000000 0x00    
120                          <0x00 0x70000000 0x00    
121                          <0x00 0x18000000 0x00    
122                          <0x41 0x00000000 0x41    
123                                                   
124                          /* MCUSS_WKUP Range *    
125                          <0x00 0x28380000 0x00    
126                          <0x00 0x40200000 0x00    
127                          <0x00 0x40f00000 0x00    
128                          <0x00 0x41000000 0x00    
129                          <0x00 0x41400000 0x00    
130                          <0x00 0x41c00000 0x00    
131                          <0x00 0x42040000 0x00    
132                          <0x00 0x45100000 0x00    
133                          <0x00 0x46000000 0x00    
134                          <0x00 0x47000000 0x00    
135                          <0x00 0x50000000 0x00    
136                          <0x05 0x00000000 0x05    
137                          <0x07 0x00000000 0x07    
138                                                   
139                 cbass_mcu_wakeup: bus@28380000    
140                         compatible = "simple-b    
141                         #address-cells = <2>;     
142                         #size-cells = <2>;        
143                         ranges = <0x00 0x28380    
144                                  <0x00 0x40200    
145                                  <0x00 0x40f00    
146                                  <0x00 0x41000    
147                                  <0x00 0x41400    
148                                  <0x00 0x41c00    
149                                  <0x00 0x42040    
150                                  <0x00 0x45100    
151                                  <0x00 0x46000    
152                                  <0x00 0x47000    
153                                  <0x00 0x50000    
154                                  <0x05 0x00000    
155                                  <0x07 0x00000    
156                 };                                
157         };                                        
158                                                   
159         #include "k3-j7200-thermal.dtsi"          
160 };                                                
161                                                   
162 /* Now include the peripherals for each bus se    
163 #include "k3-j7200-main.dtsi"                     
164 #include "k3-j7200-mcu-wakeup.dtsi"               
                                                      

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