1 // SPDX-License-Identifier: GPL-2.0-only OR MI !! 1 // SPDX-License-Identifier: GPL-2.0 2 /* 2 /* 3 * Device Tree Source for J7200 SoC Family 3 * Device Tree Source for J7200 SoC Family 4 * 4 * 5 * Copyright (C) 2020-2024 Texas Instruments I !! 5 * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/ 6 */ 6 */ 7 7 8 #include <dt-bindings/interrupt-controller/irq 8 #include <dt-bindings/interrupt-controller/irq.h> 9 #include <dt-bindings/interrupt-controller/arm 9 #include <dt-bindings/interrupt-controller/arm-gic.h> >> 10 #include <dt-bindings/pinctrl/k3.h> 10 #include <dt-bindings/soc/ti,sci_pm_domain.h> 11 #include <dt-bindings/soc/ti,sci_pm_domain.h> 11 12 12 #include "k3-pinctrl.h" << 13 << 14 / { 13 / { 15 model = "Texas Instruments K3 J7200 So 14 model = "Texas Instruments K3 J7200 SoC"; 16 compatible = "ti,j7200"; 15 compatible = "ti,j7200"; 17 interrupt-parent = <&gic500>; 16 interrupt-parent = <&gic500>; 18 #address-cells = <2>; 17 #address-cells = <2>; 19 #size-cells = <2>; 18 #size-cells = <2>; 20 19 >> 20 aliases { >> 21 serial0 = &wkup_uart0; >> 22 serial1 = &mcu_uart0; >> 23 serial2 = &main_uart0; >> 24 serial3 = &main_uart1; >> 25 serial4 = &main_uart2; >> 26 serial5 = &main_uart3; >> 27 serial6 = &main_uart4; >> 28 serial7 = &main_uart5; >> 29 serial8 = &main_uart6; >> 30 serial9 = &main_uart7; >> 31 serial10 = &main_uart8; >> 32 serial11 = &main_uart9; >> 33 }; >> 34 21 chosen { }; 35 chosen { }; 22 36 23 cpus { 37 cpus { 24 #address-cells = <1>; 38 #address-cells = <1>; 25 #size-cells = <0>; 39 #size-cells = <0>; 26 cpu-map { 40 cpu-map { 27 cluster0: cluster0 { 41 cluster0: cluster0 { 28 core0 { 42 core0 { 29 cpu = 43 cpu = <&cpu0>; 30 }; 44 }; 31 45 32 core1 { 46 core1 { 33 cpu = 47 cpu = <&cpu1>; 34 }; 48 }; 35 }; 49 }; 36 50 37 }; 51 }; 38 52 39 cpu0: cpu@0 { 53 cpu0: cpu@0 { 40 compatible = "arm,cort 54 compatible = "arm,cortex-a72"; 41 reg = <0x000>; 55 reg = <0x000>; 42 device_type = "cpu"; 56 device_type = "cpu"; 43 enable-method = "psci" 57 enable-method = "psci"; 44 i-cache-size = <0xc000 58 i-cache-size = <0xc000>; 45 i-cache-line-size = <6 59 i-cache-line-size = <64>; 46 i-cache-sets = <256>; 60 i-cache-sets = <256>; 47 d-cache-size = <0x8000 61 d-cache-size = <0x8000>; 48 d-cache-line-size = <6 62 d-cache-line-size = <64>; 49 d-cache-sets = <256>; 63 d-cache-sets = <256>; 50 next-level-cache = <&L 64 next-level-cache = <&L2_0>; 51 }; 65 }; 52 66 53 cpu1: cpu@1 { 67 cpu1: cpu@1 { 54 compatible = "arm,cort 68 compatible = "arm,cortex-a72"; 55 reg = <0x001>; 69 reg = <0x001>; 56 device_type = "cpu"; 70 device_type = "cpu"; 57 enable-method = "psci" 71 enable-method = "psci"; 58 i-cache-size = <0xc000 72 i-cache-size = <0xc000>; 59 i-cache-line-size = <6 73 i-cache-line-size = <64>; 60 i-cache-sets = <256>; 74 i-cache-sets = <256>; 61 d-cache-size = <0x8000 75 d-cache-size = <0x8000>; 62 d-cache-line-size = <6 76 d-cache-line-size = <64>; 63 d-cache-sets = <256>; 77 d-cache-sets = <256>; 64 next-level-cache = <&L 78 next-level-cache = <&L2_0>; 65 }; 79 }; 66 }; 80 }; 67 81 68 L2_0: l2-cache0 { 82 L2_0: l2-cache0 { 69 compatible = "cache"; 83 compatible = "cache"; 70 cache-level = <2>; 84 cache-level = <2>; 71 cache-unified; << 72 cache-size = <0x100000>; 85 cache-size = <0x100000>; 73 cache-line-size = <64>; 86 cache-line-size = <64>; 74 cache-sets = <1024>; 87 cache-sets = <1024>; 75 next-level-cache = <&msmc_l3>; 88 next-level-cache = <&msmc_l3>; 76 }; 89 }; 77 90 78 msmc_l3: l3-cache0 { 91 msmc_l3: l3-cache0 { 79 compatible = "cache"; 92 compatible = "cache"; 80 cache-level = <3>; 93 cache-level = <3>; 81 cache-unified; << 82 }; 94 }; 83 95 84 firmware { 96 firmware { 85 optee { 97 optee { 86 compatible = "linaro,o 98 compatible = "linaro,optee-tz"; 87 method = "smc"; 99 method = "smc"; 88 }; 100 }; 89 101 90 psci: psci { 102 psci: psci { 91 compatible = "arm,psci 103 compatible = "arm,psci-1.0"; 92 method = "smc"; 104 method = "smc"; 93 }; 105 }; 94 }; 106 }; 95 107 96 a72_timer0: timer-cl0-cpu0 { 108 a72_timer0: timer-cl0-cpu0 { 97 compatible = "arm,armv8-timer" 109 compatible = "arm,armv8-timer"; 98 interrupts = <GIC_PPI 13 IRQ_T 110 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* cntpsirq */ 99 <GIC_PPI 14 IRQ_T 111 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* cntpnsirq */ 100 <GIC_PPI 11 IRQ_T 112 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* cntvirq */ 101 <GIC_PPI 10 IRQ_T 113 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* cnthpirq */ 102 }; 114 }; 103 115 104 pmu: pmu { 116 pmu: pmu { 105 compatible = "arm,cortex-a72-p 117 compatible = "arm,cortex-a72-pmu"; 106 interrupts = <GIC_PPI 7 IRQ_TY 118 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 107 }; 119 }; 108 120 109 cbass_main: bus@100000 { 121 cbass_main: bus@100000 { 110 compatible = "simple-bus"; 122 compatible = "simple-bus"; 111 #address-cells = <2>; 123 #address-cells = <2>; 112 #size-cells = <2>; 124 #size-cells = <2>; 113 ranges = <0x00 0x00100000 0x00 125 ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */ 114 <0x00 0x00600000 0x00 126 <0x00 0x00600000 0x00 0x00600000 0x00 0x00031100>, /* GPIO */ 115 <0x00 0x00700000 0x00 << 116 <0x00 0x00a40000 0x00 127 <0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* timesync router */ 117 <0x00 0x01000000 0x00 128 <0x00 0x01000000 0x00 0x01000000 0x00 0x0d000000>, /* Most peripherals */ 118 <0x00 0x30000000 0x00 129 <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>, /* MAIN NAVSS */ 119 <0x00 0x6f000000 0x00 130 <0x00 0x6f000000 0x00 0x6f000000 0x00 0x00310000>, /* A72 PERIPHBASE */ 120 <0x00 0x70000000 0x00 131 <0x00 0x70000000 0x00 0x70000000 0x00 0x00800000>, /* MSMC RAM */ 121 <0x00 0x18000000 0x00 132 <0x00 0x18000000 0x00 0x18000000 0x00 0x08000000>, /* PCIe1 DAT0 */ 122 <0x41 0x00000000 0x41 133 <0x41 0x00000000 0x41 0x00000000 0x01 0x00000000>, /* PCIe1 DAT1 */ 123 134 124 /* MCUSS_WKUP Range * 135 /* MCUSS_WKUP Range */ 125 <0x00 0x28380000 0x00 136 <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>, 126 <0x00 0x40200000 0x00 137 <0x00 0x40200000 0x00 0x40200000 0x00 0x00998400>, 127 <0x00 0x40f00000 0x00 138 <0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>, 128 <0x00 0x41000000 0x00 139 <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>, 129 <0x00 0x41400000 0x00 140 <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>, 130 <0x00 0x41c00000 0x00 141 <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00100000>, 131 <0x00 0x42040000 0x00 142 <0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>, 132 <0x00 0x45100000 0x00 143 <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>, 133 <0x00 0x46000000 0x00 144 <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>, 134 <0x00 0x47000000 0x00 145 <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>, 135 <0x00 0x50000000 0x00 146 <0x00 0x50000000 0x00 0x50000000 0x00 0x10000000>, 136 <0x05 0x00000000 0x05 147 <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, 137 <0x07 0x00000000 0x07 148 <0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>; 138 149 139 cbass_mcu_wakeup: bus@28380000 150 cbass_mcu_wakeup: bus@28380000 { 140 compatible = "simple-b 151 compatible = "simple-bus"; 141 #address-cells = <2>; 152 #address-cells = <2>; 142 #size-cells = <2>; 153 #size-cells = <2>; 143 ranges = <0x00 0x28380 154 ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>, /* MCU NAVSS*/ 144 <0x00 0x40200 155 <0x00 0x40200000 0x00 0x40200000 0x00 0x00998400>, /* First peripheral window */ 145 <0x00 0x40f00 156 <0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>, /* CTRL_MMR0 */ 146 <0x00 0x41000 157 <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>, /* MCU R5F Core0 */ 147 <0x00 0x41400 158 <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>, /* MCU R5F Core1 */ 148 <0x00 0x41c00 159 <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00100000>, /* MCU SRAM */ 149 <0x00 0x42040 160 <0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>, /* WKUP peripheral window */ 150 <0x00 0x45100 161 <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>, /* MMRs, remaining NAVSS */ 151 <0x00 0x46000 162 <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>, /* CPSW */ 152 <0x00 0x47000 163 <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>, /* OSPI register space */ 153 <0x00 0x50000 164 <0x00 0x50000000 0x00 0x50000000 0x00 0x10000000>, /* FSS OSPI0/1 data region 0 */ 154 <0x05 0x00000 165 <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, /* FSS OSPI0 data region 3 */ 155 <0x07 0x00000 166 <0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>; /* FSS OSPI1 data region 3 */ 156 }; 167 }; 157 }; 168 }; 158 << 159 #include "k3-j7200-thermal.dtsi" << 160 }; 169 }; 161 170 162 /* Now include the peripherals for each bus se 171 /* Now include the peripherals for each bus segments */ 163 #include "k3-j7200-main.dtsi" 172 #include "k3-j7200-main.dtsi" 164 #include "k3-j7200-mcu-wakeup.dtsi" 173 #include "k3-j7200-mcu-wakeup.dtsi"
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