1 // SPDX-License-Identifier: GPL-2.0-only OR MI
2 /*
3 * https://beagleboard.org/ai-64
4 * Copyright (C) 2022-2024 Texas Instruments I
5 * Copyright (C) 2022-2024 Jason Kridner, Beag
6 * Copyright (C) 2022-2024 Robert Nelson, Beag
7 */
8
9 /dts-v1/;
10
11 #include "k3-j721e.dtsi"
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/input/input.h>
14 #include <dt-bindings/leds/common.h>
15 #include <dt-bindings/net/ti-dp83867.h>
16 #include <dt-bindings/phy/phy-cadence.h>
17
18 / {
19 compatible = "beagle,j721e-beaglebonea
20 model = "BeagleBoard.org BeagleBone AI
21
22 aliases {
23 serial0 = &wkup_uart0;
24 serial2 = &main_uart0;
25 mmc0 = &main_sdhci0;
26 mmc1 = &main_sdhci1;
27 i2c0 = &wkup_i2c0;
28 i2c1 = &main_i2c6;
29 i2c2 = &main_i2c2;
30 i2c3 = &main_i2c4;
31 };
32
33 chosen {
34 stdout-path = "serial2:115200n
35 };
36
37 memory@80000000 {
38 device_type = "memory";
39 /* 4G RAM */
40 reg = <0x00000000 0x80000000 0
41 <0x00000008 0x80000000 0
42 };
43
44 reserved_memory: reserved-memory {
45 #address-cells = <2>;
46 #size-cells = <2>;
47 ranges;
48
49 secure_ddr: optee@9e800000 {
50 reg = <0x00 0x9e800000
51 no-map;
52 };
53
54 mcu_r5fss0_core0_dma_memory_re
55 compatible = "shared-d
56 reg = <0x00 0xa0000000
57 no-map;
58 };
59
60 mcu_r5fss0_core0_memory_region
61 compatible = "shared-d
62 reg = <0x00 0xa0100000
63 no-map;
64 };
65
66 mcu_r5fss0_core1_dma_memory_re
67 compatible = "shared-d
68 reg = <0x00 0xa1000000
69 no-map;
70 };
71
72 mcu_r5fss0_core1_memory_region
73 compatible = "shared-d
74 reg = <0x00 0xa1100000
75 no-map;
76 };
77
78 main_r5fss0_core0_dma_memory_r
79 compatible = "shared-d
80 reg = <0x00 0xa2000000
81 no-map;
82 };
83
84 main_r5fss0_core0_memory_regio
85 compatible = "shared-d
86 reg = <0x00 0xa2100000
87 no-map;
88 };
89
90 main_r5fss0_core1_dma_memory_r
91 compatible = "shared-d
92 reg = <0x00 0xa3000000
93 no-map;
94 };
95
96 main_r5fss0_core1_memory_regio
97 compatible = "shared-d
98 reg = <0x00 0xa3100000
99 no-map;
100 };
101
102 main_r5fss1_core0_dma_memory_r
103 compatible = "shared-d
104 reg = <0x00 0xa4000000
105 no-map;
106 };
107
108 main_r5fss1_core0_memory_regio
109 compatible = "shared-d
110 reg = <0x00 0xa4100000
111 no-map;
112 };
113
114 main_r5fss1_core1_dma_memory_r
115 compatible = "shared-d
116 reg = <0x00 0xa5000000
117 no-map;
118 };
119
120 main_r5fss1_core1_memory_regio
121 compatible = "shared-d
122 reg = <0x00 0xa5100000
123 no-map;
124 };
125
126 c66_0_dma_memory_region: c66-d
127 compatible = "shared-d
128 reg = <0x00 0xa6000000
129 no-map;
130 };
131
132 c66_0_memory_region: c66-memor
133 compatible = "shared-d
134 reg = <0x00 0xa6100000
135 no-map;
136 };
137
138 c66_1_dma_memory_region: c66-d
139 compatible = "shared-d
140 reg = <0x00 0xa7000000
141 no-map;
142 };
143
144 c66_1_memory_region: c66-memor
145 compatible = "shared-d
146 reg = <0x00 0xa7100000
147 no-map;
148 };
149
150 c71_0_dma_memory_region: c71-d
151 compatible = "shared-d
152 reg = <0x00 0xa8000000
153 no-map;
154 };
155
156 c71_0_memory_region: c71-memor
157 compatible = "shared-d
158 reg = <0x00 0xa8100000
159 no-map;
160 };
161
162 rtos_ipc_memory_region: ipc-me
163 reg = <0x00 0xaa000000
164 alignment = <0x1000>;
165 no-map;
166 };
167 };
168
169 gpio_keys: gpio-keys {
170 compatible = "gpio-keys";
171 pinctrl-names = "default";
172 pinctrl-0 = <&sw_pwr_pins_defa
173
174 button-1 {
175 label = "BOOT";
176 linux,code = <BTN_0>;
177 gpios = <&wkup_gpio0 0
178 };
179
180 button-2 {
181 label = "POWER";
182 linux,code = <KEY_POWE
183 gpios = <&wkup_gpio0 4
184 };
185 };
186
187 leds {
188 compatible = "gpio-leds";
189 pinctrl-names = "default";
190 pinctrl-0 = <&led_pins_default
191
192 led-0 {
193 gpios = <&main_gpio0 9
194 function = LED_FUNCTIO
195 linux,default-trigger
196 };
197
198 led-1 {
199 gpios = <&main_gpio0 9
200 function = LED_FUNCTIO
201 linux,default-trigger
202 };
203
204 led-2 {
205 gpios = <&main_gpio0 9
206 function = LED_FUNCTIO
207 linux,default-trigger
208 };
209
210 led-3 {
211 gpios = <&main_gpio0 1
212 function = LED_FUNCTIO
213 linux,default-trigger
214 };
215
216 led-4 {
217 gpios = <&main_gpio0 1
218 function = LED_FUNCTIO
219 default-state = "off";
220 };
221 };
222
223 evm_12v0: regulator-0 {
224 /* main supply */
225 compatible = "regulator-fixed"
226 regulator-name = "evm_12v0";
227 regulator-min-microvolt = <120
228 regulator-max-microvolt = <120
229 regulator-always-on;
230 regulator-boot-on;
231 };
232
233 vsys_3v3: regulator-1 {
234 /* Output of LMS140 */
235 compatible = "regulator-fixed"
236 regulator-name = "vsys_3v3";
237 regulator-min-microvolt = <330
238 regulator-max-microvolt = <330
239 vin-supply = <&evm_12v0>;
240 regulator-always-on;
241 regulator-boot-on;
242 };
243
244 vsys_5v0: regulator-2 {
245 /* Output of LM5140 */
246 compatible = "regulator-fixed"
247 regulator-name = "vsys_5v0";
248 regulator-min-microvolt = <500
249 regulator-max-microvolt = <500
250 vin-supply = <&evm_12v0>;
251 regulator-always-on;
252 regulator-boot-on;
253 };
254
255 vdd_mmc1: regulator-3 {
256 compatible = "regulator-fixed"
257 pinctrl-names = "default";
258 pinctrl-0 = <&sd_pwr_en_pins_d
259 regulator-name = "vdd_mmc1";
260 regulator-min-microvolt = <330
261 regulator-max-microvolt = <330
262 regulator-boot-on;
263 enable-active-high;
264 vin-supply = <&vsys_3v3>;
265 gpio = <&main_gpio0 82 GPIO_AC
266 };
267
268 vdd_sd_dv_alt: regulator-4 {
269 compatible = "regulator-gpio";
270 pinctrl-names = "default";
271 pinctrl-0 = <&vdd_sd_dv_alt_pi
272 regulator-name = "tlv71033";
273 regulator-min-microvolt = <180
274 regulator-max-microvolt = <330
275 regulator-boot-on;
276 vin-supply = <&vsys_5v0>;
277 gpios = <&main_gpio0 117 GPIO_
278 states = <1800000 0x0>,
279 <3300000 0x1>;
280 };
281
282 dp_pwr_3v3: regulator-5 {
283 compatible = "regulator-fixed"
284 pinctrl-names = "default";
285 pinctrl-0 = <&dp0_3v3_en_pins_
286 regulator-name = "dp-pwr";
287 regulator-min-microvolt = <330
288 regulator-max-microvolt = <330
289 gpio = <&main_gpio0 49 GPIO_AC
290 enable-active-high;
291 };
292
293 dp0: connector {
294 compatible = "dp-connector";
295 label = "DP0";
296 type = "full-size";
297 dp-pwr-supply = <&dp_pwr_3v3>;
298
299 port {
300 dp_connector_in: endpo
301 remote-endpoin
302 };
303 };
304 };
305 };
306
307 &main_pmx0 {
308 led_pins_default: led-default-pins {
309 pinctrl-single,pins = <
310 J721E_IOPAD(0x184, PIN
311 J721E_IOPAD(0x180, PIN
312 J721E_IOPAD(0x188, PIN
313 J721E_IOPAD(0x1bc, PIN
314 J721E_IOPAD(0x1b8, PIN
315 >;
316 };
317
318 main_mmc1_pins_default: main-mmc1-defa
319 pinctrl-single,pins = <
320 J721E_IOPAD(0x254, PIN
321 J721E_IOPAD(0x250, PIN
322 J721E_IOPAD(0x2ac, PIN
323 J721E_IOPAD(0x24c, PIN
324 J721E_IOPAD(0x248, PIN
325 J721E_IOPAD(0x244, PIN
326 J721E_IOPAD(0x240, PIN
327 J721E_IOPAD(0x258, PIN
328 >;
329 };
330
331 main_uart0_pins_default: main-uart0-de
332 pinctrl-single,pins = <
333 J721E_IOPAD(0x1e8, PIN
334 J721E_IOPAD(0x1ec, PIN
335 >;
336 };
337
338 sd_pwr_en_pins_default: sd-pwr-en-defa
339 pinctrl-single,pins = <
340 J721E_IOPAD(0x14c, PIN
341 >;
342 };
343
344 vdd_sd_dv_alt_pins_default: vdd-sd-dv-
345 pinctrl-single,pins = <
346 J721E_IOPAD(0x1d8, PIN
347 >;
348 };
349
350 main_usbss0_pins_default: main-usbss0-
351 pinctrl-single,pins = <
352 J721E_IOPAD(0x210, PIN
353 >;
354 };
355
356 main_usbss1_pins_default: main-usbss1-
357 pinctrl-single,pins = <
358 J721E_IOPAD(0x290, INP
359 >;
360 };
361
362 dp0_3v3_en_pins_default:dp0-3v3-en-def
363 pinctrl-single,pins = <
364 J721E_IOPAD(0xc8, PIN_
365 >;
366 };
367
368 dp0_pins_default: dp0-default-pins {
369 pinctrl-single,pins = <
370 J721E_IOPAD(0x1c4, PIN
371 >;
372 };
373
374 main_i2c0_pins_default: main-i2c0-defa
375 pinctrl-single,pins = <
376 J721E_IOPAD(0x220, PIN
377 J721E_IOPAD(0x224, PIN
378 >;
379 };
380
381 main_i2c1_pins_default: main-i2c1-defa
382 pinctrl-single,pins = <
383 J721E_IOPAD(0x228, PIN
384 J721E_IOPAD(0x22c, PIN
385 >;
386 };
387
388 main_i2c2_pins_default: main-i2c2-defa
389 pinctrl-single,pins = <
390 J721E_IOPAD(0x208, PIN
391 J721E_IOPAD(0x20c, PIN
392 J721E_IOPAD(0x138, PIN
393 J721E_IOPAD(0x13c, PIN
394 >;
395 };
396
397 main_i2c3_pins_default: main-i2c3-defa
398 pinctrl-single,pins = <
399 J721E_IOPAD(0x270, PIN
400 J721E_IOPAD(0x274, PIN
401 >;
402 };
403
404 main_i2c4_pins_default: main-i2c4-defa
405 pinctrl-single,pins = <
406 J721E_IOPAD(0x1e0, PIN
407 J721E_IOPAD(0x1dc, PIN
408 J721E_IOPAD(0x30, PIN_
409 J721E_IOPAD(0x34, PIN_
410 >;
411 };
412
413 main_i2c5_pins_default: main-i2c5-defa
414 pinctrl-single,pins = <
415 J721E_IOPAD(0x150, PIN
416 J721E_IOPAD(0x154, PIN
417 >;
418 };
419
420 main_i2c6_pins_default: main-i2c6-defa
421 pinctrl-single,pins = <
422 J721E_IOPAD(0x1d0, PIN
423 J721E_IOPAD(0x1e4, PIN
424 J721E_IOPAD(0x74, PIN_
425 J721E_IOPAD(0xa4, PIN_
426 >;
427 };
428
429 csi0_gpio_pins_default: csi0-gpio-defa
430 pinctrl-single,pins = <
431 J721E_IOPAD(0x19c, PIN
432 J721E_IOPAD(0x1a0, PIN
433 >;
434 };
435
436 csi1_gpio_pins_default: csi1-gpio-defa
437 pinctrl-single,pins = <
438 J721E_IOPAD(0x198, PIN
439 J721E_IOPAD(0x1b0, PIN
440 >;
441 };
442
443 pcie1_rst_pins_default: pcie1-rst-defa
444 pinctrl-single,pins = <
445 J721E_IOPAD(0x5c, PIN_
446 >;
447 };
448 };
449
450 &wkup_pmx0 {
451 eeprom_wp_pins_default: eeprom-wp-defa
452 pinctrl-single,pins = <
453 J721E_WKUP_IOPAD(0xc4,
454 >;
455 };
456
457 mcu_adc0_pins_default: mcu-adc0-defaul
458 pinctrl-single,pins = <
459 J721E_WKUP_IOPAD(0x130
460 J721E_WKUP_IOPAD(0x134
461 J721E_WKUP_IOPAD(0x138
462 J721E_WKUP_IOPAD(0x13c
463 J721E_WKUP_IOPAD(0x140
464 J721E_WKUP_IOPAD(0x144
465 J721E_WKUP_IOPAD(0x148
466 >;
467 };
468
469 mcu_adc1_pins_default: mcu-adc1-defaul
470 pinctrl-single,pins = <
471 J721E_WKUP_IOPAD(0x150
472 >;
473 };
474
475 mikro_bus_pins_default: mikro-bus-defa
476 pinctrl-single,pins = <
477 J721E_WKUP_IOPAD(0x108
478 J721E_WKUP_IOPAD(0xd4,
479 J721E_WKUP_IOPAD(0xf4,
480 J721E_WKUP_IOPAD(0xd0,
481 J721E_WKUP_IOPAD(0xf0,
482
483 J721E_WKUP_IOPAD(0xb8,
484 J721E_WKUP_IOPAD(0xb4,
485 J721E_WKUP_IOPAD(0xb0,
486 J721E_WKUP_IOPAD(0xbc,
487
488 J721E_WKUP_IOPAD(0x44,
489 J721E_WKUP_IOPAD(0x48,
490
491 J721E_WKUP_IOPAD(0x4c,
492 J721E_WKUP_IOPAD(0x54,
493 J721E_WKUP_IOPAD(0xdc,
494 J721E_WKUP_IOPAD(0xac,
495 >;
496 };
497
498 mcu_cpsw_pins_default: mcu-cpsw-defaul
499 pinctrl-single,pins = <
500 J721E_WKUP_IOPAD(0x84,
501 J721E_WKUP_IOPAD(0x80,
502 J721E_WKUP_IOPAD(0x7c,
503 J721E_WKUP_IOPAD(0x78,
504 J721E_WKUP_IOPAD(0x74,
505 J721E_WKUP_IOPAD(0x5c,
506 J721E_WKUP_IOPAD(0x6c,
507 J721E_WKUP_IOPAD(0x68,
508 J721E_WKUP_IOPAD(0x64,
509 J721E_WKUP_IOPAD(0x60,
510 J721E_WKUP_IOPAD(0x70,
511 J721E_WKUP_IOPAD(0x58,
512 >;
513 };
514
515 mcu_mdio_pins_default: mcu-mdio1-defau
516 pinctrl-single,pins = <
517 J721E_WKUP_IOPAD(0x8c,
518 J721E_WKUP_IOPAD(0x88,
519 >;
520 };
521
522 sw_pwr_pins_default: sw-pwr-default-pi
523 pinctrl-single,pins = <
524 J721E_WKUP_IOPAD(0xc0,
525 >;
526 };
527
528 wkup_i2c0_pins_default: wkup-i2c0-defa
529 pinctrl-single,pins = <
530 J721E_WKUP_IOPAD(0xf8,
531 J721E_WKUP_IOPAD(0xfc,
532 >;
533 };
534
535 wkup_uart0_pins_default: wkup-uart0-de
536 pinctrl-single,pins = <
537 J721E_WKUP_IOPAD(0xa0,
538 J721E_WKUP_IOPAD(0xa4,
539 >;
540 };
541
542 mcu_usbss1_pins_default: mcu-usbss1-de
543 pinctrl-single,pins = <
544 J721E_WKUP_IOPAD(0x3c,
545 >;
546 };
547 };
548
549 &wkup_uart0 {
550 /* Wakeup UART is used by TIFS firmwar
551 status = "reserved";
552 pinctrl-names = "default";
553 pinctrl-0 = <&wkup_uart0_pins_default>
554 };
555
556 &main_uart0 {
557 status = "okay";
558 pinctrl-names = "default";
559 pinctrl-0 = <&main_uart0_pins_default>
560 /* Shared with ATF on this platform */
561 power-domains = <&k3_pds 146 TI_SCI_PD
562 };
563
564 &main_sdhci0 {
565 /* eMMC */
566 status = "okay";
567 non-removable;
568 ti,driver-strength-ohm = <50>;
569 disable-wp;
570 };
571
572 &main_sdhci1 {
573 /* SD Card */
574 status = "okay";
575 vmmc-supply = <&vdd_mmc1>;
576 vqmmc-supply = <&vdd_sd_dv_alt>;
577 pinctrl-names = "default";
578 pinctrl-0 = <&main_mmc1_pins_default>;
579 ti,driver-strength-ohm = <50>;
580 disable-wp;
581 };
582
583 &main_i2c0 {
584 status = "okay";
585 pinctrl-names = "default";
586 pinctrl-0 = <&main_i2c0_pins_default>;
587 clock-frequency = <400000>;
588 };
589
590 &main_i2c1 {
591 status = "okay";
592 pinctrl-names = "default";
593 pinctrl-0 = <&main_i2c1_pins_default>;
594 clock-frequency = <400000>;
595 };
596
597 &main_i2c2 {
598 /* BBB Header: P9.19 and P9.20 */
599 status = "okay";
600 pinctrl-names = "default";
601 pinctrl-0 = <&main_i2c2_pins_default>;
602 clock-frequency = <100000>;
603 };
604
605 &main_i2c3 {
606 status = "okay";
607 pinctrl-names = "default";
608 pinctrl-0 = <&main_i2c3_pins_default>;
609 clock-frequency = <400000>;
610 };
611
612 &main_i2c4 {
613 /* BBB Header: P9.24 and P9.26 */
614 status = "okay";
615 pinctrl-names = "default";
616 pinctrl-0 = <&main_i2c4_pins_default>;
617 clock-frequency = <100000>;
618 };
619
620 &main_i2c5 {
621 status = "okay";
622 pinctrl-names = "default";
623 pinctrl-0 = <&main_i2c5_pins_default>;
624 clock-frequency = <400000>;
625 };
626
627 &main_i2c6 {
628 /* BBB Header: P9.17 and P9.18 */
629 status = "okay";
630 pinctrl-names = "default";
631 pinctrl-0 = <&main_i2c6_pins_default>;
632 clock-frequency = <100000>;
633 status = "okay";
634 };
635
636 &wkup_i2c0 {
637 status = "okay";
638 pinctrl-names = "default";
639 pinctrl-0 = <&wkup_i2c0_pins_default>;
640 clock-frequency = <400000>;
641
642 eeprom@50 {
643 compatible = "atmel,24c04";
644 reg = <0x50>;
645 pinctrl-names = "default";
646 pinctrl-0 = <&eeprom_wp_pins_d
647 };
648 };
649
650 &wkup_gpio0 {
651 status = "okay";
652 pinctrl-names = "default";
653 pinctrl-0 = <&mcu_adc0_pins_default>,
654 <&mikro_bus_pins_default>;
655 };
656
657 &main_gpio0 {
658 status = "okay";
659 pinctrl-names = "default";
660 pinctrl-0 = <&csi1_gpio_pins_default>,
661 };
662
663 &main_gpio1 {
664 status = "okay";
665 };
666
667 &usb_serdes_mux {
668 idle-states = <1>, <1>; /* USB0 to SER
669 };
670
671 &serdes_ln_ctrl {
672 idle-states = <J721E_SERDES0_LANE0_IP4
673 <J721E_SERDES1_LANE0_PCI
674 <J721E_SERDES2_LANE0_IP1
675 <J721E_SERDES3_LANE0_USB
676 <J721E_SERDES4_LANE0_EDP
677 <J721E_SERDES4_LANE2_EDP
678 };
679
680 &serdes_wiz3 {
681 typec-dir-gpios = <&main_gpio1 3 GPIO_
682 typec-dir-debounce-ms = <700>; /* TUS
683 };
684
685 &serdes3 {
686 serdes3_usb_link: phy@0 {
687 reg = <0>;
688 cdns,num-lanes = <2>;
689 #phy-cells = <0>;
690 cdns,phy-type = <PHY_TYPE_USB3
691 resets = <&serdes_wiz3 1>, <&s
692 };
693 };
694
695 &serdes4 {
696 torrent_phy_dp: phy@0 {
697 reg = <0>;
698 resets = <&serdes_wiz4 1>;
699 cdns,phy-type = <PHY_TYPE_DP>;
700 cdns,num-lanes = <4>;
701 cdns,max-bit-rate = <5400>;
702 #phy-cells = <0>;
703 };
704 };
705
706 &mhdp {
707 phys = <&torrent_phy_dp>;
708 phy-names = "dpphy";
709 pinctrl-names = "default";
710 pinctrl-0 = <&dp0_pins_default>;
711 };
712
713 &usbss0 {
714 pinctrl-names = "default";
715 pinctrl-0 = <&main_usbss0_pins_default
716 ti,vbus-divider;
717 };
718
719 &usb0 {
720 dr_mode = "peripheral";
721 maximum-speed = "super-speed";
722 phys = <&serdes3_usb_link>;
723 phy-names = "cdns3,usb3-phy";
724 };
725
726 &serdes2 {
727 serdes2_usb_link: phy@1 {
728 reg = <1>;
729 cdns,num-lanes = <1>;
730 #phy-cells = <0>;
731 cdns,phy-type = <PHY_TYPE_USB3
732 resets = <&serdes_wiz2 2>;
733 };
734 };
735
736 &usbss1 {
737 pinctrl-names = "default";
738 pinctrl-0 = <&main_usbss1_pins_default
739 ti,vbus-divider;
740 };
741
742 &usb1 {
743 dr_mode = "host";
744 maximum-speed = "super-speed";
745 phys = <&serdes2_usb_link>;
746 phy-names = "cdns3,usb3-phy";
747 };
748
749 &tscadc0 {
750 status = "okay";
751 /* BBB Header: P9.39, P9.40, P9.37, P9
752 adc {
753 ti,adc-channels = <0 1 2 3 4 5
754 };
755 };
756
757 &tscadc1 {
758 status = "okay";
759 /* MCU mikroBUS Header J10.1 - MCU_ADC
760 adc {
761 ti,adc-channels = <0>;
762 };
763 };
764
765 &mcu_cpsw {
766 pinctrl-names = "default";
767 pinctrl-0 = <&mcu_cpsw_pins_default>;
768 };
769
770 &davinci_mdio {
771 pinctrl-names = "default";
772 pinctrl-0 = <&mcu_mdio_pins_default>;
773
774 phy0: ethernet-phy@0 {
775 reg = <0>;
776 ti,rx-internal-delay = <DP8386
777 ti,fifo-depth = <DP83867_PHYCR
778 };
779 };
780
781 &cpsw_port1 {
782 phy-mode = "rgmii-rxid";
783 phy-handle = <&phy0>;
784 };
785
786 &dss {
787 /*
788 * These clock assignments are chosen
789 *
790 * VP0 - DisplayPort SST
791 * VP1 - DPI0
792 * VP2 - DSI
793 * VP3 - DPI1
794 */
795
796 assigned-clocks = <&k3_clks 152 1>,
797 <&k3_clks 152 4>,
798 <&k3_clks 152 9>,
799 <&k3_clks 152 13>;
800 assigned-clock-parents = <&k3_clks 152
801 <&k3_clks 152
802 <&k3_clks 152
803 <&k3_clks 152
804 };
805
806 &dss_ports {
807 port {
808 dpi0_out: endpoint {
809 remote-endpoint = <&dp
810 };
811 };
812 };
813
814 &dp0_ports {
815 #address-cells = <1>;
816 #size-cells = <0>;
817
818 port@0 {
819 reg = <0>;
820 dp0_in: endpoint {
821 remote-endpoint = <&dp
822 };
823 };
824
825 port@4 {
826 reg = <4>;
827 dp0_out: endpoint {
828 remote-endpoint = <&dp
829 };
830 };
831 };
832
833 &serdes0 {
834 serdes0_pcie_link: phy@0 {
835 reg = <0>;
836 cdns,num-lanes = <1>;
837 #phy-cells = <0>;
838 cdns,phy-type = <PHY_TYPE_PCIE
839 resets = <&serdes_wiz0 1>;
840 };
841 };
842
843 &serdes1 {
844 serdes1_pcie_link: phy@0 {
845 reg = <0>;
846 cdns,num-lanes = <2>;
847 #phy-cells = <0>;
848 cdns,phy-type = <PHY_TYPE_PCIE
849 resets = <&serdes_wiz1 1>, <&s
850 };
851 };
852
853 &pcie1_rc {
854 status = "okay";
855 pinctrl-names = "default";
856 pinctrl-0 = <&pcie1_rst_pins_default>;
857 phys = <&serdes1_pcie_link>;
858 phy-names = "pcie-phy";
859 num-lanes = <2>;
860 max-link-speed = <3>;
861 reset-gpios = <&main_gpio0 22 GPIO_ACT
862 };
863
864 &ufs_wrapper {
865 status = "disabled";
866 };
867
868 &mailbox0_cluster0 {
869 status = "okay";
870 interrupts = <436>;
871
872 mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0
873 ti,mbox-rx = <0 0 0>;
874 ti,mbox-tx = <1 0 0>;
875 };
876
877 mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0
878 ti,mbox-rx = <2 0 0>;
879 ti,mbox-tx = <3 0 0>;
880 };
881 };
882
883 &mailbox0_cluster1 {
884 status = "okay";
885 interrupts = <432>;
886
887 mbox_main_r5fss0_core0: mbox-main-r5fs
888 ti,mbox-rx = <0 0 0>;
889 ti,mbox-tx = <1 0 0>;
890 };
891
892 mbox_main_r5fss0_core1: mbox-main-r5fs
893 ti,mbox-rx = <2 0 0>;
894 ti,mbox-tx = <3 0 0>;
895 };
896 };
897
898 &mailbox0_cluster2 {
899 status = "okay";
900 interrupts = <428>;
901
902 mbox_main_r5fss1_core0: mbox-main-r5fs
903 ti,mbox-rx = <0 0 0>;
904 ti,mbox-tx = <1 0 0>;
905 };
906
907 mbox_main_r5fss1_core1: mbox-main-r5fs
908 ti,mbox-rx = <2 0 0>;
909 ti,mbox-tx = <3 0 0>;
910 };
911 };
912
913 &mailbox0_cluster3 {
914 status = "okay";
915 interrupts = <424>;
916
917 mbox_c66_0: mbox-c66-0 {
918 ti,mbox-rx = <0 0 0>;
919 ti,mbox-tx = <1 0 0>;
920 };
921
922 mbox_c66_1: mbox-c66-1 {
923 ti,mbox-rx = <2 0 0>;
924 ti,mbox-tx = <3 0 0>;
925 };
926 };
927
928 &mailbox0_cluster4 {
929 status = "okay";
930 interrupts = <420>;
931
932 mbox_c71_0: mbox-c71-0 {
933 ti,mbox-rx = <0 0 0>;
934 ti,mbox-tx = <1 0 0>;
935 };
936 };
937
938 &mcu_r5fss0_core0 {
939 mboxes = <&mailbox0_cluster0 &mbox_mcu
940 memory-region = <&mcu_r5fss0_core0_dma
941 <&mcu_r5fss0_core0_mem
942 };
943
944 &mcu_r5fss0_core1 {
945 mboxes = <&mailbox0_cluster0 &mbox_mcu
946 memory-region = <&mcu_r5fss0_core1_dma
947 <&mcu_r5fss0_core1_mem
948 };
949
950 &main_r5fss0_core0 {
951 mboxes = <&mailbox0_cluster1 &mbox_mai
952 memory-region = <&main_r5fss0_core0_dm
953 <&main_r5fss0_core0_me
954 };
955
956 &main_r5fss0_core1 {
957 mboxes = <&mailbox0_cluster1 &mbox_mai
958 memory-region = <&main_r5fss0_core1_dm
959 <&main_r5fss0_core1_me
960 };
961
962 &main_r5fss1_core0 {
963 mboxes = <&mailbox0_cluster2 &mbox_mai
964 memory-region = <&main_r5fss1_core0_dm
965 <&main_r5fss1_core0_me
966 };
967
968 &main_r5fss1_core1 {
969 mboxes = <&mailbox0_cluster2 &mbox_mai
970 memory-region = <&main_r5fss1_core1_dm
971 <&main_r5fss1_core1_me
972 };
973
974 &c66_0 {
975 status = "okay";
976 mboxes = <&mailbox0_cluster3 &mbox_c66
977 memory-region = <&c66_0_dma_memory_reg
978 <&c66_0_memory_region>
979 };
980
981 &c66_1 {
982 status = "okay";
983 mboxes = <&mailbox0_cluster3 &mbox_c66
984 memory-region = <&c66_1_dma_memory_reg
985 <&c66_1_memory_region>
986 };
987
988 &c71_0 {
989 status = "okay";
990 mboxes = <&mailbox0_cluster4 &mbox_c71
991 memory-region = <&c71_0_dma_memory_reg
992 <&c71_0_memory_region>
993 };
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