1 // SPDX-License-Identifier: GPL-2.0-only OR MI !! 1 // SPDX-License-Identifier: GPL-2.0
2 /* 2 /*
3 * https://beagleboard.org/ai-64 3 * https://beagleboard.org/ai-64
4 * Copyright (C) 2022-2024 Texas Instruments I !! 4 * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
5 * Copyright (C) 2022-2024 Jason Kridner, Beag !! 5 * Copyright (C) 2022 Jason Kridner, BeagleBoard.org Foundation
6 * Copyright (C) 2022-2024 Robert Nelson, Beag !! 6 * Copyright (C) 2022 Robert Nelson, BeagleBoard.org Foundation
7 */ 7 */
8 8
9 /dts-v1/; 9 /dts-v1/;
10 10
11 #include "k3-j721e.dtsi" 11 #include "k3-j721e.dtsi"
12 #include <dt-bindings/gpio/gpio.h> 12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/input/input.h> 13 #include <dt-bindings/input/input.h>
14 #include <dt-bindings/leds/common.h> 14 #include <dt-bindings/leds/common.h>
15 #include <dt-bindings/net/ti-dp83867.h> 15 #include <dt-bindings/net/ti-dp83867.h>
16 #include <dt-bindings/phy/phy-cadence.h> 16 #include <dt-bindings/phy/phy-cadence.h>
17 17
18 / { 18 / {
19 compatible = "beagle,j721e-beaglebonea 19 compatible = "beagle,j721e-beagleboneai64", "ti,j721e";
20 model = "BeagleBoard.org BeagleBone AI 20 model = "BeagleBoard.org BeagleBone AI-64";
21 21
22 aliases { 22 aliases {
23 serial0 = &wkup_uart0; 23 serial0 = &wkup_uart0;
24 serial2 = &main_uart0; 24 serial2 = &main_uart0;
25 mmc0 = &main_sdhci0; 25 mmc0 = &main_sdhci0;
26 mmc1 = &main_sdhci1; 26 mmc1 = &main_sdhci1;
27 i2c0 = &wkup_i2c0; 27 i2c0 = &wkup_i2c0;
28 i2c1 = &main_i2c6; 28 i2c1 = &main_i2c6;
29 i2c2 = &main_i2c2; 29 i2c2 = &main_i2c2;
30 i2c3 = &main_i2c4; 30 i2c3 = &main_i2c4;
31 }; 31 };
32 32
33 chosen { 33 chosen {
34 stdout-path = "serial2:115200n 34 stdout-path = "serial2:115200n8";
35 }; 35 };
36 36
37 memory@80000000 { 37 memory@80000000 {
38 device_type = "memory"; 38 device_type = "memory";
39 /* 4G RAM */ 39 /* 4G RAM */
40 reg = <0x00000000 0x80000000 0 40 reg = <0x00000000 0x80000000 0x00000000 0x80000000>,
41 <0x00000008 0x80000000 0 41 <0x00000008 0x80000000 0x00000000 0x80000000>;
42 }; 42 };
43 43
44 reserved_memory: reserved-memory { 44 reserved_memory: reserved-memory {
45 #address-cells = <2>; 45 #address-cells = <2>;
46 #size-cells = <2>; 46 #size-cells = <2>;
47 ranges; 47 ranges;
48 48
49 secure_ddr: optee@9e800000 { 49 secure_ddr: optee@9e800000 {
50 reg = <0x00 0x9e800000 50 reg = <0x00 0x9e800000 0x00 0x01800000>;
51 no-map; 51 no-map;
52 }; 52 };
53 53
54 mcu_r5fss0_core0_dma_memory_re 54 mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 {
55 compatible = "shared-d 55 compatible = "shared-dma-pool";
56 reg = <0x00 0xa0000000 56 reg = <0x00 0xa0000000 0x00 0x100000>;
57 no-map; 57 no-map;
58 }; 58 };
59 59
60 mcu_r5fss0_core0_memory_region 60 mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 {
61 compatible = "shared-d 61 compatible = "shared-dma-pool";
62 reg = <0x00 0xa0100000 62 reg = <0x00 0xa0100000 0x00 0xf00000>;
63 no-map; 63 no-map;
64 }; 64 };
65 65
66 mcu_r5fss0_core1_dma_memory_re 66 mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 {
67 compatible = "shared-d 67 compatible = "shared-dma-pool";
68 reg = <0x00 0xa1000000 68 reg = <0x00 0xa1000000 0x00 0x100000>;
69 no-map; 69 no-map;
70 }; 70 };
71 71
72 mcu_r5fss0_core1_memory_region 72 mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 {
73 compatible = "shared-d 73 compatible = "shared-dma-pool";
74 reg = <0x00 0xa1100000 74 reg = <0x00 0xa1100000 0x00 0xf00000>;
75 no-map; 75 no-map;
76 }; 76 };
77 77
78 main_r5fss0_core0_dma_memory_r 78 main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a2000000 {
79 compatible = "shared-d 79 compatible = "shared-dma-pool";
80 reg = <0x00 0xa2000000 80 reg = <0x00 0xa2000000 0x00 0x100000>;
81 no-map; 81 no-map;
82 }; 82 };
83 83
84 main_r5fss0_core0_memory_regio 84 main_r5fss0_core0_memory_region: r5f-memory@a2100000 {
85 compatible = "shared-d 85 compatible = "shared-dma-pool";
86 reg = <0x00 0xa2100000 86 reg = <0x00 0xa2100000 0x00 0xf00000>;
87 no-map; 87 no-map;
88 }; 88 };
89 89
90 main_r5fss0_core1_dma_memory_r 90 main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a3000000 {
91 compatible = "shared-d 91 compatible = "shared-dma-pool";
92 reg = <0x00 0xa3000000 92 reg = <0x00 0xa3000000 0x00 0x100000>;
93 no-map; 93 no-map;
94 }; 94 };
95 95
96 main_r5fss0_core1_memory_regio 96 main_r5fss0_core1_memory_region: r5f-memory@a3100000 {
97 compatible = "shared-d 97 compatible = "shared-dma-pool";
98 reg = <0x00 0xa3100000 98 reg = <0x00 0xa3100000 0x00 0xf00000>;
99 no-map; 99 no-map;
100 }; 100 };
101 101
102 main_r5fss1_core0_dma_memory_r 102 main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a4000000 {
103 compatible = "shared-d 103 compatible = "shared-dma-pool";
104 reg = <0x00 0xa4000000 104 reg = <0x00 0xa4000000 0x00 0x100000>;
105 no-map; 105 no-map;
106 }; 106 };
107 107
108 main_r5fss1_core0_memory_regio 108 main_r5fss1_core0_memory_region: r5f-memory@a4100000 {
109 compatible = "shared-d 109 compatible = "shared-dma-pool";
110 reg = <0x00 0xa4100000 110 reg = <0x00 0xa4100000 0x00 0xf00000>;
111 no-map; 111 no-map;
112 }; 112 };
113 113
114 main_r5fss1_core1_dma_memory_r 114 main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a5000000 {
115 compatible = "shared-d 115 compatible = "shared-dma-pool";
116 reg = <0x00 0xa5000000 116 reg = <0x00 0xa5000000 0x00 0x100000>;
117 no-map; 117 no-map;
118 }; 118 };
119 119
120 main_r5fss1_core1_memory_regio 120 main_r5fss1_core1_memory_region: r5f-memory@a5100000 {
121 compatible = "shared-d 121 compatible = "shared-dma-pool";
122 reg = <0x00 0xa5100000 122 reg = <0x00 0xa5100000 0x00 0xf00000>;
123 no-map; 123 no-map;
124 }; 124 };
125 125
126 c66_0_dma_memory_region: c66-d !! 126 c66_1_dma_memory_region: c66-dma-memory@a6000000 {
127 compatible = "shared-d 127 compatible = "shared-dma-pool";
128 reg = <0x00 0xa6000000 128 reg = <0x00 0xa6000000 0x00 0x100000>;
129 no-map; 129 no-map;
130 }; 130 };
131 131
132 c66_0_memory_region: c66-memor 132 c66_0_memory_region: c66-memory@a6100000 {
133 compatible = "shared-d 133 compatible = "shared-dma-pool";
134 reg = <0x00 0xa6100000 134 reg = <0x00 0xa6100000 0x00 0xf00000>;
135 no-map; 135 no-map;
136 }; 136 };
137 137
138 c66_1_dma_memory_region: c66-d !! 138 c66_0_dma_memory_region: c66-dma-memory@a7000000 {
139 compatible = "shared-d 139 compatible = "shared-dma-pool";
140 reg = <0x00 0xa7000000 140 reg = <0x00 0xa7000000 0x00 0x100000>;
141 no-map; 141 no-map;
142 }; 142 };
143 143
144 c66_1_memory_region: c66-memor 144 c66_1_memory_region: c66-memory@a7100000 {
145 compatible = "shared-d 145 compatible = "shared-dma-pool";
146 reg = <0x00 0xa7100000 146 reg = <0x00 0xa7100000 0x00 0xf00000>;
147 no-map; 147 no-map;
148 }; 148 };
149 149
150 c71_0_dma_memory_region: c71-d 150 c71_0_dma_memory_region: c71-dma-memory@a8000000 {
151 compatible = "shared-d 151 compatible = "shared-dma-pool";
152 reg = <0x00 0xa8000000 152 reg = <0x00 0xa8000000 0x00 0x100000>;
153 no-map; 153 no-map;
154 }; 154 };
155 155
156 c71_0_memory_region: c71-memor 156 c71_0_memory_region: c71-memory@a8100000 {
157 compatible = "shared-d 157 compatible = "shared-dma-pool";
158 reg = <0x00 0xa8100000 158 reg = <0x00 0xa8100000 0x00 0xf00000>;
159 no-map; 159 no-map;
160 }; 160 };
161 161
162 rtos_ipc_memory_region: ipc-me 162 rtos_ipc_memory_region: ipc-memories@aa000000 {
163 reg = <0x00 0xaa000000 163 reg = <0x00 0xaa000000 0x00 0x01c00000>;
164 alignment = <0x1000>; 164 alignment = <0x1000>;
165 no-map; 165 no-map;
166 }; 166 };
167 }; 167 };
168 168
169 gpio_keys: gpio-keys { 169 gpio_keys: gpio-keys {
170 compatible = "gpio-keys"; 170 compatible = "gpio-keys";
171 pinctrl-names = "default"; 171 pinctrl-names = "default";
172 pinctrl-0 = <&sw_pwr_pins_defa 172 pinctrl-0 = <&sw_pwr_pins_default>;
173 173
174 button-1 { 174 button-1 {
175 label = "BOOT"; 175 label = "BOOT";
176 linux,code = <BTN_0>; 176 linux,code = <BTN_0>;
177 gpios = <&wkup_gpio0 0 177 gpios = <&wkup_gpio0 0 GPIO_ACTIVE_LOW>;
178 }; 178 };
179 179
180 button-2 { 180 button-2 {
181 label = "POWER"; 181 label = "POWER";
182 linux,code = <KEY_POWE 182 linux,code = <KEY_POWER>;
183 gpios = <&wkup_gpio0 4 183 gpios = <&wkup_gpio0 4 GPIO_ACTIVE_LOW>;
184 }; 184 };
185 }; 185 };
186 186
187 leds { 187 leds {
188 compatible = "gpio-leds"; 188 compatible = "gpio-leds";
189 pinctrl-names = "default"; 189 pinctrl-names = "default";
190 pinctrl-0 = <&led_pins_default 190 pinctrl-0 = <&led_pins_default>;
191 191
192 led-0 { 192 led-0 {
193 gpios = <&main_gpio0 9 193 gpios = <&main_gpio0 96 GPIO_ACTIVE_HIGH>;
194 function = LED_FUNCTIO 194 function = LED_FUNCTION_HEARTBEAT;
195 linux,default-trigger 195 linux,default-trigger = "heartbeat";
196 }; 196 };
197 197
198 led-1 { 198 led-1 {
199 gpios = <&main_gpio0 9 199 gpios = <&main_gpio0 95 GPIO_ACTIVE_HIGH>;
200 function = LED_FUNCTIO 200 function = LED_FUNCTION_DISK_ACTIVITY;
201 linux,default-trigger 201 linux,default-trigger = "mmc0";
202 }; 202 };
203 203
204 led-2 { 204 led-2 {
205 gpios = <&main_gpio0 9 205 gpios = <&main_gpio0 97 GPIO_ACTIVE_HIGH>;
206 function = LED_FUNCTIO 206 function = LED_FUNCTION_CPU;
207 linux,default-trigger 207 linux,default-trigger = "cpu";
208 }; 208 };
209 209
210 led-3 { 210 led-3 {
211 gpios = <&main_gpio0 1 211 gpios = <&main_gpio0 110 GPIO_ACTIVE_HIGH>;
212 function = LED_FUNCTIO 212 function = LED_FUNCTION_DISK_ACTIVITY;
213 linux,default-trigger 213 linux,default-trigger = "mmc1";
214 }; 214 };
215 215
216 led-4 { 216 led-4 {
217 gpios = <&main_gpio0 1 217 gpios = <&main_gpio0 109 GPIO_ACTIVE_HIGH>;
218 function = LED_FUNCTIO 218 function = LED_FUNCTION_WLAN;
219 default-state = "off"; 219 default-state = "off";
220 }; 220 };
221 }; 221 };
222 222
223 evm_12v0: regulator-0 { 223 evm_12v0: regulator-0 {
224 /* main supply */ 224 /* main supply */
225 compatible = "regulator-fixed" 225 compatible = "regulator-fixed";
226 regulator-name = "evm_12v0"; 226 regulator-name = "evm_12v0";
227 regulator-min-microvolt = <120 227 regulator-min-microvolt = <12000000>;
228 regulator-max-microvolt = <120 228 regulator-max-microvolt = <12000000>;
229 regulator-always-on; 229 regulator-always-on;
230 regulator-boot-on; 230 regulator-boot-on;
231 }; 231 };
232 232
233 vsys_3v3: regulator-1 { 233 vsys_3v3: regulator-1 {
234 /* Output of LMS140 */ 234 /* Output of LMS140 */
235 compatible = "regulator-fixed" 235 compatible = "regulator-fixed";
236 regulator-name = "vsys_3v3"; 236 regulator-name = "vsys_3v3";
237 regulator-min-microvolt = <330 237 regulator-min-microvolt = <3300000>;
238 regulator-max-microvolt = <330 238 regulator-max-microvolt = <3300000>;
239 vin-supply = <&evm_12v0>; 239 vin-supply = <&evm_12v0>;
240 regulator-always-on; 240 regulator-always-on;
241 regulator-boot-on; 241 regulator-boot-on;
242 }; 242 };
243 243
244 vsys_5v0: regulator-2 { 244 vsys_5v0: regulator-2 {
245 /* Output of LM5140 */ 245 /* Output of LM5140 */
246 compatible = "regulator-fixed" 246 compatible = "regulator-fixed";
247 regulator-name = "vsys_5v0"; 247 regulator-name = "vsys_5v0";
248 regulator-min-microvolt = <500 248 regulator-min-microvolt = <5000000>;
249 regulator-max-microvolt = <500 249 regulator-max-microvolt = <5000000>;
250 vin-supply = <&evm_12v0>; 250 vin-supply = <&evm_12v0>;
251 regulator-always-on; 251 regulator-always-on;
252 regulator-boot-on; 252 regulator-boot-on;
253 }; 253 };
254 254
255 vdd_mmc1: regulator-3 { 255 vdd_mmc1: regulator-3 {
256 compatible = "regulator-fixed" 256 compatible = "regulator-fixed";
257 pinctrl-names = "default"; 257 pinctrl-names = "default";
258 pinctrl-0 = <&sd_pwr_en_pins_d 258 pinctrl-0 = <&sd_pwr_en_pins_default>;
259 regulator-name = "vdd_mmc1"; 259 regulator-name = "vdd_mmc1";
260 regulator-min-microvolt = <330 260 regulator-min-microvolt = <3300000>;
261 regulator-max-microvolt = <330 261 regulator-max-microvolt = <3300000>;
262 regulator-boot-on; 262 regulator-boot-on;
263 enable-active-high; 263 enable-active-high;
264 vin-supply = <&vsys_3v3>; 264 vin-supply = <&vsys_3v3>;
265 gpio = <&main_gpio0 82 GPIO_AC 265 gpio = <&main_gpio0 82 GPIO_ACTIVE_HIGH>;
266 }; 266 };
267 267
268 vdd_sd_dv_alt: regulator-4 { 268 vdd_sd_dv_alt: regulator-4 {
269 compatible = "regulator-gpio"; 269 compatible = "regulator-gpio";
270 pinctrl-names = "default"; 270 pinctrl-names = "default";
271 pinctrl-0 = <&vdd_sd_dv_alt_pi 271 pinctrl-0 = <&vdd_sd_dv_alt_pins_default>;
272 regulator-name = "tlv71033"; 272 regulator-name = "tlv71033";
273 regulator-min-microvolt = <180 273 regulator-min-microvolt = <1800000>;
274 regulator-max-microvolt = <330 274 regulator-max-microvolt = <3300000>;
275 regulator-boot-on; 275 regulator-boot-on;
276 vin-supply = <&vsys_5v0>; 276 vin-supply = <&vsys_5v0>;
277 gpios = <&main_gpio0 117 GPIO_ 277 gpios = <&main_gpio0 117 GPIO_ACTIVE_HIGH>;
278 states = <1800000 0x0>, 278 states = <1800000 0x0>,
279 <3300000 0x1>; 279 <3300000 0x1>;
280 }; 280 };
281 281
282 dp_pwr_3v3: regulator-5 { 282 dp_pwr_3v3: regulator-5 {
283 compatible = "regulator-fixed" 283 compatible = "regulator-fixed";
284 pinctrl-names = "default"; 284 pinctrl-names = "default";
285 pinctrl-0 = <&dp0_3v3_en_pins_ 285 pinctrl-0 = <&dp0_3v3_en_pins_default>;
286 regulator-name = "dp-pwr"; 286 regulator-name = "dp-pwr";
287 regulator-min-microvolt = <330 287 regulator-min-microvolt = <3300000>;
288 regulator-max-microvolt = <330 288 regulator-max-microvolt = <3300000>;
289 gpio = <&main_gpio0 49 GPIO_AC 289 gpio = <&main_gpio0 49 GPIO_ACTIVE_HIGH>; /* DP0_PWR_SW_EN */
290 enable-active-high; 290 enable-active-high;
291 }; 291 };
292 292
293 dp0: connector { 293 dp0: connector {
294 compatible = "dp-connector"; 294 compatible = "dp-connector";
295 label = "DP0"; 295 label = "DP0";
296 type = "full-size"; 296 type = "full-size";
297 dp-pwr-supply = <&dp_pwr_3v3>; 297 dp-pwr-supply = <&dp_pwr_3v3>;
298 298
299 port { 299 port {
300 dp_connector_in: endpo 300 dp_connector_in: endpoint {
301 remote-endpoin 301 remote-endpoint = <&dp0_out>;
302 }; 302 };
303 }; 303 };
304 }; 304 };
305 }; 305 };
306 306
307 &main_pmx0 { 307 &main_pmx0 {
308 led_pins_default: led-default-pins { 308 led_pins_default: led-default-pins {
309 pinctrl-single,pins = < 309 pinctrl-single,pins = <
310 J721E_IOPAD(0x184, PIN 310 J721E_IOPAD(0x184, PIN_INPUT, 7) /* (T23) RGMII5_RD0.GPIO0_96 */
311 J721E_IOPAD(0x180, PIN 311 J721E_IOPAD(0x180, PIN_INPUT, 7) /* (R23) RGMII5_RD1.GPIO0_95 */
312 J721E_IOPAD(0x188, PIN 312 J721E_IOPAD(0x188, PIN_INPUT, 7) /* (Y28) RGMII6_TX_CTL.GPIO0_97 */
313 J721E_IOPAD(0x1bc, PIN 313 J721E_IOPAD(0x1bc, PIN_INPUT, 7) /* (V24) MDIO0_MDC.GPIO0_110 */
314 J721E_IOPAD(0x1b8, PIN 314 J721E_IOPAD(0x1b8, PIN_INPUT, 7) /* (V26) MDIO0_MDIO.GPIO0_109 */
315 >; 315 >;
316 }; 316 };
317 317
318 main_mmc1_pins_default: main-mmc1-defa 318 main_mmc1_pins_default: main-mmc1-default-pins {
319 pinctrl-single,pins = < 319 pinctrl-single,pins = <
320 J721E_IOPAD(0x254, PIN 320 J721E_IOPAD(0x254, PIN_INPUT, 0) /* (R29) MMC1_CMD */
321 J721E_IOPAD(0x250, PIN 321 J721E_IOPAD(0x250, PIN_INPUT, 0) /* (P25) MMC1_CLK */
322 J721E_IOPAD(0x2ac, PIN 322 J721E_IOPAD(0x2ac, PIN_INPUT, 0) /* (P25) MMC1_CLKLB */
323 J721E_IOPAD(0x24c, PIN 323 J721E_IOPAD(0x24c, PIN_INPUT, 0) /* (R24) MMC1_DAT0 */
324 J721E_IOPAD(0x248, PIN 324 J721E_IOPAD(0x248, PIN_INPUT, 0) /* (P24) MMC1_DAT1 */
325 J721E_IOPAD(0x244, PIN 325 J721E_IOPAD(0x244, PIN_INPUT, 0) /* (R25) MMC1_DAT2 */
326 J721E_IOPAD(0x240, PIN 326 J721E_IOPAD(0x240, PIN_INPUT, 0) /* (R26) MMC1_DAT3 */
327 J721E_IOPAD(0x258, PIN 327 J721E_IOPAD(0x258, PIN_INPUT, 0) /* (P23) MMC1_SDCD */
328 >; 328 >;
329 }; 329 };
330 330
331 main_uart0_pins_default: main-uart0-de 331 main_uart0_pins_default: main-uart0-default-pins {
332 pinctrl-single,pins = < 332 pinctrl-single,pins = <
333 J721E_IOPAD(0x1e8, PIN 333 J721E_IOPAD(0x1e8, PIN_INPUT, 0) /* (AB2) UART0_RXD */
334 J721E_IOPAD(0x1ec, PIN 334 J721E_IOPAD(0x1ec, PIN_OUTPUT, 0) /* (AB3) UART0_TXD */
335 >; 335 >;
336 }; 336 };
337 337
338 sd_pwr_en_pins_default: sd-pwr-en-defa 338 sd_pwr_en_pins_default: sd-pwr-en-default-pins {
339 pinctrl-single,pins = < 339 pinctrl-single,pins = <
340 J721E_IOPAD(0x14c, PIN 340 J721E_IOPAD(0x14c, PIN_INPUT, 7) /* (AA29) PRG0_PRU1_GPO19.GPIO0_82 */
341 >; 341 >;
342 }; 342 };
343 343
344 vdd_sd_dv_alt_pins_default: vdd-sd-dv- 344 vdd_sd_dv_alt_pins_default: vdd-sd-dv-alt-default-pins {
345 pinctrl-single,pins = < 345 pinctrl-single,pins = <
346 J721E_IOPAD(0x1d8, PIN 346 J721E_IOPAD(0x1d8, PIN_INPUT, 7) /* (W4) SPI1_CS1.GPIO0_117 */
347 >; 347 >;
348 }; 348 };
349 349
350 main_usbss0_pins_default: main-usbss0- 350 main_usbss0_pins_default: main-usbss0-default-pins {
351 pinctrl-single,pins = < 351 pinctrl-single,pins = <
352 J721E_IOPAD(0x210, PIN 352 J721E_IOPAD(0x210, PIN_INPUT, 7) /* (W3) MCAN1_RX.GPIO1_3 - USBC_DIR */
353 >; 353 >;
354 }; 354 };
355 355
356 main_usbss1_pins_default: main-usbss1- 356 main_usbss1_pins_default: main-usbss1-default-pins {
357 pinctrl-single,pins = < 357 pinctrl-single,pins = <
358 J721E_IOPAD(0x290, INP 358 J721E_IOPAD(0x290, INPUT_DISABLE, 1) /* (U6) USB0_DRVVBUS.USB1_DRVVBUS */
359 >; 359 >;
360 }; 360 };
361 361
362 dp0_3v3_en_pins_default:dp0-3v3-en-def 362 dp0_3v3_en_pins_default:dp0-3v3-en-default-pins {
363 pinctrl-single,pins = < 363 pinctrl-single,pins = <
364 J721E_IOPAD(0xc8, PIN_ 364 J721E_IOPAD(0xc8, PIN_INPUT, 7) /* (AE26) PRG0_PRU0_GPO6.GPIO0_49 */
365 >; 365 >;
366 }; 366 };
367 367
368 dp0_pins_default: dp0-default-pins { 368 dp0_pins_default: dp0-default-pins {
369 pinctrl-single,pins = < 369 pinctrl-single,pins = <
370 J721E_IOPAD(0x1c4, PIN 370 J721E_IOPAD(0x1c4, PIN_INPUT, 5) /* (Y4) SPI0_CS1.DP0_HPD */
371 >; 371 >;
372 }; 372 };
373 373
374 main_i2c0_pins_default: main-i2c0-defa 374 main_i2c0_pins_default: main-i2c0-default-pins {
375 pinctrl-single,pins = < 375 pinctrl-single,pins = <
376 J721E_IOPAD(0x220, PIN 376 J721E_IOPAD(0x220, PIN_INPUT_PULLUP, 0) /* (AC5) I2C0_SCL */
377 J721E_IOPAD(0x224, PIN 377 J721E_IOPAD(0x224, PIN_INPUT_PULLUP, 0) /* (AA5) I2C0_SDA */
378 >; 378 >;
379 }; 379 };
380 380
381 main_i2c1_pins_default: main-i2c1-defa 381 main_i2c1_pins_default: main-i2c1-default-pins {
382 pinctrl-single,pins = < 382 pinctrl-single,pins = <
383 J721E_IOPAD(0x228, PIN 383 J721E_IOPAD(0x228, PIN_INPUT_PULLUP, 0) /* (Y6) I2C1_SCL */
384 J721E_IOPAD(0x22c, PIN 384 J721E_IOPAD(0x22c, PIN_INPUT_PULLUP, 0) /* (AA6) I2C1_SDA */
385 >; 385 >;
386 }; 386 };
387 387
388 main_i2c2_pins_default: main-i2c2-defa 388 main_i2c2_pins_default: main-i2c2-default-pins {
389 pinctrl-single,pins = < 389 pinctrl-single,pins = <
390 J721E_IOPAD(0x208, PIN 390 J721E_IOPAD(0x208, PIN_INPUT_PULLUP, 4) /* (W5) MCAN0_RX.I2C2_SCL */
391 J721E_IOPAD(0x20c, PIN 391 J721E_IOPAD(0x20c, PIN_INPUT_PULLUP, 4) /* (W6) MCAN0_TX.I2C2_SDA */
392 J721E_IOPAD(0x138, PIN 392 J721E_IOPAD(0x138, PIN_INPUT, 7) /* (AE25) PRG0_PRU1_GPO14.GPIO0_77 */
393 J721E_IOPAD(0x13c, PIN 393 J721E_IOPAD(0x13c, PIN_INPUT, 7) /* (AF29) PRG0_PRU1_GPO15.GPIO0_78 */
394 >; 394 >;
395 }; 395 };
396 396
397 main_i2c3_pins_default: main-i2c3-defa 397 main_i2c3_pins_default: main-i2c3-default-pins {
398 pinctrl-single,pins = < 398 pinctrl-single,pins = <
399 J721E_IOPAD(0x270, PIN 399 J721E_IOPAD(0x270, PIN_INPUT_PULLUP, 4) /* (T26) MMC2_CLK.I2C3_SCL */
400 J721E_IOPAD(0x274, PIN 400 J721E_IOPAD(0x274, PIN_INPUT_PULLUP, 4) /* (T25) MMC2_CMD.I2C3_SDA */
401 >; 401 >;
402 }; 402 };
403 403
404 main_i2c4_pins_default: main-i2c4-defa 404 main_i2c4_pins_default: main-i2c4-default-pins {
405 pinctrl-single,pins = < 405 pinctrl-single,pins = <
406 J721E_IOPAD(0x1e0, PIN 406 J721E_IOPAD(0x1e0, PIN_INPUT_PULLUP, 2) /* (Y5) SPI1_D0.I2C4_SCL */
407 J721E_IOPAD(0x1dc, PIN 407 J721E_IOPAD(0x1dc, PIN_INPUT_PULLUP, 2) /* (Y1) SPI1_CLK.I2C4_SDA */
408 J721E_IOPAD(0x30, PIN_ 408 J721E_IOPAD(0x30, PIN_INPUT, 7) /* (AF24) PRG1_PRU0_GPO11.GPIO0_12 */
409 J721E_IOPAD(0x34, PIN_ 409 J721E_IOPAD(0x34, PIN_INPUT, 7) /* (AJ24) PRG1_PRU0_GPO12.GPIO0_13 */
410 >; 410 >;
411 }; 411 };
412 412
413 main_i2c5_pins_default: main-i2c5-defa 413 main_i2c5_pins_default: main-i2c5-default-pins {
414 pinctrl-single,pins = < 414 pinctrl-single,pins = <
415 J721E_IOPAD(0x150, PIN 415 J721E_IOPAD(0x150, PIN_INPUT_PULLUP, 2) /* (Y26) PRG0_MDIO0_MDIO.I2C5_SCL */
416 J721E_IOPAD(0x154, PIN 416 J721E_IOPAD(0x154, PIN_INPUT_PULLUP, 2) /* (AA27) PRG0_MDIO0_MDC.I2C5_SDA */
417 >; 417 >;
418 }; 418 };
419 419
420 main_i2c6_pins_default: main-i2c6-defa 420 main_i2c6_pins_default: main-i2c6-default-pins {
421 pinctrl-single,pins = < 421 pinctrl-single,pins = <
422 J721E_IOPAD(0x1d0, PIN 422 J721E_IOPAD(0x1d0, PIN_INPUT_PULLUP, 2) /* (AA3) SPI0_D1.I2C6_SCL */
423 J721E_IOPAD(0x1e4, PIN 423 J721E_IOPAD(0x1e4, PIN_INPUT_PULLUP, 2) /* (Y2) SPI1_D1.I2C6_SDA */
424 J721E_IOPAD(0x74, PIN_ 424 J721E_IOPAD(0x74, PIN_INPUT, 7) /* (AC21) PRG1_PRU1_GPO7.GPIO0_28 */
425 J721E_IOPAD(0xa4, PIN_ 425 J721E_IOPAD(0xa4, PIN_INPUT, 7) /* (AH22) PRG1_PRU1_GPO19.GPIO0_40 */
426 >; 426 >;
427 }; 427 };
428 428
429 csi0_gpio_pins_default: csi0-gpio-defa 429 csi0_gpio_pins_default: csi0-gpio-default-pins {
430 pinctrl-single,pins = < 430 pinctrl-single,pins = <
431 J721E_IOPAD(0x19c, PIN 431 J721E_IOPAD(0x19c, PIN_INPUT_PULLDOWN, 7) /* (W27) RGMII6_TD0.GPIO0_102 */
432 J721E_IOPAD(0x1a0, PIN 432 J721E_IOPAD(0x1a0, PIN_INPUT_PULLDOWN, 7) /* (W29) RGMII6_TXC.GPIO0_103 */
433 >; 433 >;
434 }; 434 };
435 435
436 csi1_gpio_pins_default: csi1-gpio-defa 436 csi1_gpio_pins_default: csi1-gpio-default-pins {
437 pinctrl-single,pins = < 437 pinctrl-single,pins = <
438 J721E_IOPAD(0x198, PIN 438 J721E_IOPAD(0x198, PIN_INPUT_PULLDOWN, 7) /* (V25) RGMII6_TD1.GPIO0_101 */
439 J721E_IOPAD(0x1b0, PIN 439 J721E_IOPAD(0x1b0, PIN_INPUT_PULLDOWN, 7) /* (W24) RGMII6_RD1.GPIO0_107 */
440 >; 440 >;
441 }; 441 };
442 442
443 pcie1_rst_pins_default: pcie1-rst-defa 443 pcie1_rst_pins_default: pcie1-rst-default-pins {
444 pinctrl-single,pins = < 444 pinctrl-single,pins = <
445 J721E_IOPAD(0x5c, PIN_ 445 J721E_IOPAD(0x5c, PIN_INPUT, 7) /* (AG23) PRG1_PRU1_GPO1.GPIO0_22 */
446 >; 446 >;
447 }; 447 };
448 }; 448 };
449 449
450 &wkup_pmx0 { 450 &wkup_pmx0 {
451 eeprom_wp_pins_default: eeprom-wp-defa 451 eeprom_wp_pins_default: eeprom-wp-default-pins {
452 pinctrl-single,pins = < 452 pinctrl-single,pins = <
453 J721E_WKUP_IOPAD(0xc4, 453 J721E_WKUP_IOPAD(0xc4, PIN_OUTPUT_PULLUP, 7) /* (G24) WKUP_GPIO0_5 */
454 >; 454 >;
455 }; 455 };
456 456
457 mcu_adc0_pins_default: mcu-adc0-defaul 457 mcu_adc0_pins_default: mcu-adc0-default-pins {
458 pinctrl-single,pins = < 458 pinctrl-single,pins = <
459 J721E_WKUP_IOPAD(0x130 459 J721E_WKUP_IOPAD(0x130, PIN_INPUT, 0) /* (K25) MCU_ADC0_AIN0 */
460 J721E_WKUP_IOPAD(0x134 460 J721E_WKUP_IOPAD(0x134, PIN_INPUT, 0) /* (K26) MCU_ADC0_AIN1 */
461 J721E_WKUP_IOPAD(0x138 461 J721E_WKUP_IOPAD(0x138, PIN_INPUT, 0) /* (K28) MCU_ADC0_AIN2 */
462 J721E_WKUP_IOPAD(0x13c 462 J721E_WKUP_IOPAD(0x13c, PIN_INPUT, 0) /* (L28) MCU_ADC0_AIN3 */
463 J721E_WKUP_IOPAD(0x140 463 J721E_WKUP_IOPAD(0x140, PIN_INPUT, 0) /* (K24) MCU_ADC0_AIN4 */
464 J721E_WKUP_IOPAD(0x144 464 J721E_WKUP_IOPAD(0x144, PIN_INPUT, 0) /* (K27) MCU_ADC0_AIN5 */
465 J721E_WKUP_IOPAD(0x148 465 J721E_WKUP_IOPAD(0x148, PIN_INPUT, 0) /* (K29) MCU_ADC0_AIN6 */
466 >; 466 >;
467 }; 467 };
468 468
469 mcu_adc1_pins_default: mcu-adc1-defaul 469 mcu_adc1_pins_default: mcu-adc1-default-pins {
470 pinctrl-single,pins = < 470 pinctrl-single,pins = <
471 J721E_WKUP_IOPAD(0x150 471 J721E_WKUP_IOPAD(0x150, PIN_INPUT, 0) /* (N23) MCU_ADC1_AIN0 */
472 >; 472 >;
473 }; 473 };
474 474
475 mikro_bus_pins_default: mikro-bus-defa 475 mikro_bus_pins_default: mikro-bus-default-pins {
476 pinctrl-single,pins = < 476 pinctrl-single,pins = <
477 J721E_WKUP_IOPAD(0x108 477 J721E_WKUP_IOPAD(0x108, PIN_INPUT, 7) /* SDAPULLEN (E26) PMIC_POWER_EN0.WKUP_GPIO0_66 */
478 J721E_WKUP_IOPAD(0xd4, 478 J721E_WKUP_IOPAD(0xd4, PIN_INPUT, 7) /* SDA (G26) WKUP_GPIO0_9.MCU_I2C1_SDA */
479 J721E_WKUP_IOPAD(0xf4, 479 J721E_WKUP_IOPAD(0xf4, PIN_INPUT, 7) /* SDA (D25) MCU_I3C0_SDA.WKUP_GPIO0_61 */
480 J721E_WKUP_IOPAD(0xd0, 480 J721E_WKUP_IOPAD(0xd0, PIN_INPUT, 7) /* SCL (G27) WKUP_GPIO0_8.MCU_I2C1_SCL */
481 J721E_WKUP_IOPAD(0xf0, 481 J721E_WKUP_IOPAD(0xf0, PIN_INPUT, 7) /* SCL (D26) MCU_I3C0_SCL.WKUP_GPIO0_60 */
482 482
483 J721E_WKUP_IOPAD(0xb8, 483 J721E_WKUP_IOPAD(0xb8, PIN_INPUT, 7) /* MOSI (F28) WKUP_GPIO0_2.MCU_SPI1_D1 */
484 J721E_WKUP_IOPAD(0xb4, 484 J721E_WKUP_IOPAD(0xb4, PIN_INPUT, 7) /* MISO (F25) WKUP_GPIO0_1.MCU_SPI1_D0 */
485 J721E_WKUP_IOPAD(0xb0, 485 J721E_WKUP_IOPAD(0xb0, PIN_INPUT, 7) /* CLK (F26) WKUP_GPIO0_0.MCU_SPI1_CLK */
486 J721E_WKUP_IOPAD(0xbc, 486 J721E_WKUP_IOPAD(0xbc, PIN_INPUT, 7) /* CS (F27) WKUP_GPIO0_3.MCU_SPI1_CS0 */
487 487
488 J721E_WKUP_IOPAD(0x44, 488 J721E_WKUP_IOPAD(0x44, PIN_INPUT, 7) /* RX (G22) MCU_OSPI1_D1.WKUP_GPIO0_33 */
489 J721E_WKUP_IOPAD(0x48, 489 J721E_WKUP_IOPAD(0x48, PIN_INPUT, 7) /* TX (D23) MCU_OSPI1_D2.WKUP_GPIO0_34 */
490 490
491 J721E_WKUP_IOPAD(0x4c, 491 J721E_WKUP_IOPAD(0x4c, PIN_INPUT, 7) /* INT (C23) MCU_OSPI1_D3.WKUP_GPIO0_35 */
492 J721E_WKUP_IOPAD(0x54, 492 J721E_WKUP_IOPAD(0x54, PIN_INPUT, 7) /* RST (E22) MCU_OSPI1_CSn1.WKUP_GPIO0_37 */
493 J721E_WKUP_IOPAD(0xdc, 493 J721E_WKUP_IOPAD(0xdc, PIN_INPUT, 7) /* PWM (H27) WKUP_GPIO0_11 */
494 J721E_WKUP_IOPAD(0xac, 494 J721E_WKUP_IOPAD(0xac, PIN_INPUT, 7) /* AN (C29) MCU_MCAN0_RX.WKUP_GPIO0_59 */
495 >; 495 >;
496 }; 496 };
497 497
498 mcu_cpsw_pins_default: mcu-cpsw-defaul 498 mcu_cpsw_pins_default: mcu-cpsw-default-pins {
499 pinctrl-single,pins = < 499 pinctrl-single,pins = <
500 J721E_WKUP_IOPAD(0x84, 500 J721E_WKUP_IOPAD(0x84, PIN_INPUT, 0) /* (B24) MCU_RGMII1_RD0 */
501 J721E_WKUP_IOPAD(0x80, 501 J721E_WKUP_IOPAD(0x80, PIN_INPUT, 0) /* (A24) MCU_RGMII1_RD1 */
502 J721E_WKUP_IOPAD(0x7c, 502 J721E_WKUP_IOPAD(0x7c, PIN_INPUT, 0) /* (D24) MCU_RGMII1_RD2 */
503 J721E_WKUP_IOPAD(0x78, 503 J721E_WKUP_IOPAD(0x78, PIN_INPUT, 0) /* (A25) MCU_RGMII1_RD3 */
504 J721E_WKUP_IOPAD(0x74, 504 J721E_WKUP_IOPAD(0x74, PIN_INPUT, 0) /* (C24) MCU_RGMII1_RXC */
505 J721E_WKUP_IOPAD(0x5c, 505 J721E_WKUP_IOPAD(0x5c, PIN_INPUT, 0) /* (C25) MCU_RGMII1_RX_CTL */
506 J721E_WKUP_IOPAD(0x6c, 506 J721E_WKUP_IOPAD(0x6c, PIN_OUTPUT, 0) /* (B25) MCU_RGMII1_TD0 */
507 J721E_WKUP_IOPAD(0x68, 507 J721E_WKUP_IOPAD(0x68, PIN_OUTPUT, 0) /* (A26) MCU_RGMII1_TD1 */
508 J721E_WKUP_IOPAD(0x64, 508 J721E_WKUP_IOPAD(0x64, PIN_OUTPUT, 0) /* (A27) MCU_RGMII1_TD2 */
509 J721E_WKUP_IOPAD(0x60, 509 J721E_WKUP_IOPAD(0x60, PIN_OUTPUT, 0) /* (A28) MCU_RGMII1_TD3 */
510 J721E_WKUP_IOPAD(0x70, 510 J721E_WKUP_IOPAD(0x70, PIN_OUTPUT, 0) /* (B26) MCU_RGMII1_TXC */
511 J721E_WKUP_IOPAD(0x58, 511 J721E_WKUP_IOPAD(0x58, PIN_OUTPUT, 0) /* (B27) MCU_RGMII1_TX_CTL */
512 >; 512 >;
513 }; 513 };
514 514
515 mcu_mdio_pins_default: mcu-mdio1-defau 515 mcu_mdio_pins_default: mcu-mdio1-default-pins {
516 pinctrl-single,pins = < 516 pinctrl-single,pins = <
517 J721E_WKUP_IOPAD(0x8c, 517 J721E_WKUP_IOPAD(0x8c, PIN_OUTPUT, 0) /* (F23) MCU_MDIO0_MDC */
518 J721E_WKUP_IOPAD(0x88, 518 J721E_WKUP_IOPAD(0x88, PIN_INPUT, 0) /* (E23) MCU_MDIO0_MDIO */
519 >; 519 >;
520 }; 520 };
521 521
522 sw_pwr_pins_default: sw-pwr-default-pi 522 sw_pwr_pins_default: sw-pwr-default-pins {
523 pinctrl-single,pins = < 523 pinctrl-single,pins = <
524 J721E_WKUP_IOPAD(0xc0, 524 J721E_WKUP_IOPAD(0xc0, PIN_INPUT, 7) /* (G25) WKUP_GPIO0_4 */
525 >; 525 >;
526 }; 526 };
527 527
528 wkup_i2c0_pins_default: wkup-i2c0-defa 528 wkup_i2c0_pins_default: wkup-i2c0-default-pins {
529 pinctrl-single,pins = < 529 pinctrl-single,pins = <
530 J721E_WKUP_IOPAD(0xf8, 530 J721E_WKUP_IOPAD(0xf8, PIN_INPUT_PULLUP, 0) /* (J25) WKUP_I2C0_SCL */
531 J721E_WKUP_IOPAD(0xfc, 531 J721E_WKUP_IOPAD(0xfc, PIN_INPUT_PULLUP, 0) /* (H24) WKUP_I2C0_SDA */
532 >; 532 >;
533 }; 533 };
534 534
535 wkup_uart0_pins_default: wkup-uart0-de 535 wkup_uart0_pins_default: wkup-uart0-default-pins {
536 pinctrl-single,pins = < 536 pinctrl-single,pins = <
537 J721E_WKUP_IOPAD(0xa0, 537 J721E_WKUP_IOPAD(0xa0, PIN_INPUT, 0) /* (J29) WKUP_UART0_RXD */
538 J721E_WKUP_IOPAD(0xa4, 538 J721E_WKUP_IOPAD(0xa4, PIN_OUTPUT, 0) /* (J28) WKUP_UART0_TXD */
539 >; 539 >;
540 }; 540 };
541 541
542 mcu_usbss1_pins_default: mcu-usbss1-de 542 mcu_usbss1_pins_default: mcu-usbss1-default-pins {
543 pinctrl-single,pins = < 543 pinctrl-single,pins = <
544 J721E_WKUP_IOPAD(0x3c, 544 J721E_WKUP_IOPAD(0x3c, PIN_OUTPUT_PULLUP, 5) /* (A23) MCU_OSPI1_LBCLKO.WKUP_GPIO0_30 */
545 >; 545 >;
546 }; 546 };
547 }; 547 };
548 548
549 &wkup_uart0 { 549 &wkup_uart0 {
550 /* Wakeup UART is used by TIFS firmwar 550 /* Wakeup UART is used by TIFS firmware. */
551 status = "reserved"; 551 status = "reserved";
552 pinctrl-names = "default"; 552 pinctrl-names = "default";
553 pinctrl-0 = <&wkup_uart0_pins_default> 553 pinctrl-0 = <&wkup_uart0_pins_default>;
554 }; 554 };
555 555
556 &main_uart0 { 556 &main_uart0 {
557 status = "okay"; 557 status = "okay";
558 pinctrl-names = "default"; 558 pinctrl-names = "default";
559 pinctrl-0 = <&main_uart0_pins_default> 559 pinctrl-0 = <&main_uart0_pins_default>;
560 /* Shared with ATF on this platform */ 560 /* Shared with ATF on this platform */
561 power-domains = <&k3_pds 146 TI_SCI_PD 561 power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>;
562 }; 562 };
563 563
564 &main_sdhci0 { 564 &main_sdhci0 {
565 /* eMMC */ 565 /* eMMC */
566 status = "okay"; 566 status = "okay";
567 non-removable; 567 non-removable;
568 ti,driver-strength-ohm = <50>; 568 ti,driver-strength-ohm = <50>;
569 disable-wp; 569 disable-wp;
570 }; 570 };
571 571
572 &main_sdhci1 { 572 &main_sdhci1 {
573 /* SD Card */ 573 /* SD Card */
574 status = "okay"; 574 status = "okay";
575 vmmc-supply = <&vdd_mmc1>; 575 vmmc-supply = <&vdd_mmc1>;
576 vqmmc-supply = <&vdd_sd_dv_alt>; 576 vqmmc-supply = <&vdd_sd_dv_alt>;
577 pinctrl-names = "default"; 577 pinctrl-names = "default";
578 pinctrl-0 = <&main_mmc1_pins_default>; 578 pinctrl-0 = <&main_mmc1_pins_default>;
579 ti,driver-strength-ohm = <50>; 579 ti,driver-strength-ohm = <50>;
580 disable-wp; 580 disable-wp;
581 }; 581 };
582 582
583 &main_i2c0 { 583 &main_i2c0 {
584 status = "okay"; 584 status = "okay";
585 pinctrl-names = "default"; 585 pinctrl-names = "default";
586 pinctrl-0 = <&main_i2c0_pins_default>; 586 pinctrl-0 = <&main_i2c0_pins_default>;
587 clock-frequency = <400000>; 587 clock-frequency = <400000>;
588 }; 588 };
589 589
590 &main_i2c1 { 590 &main_i2c1 {
591 status = "okay"; 591 status = "okay";
592 pinctrl-names = "default"; 592 pinctrl-names = "default";
593 pinctrl-0 = <&main_i2c1_pins_default>; 593 pinctrl-0 = <&main_i2c1_pins_default>;
594 clock-frequency = <400000>; 594 clock-frequency = <400000>;
595 }; 595 };
596 596
597 &main_i2c2 { 597 &main_i2c2 {
598 /* BBB Header: P9.19 and P9.20 */ 598 /* BBB Header: P9.19 and P9.20 */
599 status = "okay"; 599 status = "okay";
600 pinctrl-names = "default"; 600 pinctrl-names = "default";
601 pinctrl-0 = <&main_i2c2_pins_default>; 601 pinctrl-0 = <&main_i2c2_pins_default>;
602 clock-frequency = <100000>; 602 clock-frequency = <100000>;
603 }; 603 };
604 604
605 &main_i2c3 { 605 &main_i2c3 {
606 status = "okay"; 606 status = "okay";
607 pinctrl-names = "default"; 607 pinctrl-names = "default";
608 pinctrl-0 = <&main_i2c3_pins_default>; 608 pinctrl-0 = <&main_i2c3_pins_default>;
609 clock-frequency = <400000>; 609 clock-frequency = <400000>;
610 }; 610 };
611 611
612 &main_i2c4 { 612 &main_i2c4 {
613 /* BBB Header: P9.24 and P9.26 */ 613 /* BBB Header: P9.24 and P9.26 */
614 status = "okay"; 614 status = "okay";
615 pinctrl-names = "default"; 615 pinctrl-names = "default";
616 pinctrl-0 = <&main_i2c4_pins_default>; 616 pinctrl-0 = <&main_i2c4_pins_default>;
617 clock-frequency = <100000>; 617 clock-frequency = <100000>;
618 }; 618 };
619 619
620 &main_i2c5 { 620 &main_i2c5 {
621 status = "okay"; 621 status = "okay";
622 pinctrl-names = "default"; 622 pinctrl-names = "default";
623 pinctrl-0 = <&main_i2c5_pins_default>; 623 pinctrl-0 = <&main_i2c5_pins_default>;
624 clock-frequency = <400000>; 624 clock-frequency = <400000>;
625 }; 625 };
626 626
627 &main_i2c6 { 627 &main_i2c6 {
628 /* BBB Header: P9.17 and P9.18 */ 628 /* BBB Header: P9.17 and P9.18 */
629 status = "okay"; 629 status = "okay";
630 pinctrl-names = "default"; 630 pinctrl-names = "default";
631 pinctrl-0 = <&main_i2c6_pins_default>; 631 pinctrl-0 = <&main_i2c6_pins_default>;
632 clock-frequency = <100000>; 632 clock-frequency = <100000>;
633 status = "okay"; 633 status = "okay";
634 }; 634 };
635 635
636 &wkup_i2c0 { 636 &wkup_i2c0 {
637 status = "okay"; 637 status = "okay";
638 pinctrl-names = "default"; 638 pinctrl-names = "default";
639 pinctrl-0 = <&wkup_i2c0_pins_default>; 639 pinctrl-0 = <&wkup_i2c0_pins_default>;
640 clock-frequency = <400000>; 640 clock-frequency = <400000>;
641 641
642 eeprom@50 { 642 eeprom@50 {
643 compatible = "atmel,24c04"; 643 compatible = "atmel,24c04";
644 reg = <0x50>; 644 reg = <0x50>;
645 pinctrl-names = "default"; 645 pinctrl-names = "default";
646 pinctrl-0 = <&eeprom_wp_pins_d 646 pinctrl-0 = <&eeprom_wp_pins_default>;
647 }; 647 };
648 }; 648 };
649 649
650 &wkup_gpio0 { 650 &wkup_gpio0 {
651 status = "okay"; 651 status = "okay";
652 pinctrl-names = "default"; 652 pinctrl-names = "default";
653 pinctrl-0 = <&mcu_adc0_pins_default>, 653 pinctrl-0 = <&mcu_adc0_pins_default>, <&mcu_adc1_pins_default>,
654 <&mikro_bus_pins_default>; 654 <&mikro_bus_pins_default>;
655 }; 655 };
656 656
657 &main_gpio0 { 657 &main_gpio0 {
658 status = "okay"; 658 status = "okay";
659 pinctrl-names = "default"; 659 pinctrl-names = "default";
660 pinctrl-0 = <&csi1_gpio_pins_default>, 660 pinctrl-0 = <&csi1_gpio_pins_default>, <&csi0_gpio_pins_default>;
661 }; 661 };
662 662
663 &main_gpio1 { 663 &main_gpio1 {
664 status = "okay"; 664 status = "okay";
665 }; 665 };
666 666
667 &usb_serdes_mux { 667 &usb_serdes_mux {
668 idle-states = <1>, <1>; /* USB0 to SER 668 idle-states = <1>, <1>; /* USB0 to SERDES3, USB1 to SERDES2 */
669 }; 669 };
670 670
671 &serdes_ln_ctrl { 671 &serdes_ln_ctrl {
672 idle-states = <J721E_SERDES0_LANE0_IP4 672 idle-states = <J721E_SERDES0_LANE0_IP4_UNUSED>, <J721E_SERDES0_LANE1_IP4_UNUSED>,
673 <J721E_SERDES1_LANE0_PCI 673 <J721E_SERDES1_LANE0_PCIE1_LANE0>, <J721E_SERDES1_LANE1_PCIE1_LANE1>,
674 <J721E_SERDES2_LANE0_IP1 674 <J721E_SERDES2_LANE0_IP1_UNUSED>, <J721E_SERDES2_LANE1_USB3_1>,
675 <J721E_SERDES3_LANE0_USB 675 <J721E_SERDES3_LANE0_USB3_0_SWAP>, <J721E_SERDES3_LANE1_USB3_0>,
676 <J721E_SERDES4_LANE0_EDP 676 <J721E_SERDES4_LANE0_EDP_LANE0>, <J721E_SERDES4_LANE1_EDP_LANE1>,
677 <J721E_SERDES4_LANE2_EDP 677 <J721E_SERDES4_LANE2_EDP_LANE2>, <J721E_SERDES4_LANE3_EDP_LANE3>;
678 }; 678 };
679 679
680 &serdes_wiz3 { 680 &serdes_wiz3 {
681 typec-dir-gpios = <&main_gpio1 3 GPIO_ 681 typec-dir-gpios = <&main_gpio1 3 GPIO_ACTIVE_LOW>;
682 typec-dir-debounce-ms = <700>; /* TUS 682 typec-dir-debounce-ms = <700>; /* TUSB321, tCCB_DEFAULT 133 ms */
683 }; 683 };
684 684
685 &serdes3 { 685 &serdes3 {
686 serdes3_usb_link: phy@0 { 686 serdes3_usb_link: phy@0 {
687 reg = <0>; 687 reg = <0>;
688 cdns,num-lanes = <2>; 688 cdns,num-lanes = <2>;
689 #phy-cells = <0>; 689 #phy-cells = <0>;
690 cdns,phy-type = <PHY_TYPE_USB3 690 cdns,phy-type = <PHY_TYPE_USB3>;
691 resets = <&serdes_wiz3 1>, <&s 691 resets = <&serdes_wiz3 1>, <&serdes_wiz3 2>;
692 }; 692 };
693 }; 693 };
694 694
695 &serdes4 { 695 &serdes4 {
696 torrent_phy_dp: phy@0 { 696 torrent_phy_dp: phy@0 {
697 reg = <0>; 697 reg = <0>;
698 resets = <&serdes_wiz4 1>; 698 resets = <&serdes_wiz4 1>;
699 cdns,phy-type = <PHY_TYPE_DP>; 699 cdns,phy-type = <PHY_TYPE_DP>;
700 cdns,num-lanes = <4>; 700 cdns,num-lanes = <4>;
701 cdns,max-bit-rate = <5400>; 701 cdns,max-bit-rate = <5400>;
702 #phy-cells = <0>; 702 #phy-cells = <0>;
703 }; 703 };
704 }; 704 };
705 705
706 &mhdp { 706 &mhdp {
707 phys = <&torrent_phy_dp>; 707 phys = <&torrent_phy_dp>;
708 phy-names = "dpphy"; 708 phy-names = "dpphy";
709 pinctrl-names = "default"; 709 pinctrl-names = "default";
710 pinctrl-0 = <&dp0_pins_default>; 710 pinctrl-0 = <&dp0_pins_default>;
711 }; 711 };
712 712
713 &usbss0 { 713 &usbss0 {
714 pinctrl-names = "default"; 714 pinctrl-names = "default";
715 pinctrl-0 = <&main_usbss0_pins_default 715 pinctrl-0 = <&main_usbss0_pins_default>;
716 ti,vbus-divider; 716 ti,vbus-divider;
717 }; 717 };
718 718
719 &usb0 { 719 &usb0 {
720 dr_mode = "peripheral"; 720 dr_mode = "peripheral";
721 maximum-speed = "super-speed"; 721 maximum-speed = "super-speed";
722 phys = <&serdes3_usb_link>; 722 phys = <&serdes3_usb_link>;
723 phy-names = "cdns3,usb3-phy"; 723 phy-names = "cdns3,usb3-phy";
724 }; 724 };
725 725
726 &serdes2 { 726 &serdes2 {
727 serdes2_usb_link: phy@1 { 727 serdes2_usb_link: phy@1 {
728 reg = <1>; 728 reg = <1>;
729 cdns,num-lanes = <1>; 729 cdns,num-lanes = <1>;
730 #phy-cells = <0>; 730 #phy-cells = <0>;
731 cdns,phy-type = <PHY_TYPE_USB3 731 cdns,phy-type = <PHY_TYPE_USB3>;
732 resets = <&serdes_wiz2 2>; 732 resets = <&serdes_wiz2 2>;
733 }; 733 };
734 }; 734 };
735 735
736 &usbss1 { 736 &usbss1 {
737 pinctrl-names = "default"; 737 pinctrl-names = "default";
738 pinctrl-0 = <&main_usbss1_pins_default 738 pinctrl-0 = <&main_usbss1_pins_default>, <&mcu_usbss1_pins_default>;
739 ti,vbus-divider; 739 ti,vbus-divider;
740 }; 740 };
741 741
742 &usb1 { 742 &usb1 {
743 dr_mode = "host"; 743 dr_mode = "host";
744 maximum-speed = "super-speed"; 744 maximum-speed = "super-speed";
745 phys = <&serdes2_usb_link>; 745 phys = <&serdes2_usb_link>;
746 phy-names = "cdns3,usb3-phy"; 746 phy-names = "cdns3,usb3-phy";
747 }; 747 };
748 748
749 &tscadc0 { 749 &tscadc0 {
750 status = "okay"; 750 status = "okay";
751 /* BBB Header: P9.39, P9.40, P9.37, P9 751 /* BBB Header: P9.39, P9.40, P9.37, P9.38, P9.33, P9.36, P9.35 */
752 adc { 752 adc {
753 ti,adc-channels = <0 1 2 3 4 5 753 ti,adc-channels = <0 1 2 3 4 5 6>;
754 }; 754 };
755 }; 755 };
756 756
757 &tscadc1 { 757 &tscadc1 {
758 status = "okay"; 758 status = "okay";
759 /* MCU mikroBUS Header J10.1 - MCU_ADC 759 /* MCU mikroBUS Header J10.1 - MCU_ADC1_AIN0 */
760 adc { 760 adc {
761 ti,adc-channels = <0>; 761 ti,adc-channels = <0>;
762 }; 762 };
763 }; 763 };
764 764
765 &mcu_cpsw { 765 &mcu_cpsw {
766 pinctrl-names = "default"; 766 pinctrl-names = "default";
767 pinctrl-0 = <&mcu_cpsw_pins_default>; 767 pinctrl-0 = <&mcu_cpsw_pins_default>;
768 }; 768 };
769 769
770 &davinci_mdio { 770 &davinci_mdio {
771 pinctrl-names = "default"; 771 pinctrl-names = "default";
772 pinctrl-0 = <&mcu_mdio_pins_default>; 772 pinctrl-0 = <&mcu_mdio_pins_default>;
773 773
774 phy0: ethernet-phy@0 { 774 phy0: ethernet-phy@0 {
775 reg = <0>; 775 reg = <0>;
776 ti,rx-internal-delay = <DP8386 776 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
777 ti,fifo-depth = <DP83867_PHYCR 777 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
778 }; 778 };
779 }; 779 };
780 780
781 &cpsw_port1 { 781 &cpsw_port1 {
782 phy-mode = "rgmii-rxid"; 782 phy-mode = "rgmii-rxid";
783 phy-handle = <&phy0>; 783 phy-handle = <&phy0>;
784 }; 784 };
785 785
786 &dss { 786 &dss {
787 /* 787 /*
788 * These clock assignments are chosen 788 * These clock assignments are chosen to enable the following outputs:
789 * 789 *
790 * VP0 - DisplayPort SST 790 * VP0 - DisplayPort SST
791 * VP1 - DPI0 791 * VP1 - DPI0
792 * VP2 - DSI 792 * VP2 - DSI
793 * VP3 - DPI1 793 * VP3 - DPI1
794 */ 794 */
795 795
796 assigned-clocks = <&k3_clks 152 1>, 796 assigned-clocks = <&k3_clks 152 1>, /* VP 1 pixel clock */
797 <&k3_clks 152 4>, 797 <&k3_clks 152 4>, /* VP 2 pixel clock */
798 <&k3_clks 152 9>, 798 <&k3_clks 152 9>, /* VP 3 pixel clock */
799 <&k3_clks 152 13>; 799 <&k3_clks 152 13>; /* VP 4 pixel clock */
800 assigned-clock-parents = <&k3_clks 152 800 assigned-clock-parents = <&k3_clks 152 2>, /* PLL16_HSDIV0 */
801 <&k3_clks 152 801 <&k3_clks 152 6>, /* PLL19_HSDIV0 */
802 <&k3_clks 152 802 <&k3_clks 152 11>, /* PLL18_HSDIV0 */
803 <&k3_clks 152 803 <&k3_clks 152 18>; /* PLL23_HSDIV0 */
804 }; 804 };
805 805
806 &dss_ports { 806 &dss_ports {
807 port { 807 port {
808 dpi0_out: endpoint { 808 dpi0_out: endpoint {
809 remote-endpoint = <&dp 809 remote-endpoint = <&dp0_in>;
810 }; 810 };
811 }; 811 };
812 }; 812 };
813 813
814 &dp0_ports { 814 &dp0_ports {
815 #address-cells = <1>; 815 #address-cells = <1>;
816 #size-cells = <0>; 816 #size-cells = <0>;
817 817
818 port@0 { 818 port@0 {
819 reg = <0>; 819 reg = <0>;
820 dp0_in: endpoint { 820 dp0_in: endpoint {
821 remote-endpoint = <&dp 821 remote-endpoint = <&dpi0_out>;
822 }; 822 };
823 }; 823 };
824 824
825 port@4 { 825 port@4 {
826 reg = <4>; 826 reg = <4>;
827 dp0_out: endpoint { 827 dp0_out: endpoint {
828 remote-endpoint = <&dp 828 remote-endpoint = <&dp_connector_in>;
829 }; 829 };
830 }; 830 };
831 }; 831 };
832 832
833 &serdes0 { 833 &serdes0 {
834 serdes0_pcie_link: phy@0 { 834 serdes0_pcie_link: phy@0 {
835 reg = <0>; 835 reg = <0>;
836 cdns,num-lanes = <1>; 836 cdns,num-lanes = <1>;
837 #phy-cells = <0>; 837 #phy-cells = <0>;
838 cdns,phy-type = <PHY_TYPE_PCIE 838 cdns,phy-type = <PHY_TYPE_PCIE>;
839 resets = <&serdes_wiz0 1>; 839 resets = <&serdes_wiz0 1>;
840 }; 840 };
841 }; 841 };
842 842
843 &serdes1 { 843 &serdes1 {
844 serdes1_pcie_link: phy@0 { 844 serdes1_pcie_link: phy@0 {
845 reg = <0>; 845 reg = <0>;
846 cdns,num-lanes = <2>; 846 cdns,num-lanes = <2>;
847 #phy-cells = <0>; 847 #phy-cells = <0>;
848 cdns,phy-type = <PHY_TYPE_PCIE 848 cdns,phy-type = <PHY_TYPE_PCIE>;
849 resets = <&serdes_wiz1 1>, <&s 849 resets = <&serdes_wiz1 1>, <&serdes_wiz1 2>;
850 }; 850 };
851 }; 851 };
852 852
853 &pcie1_rc { 853 &pcie1_rc {
854 status = "okay"; 854 status = "okay";
855 pinctrl-names = "default"; 855 pinctrl-names = "default";
856 pinctrl-0 = <&pcie1_rst_pins_default>; 856 pinctrl-0 = <&pcie1_rst_pins_default>;
857 phys = <&serdes1_pcie_link>; 857 phys = <&serdes1_pcie_link>;
858 phy-names = "pcie-phy"; 858 phy-names = "pcie-phy";
859 num-lanes = <2>; 859 num-lanes = <2>;
860 max-link-speed = <3>; 860 max-link-speed = <3>;
861 reset-gpios = <&main_gpio0 22 GPIO_ACT 861 reset-gpios = <&main_gpio0 22 GPIO_ACTIVE_HIGH>;
862 }; 862 };
863 863
864 &ufs_wrapper { 864 &ufs_wrapper {
865 status = "disabled"; 865 status = "disabled";
866 }; 866 };
867 867
868 &mailbox0_cluster0 { 868 &mailbox0_cluster0 {
869 status = "okay"; 869 status = "okay";
870 interrupts = <436>; 870 interrupts = <436>;
871 871
872 mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0 872 mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 {
873 ti,mbox-rx = <0 0 0>; 873 ti,mbox-rx = <0 0 0>;
874 ti,mbox-tx = <1 0 0>; 874 ti,mbox-tx = <1 0 0>;
875 }; 875 };
876 876
877 mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0 877 mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 {
878 ti,mbox-rx = <2 0 0>; 878 ti,mbox-rx = <2 0 0>;
879 ti,mbox-tx = <3 0 0>; 879 ti,mbox-tx = <3 0 0>;
880 }; 880 };
881 }; 881 };
882 882
883 &mailbox0_cluster1 { 883 &mailbox0_cluster1 {
884 status = "okay"; 884 status = "okay";
885 interrupts = <432>; 885 interrupts = <432>;
886 886
887 mbox_main_r5fss0_core0: mbox-main-r5fs 887 mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
888 ti,mbox-rx = <0 0 0>; 888 ti,mbox-rx = <0 0 0>;
889 ti,mbox-tx = <1 0 0>; 889 ti,mbox-tx = <1 0 0>;
890 }; 890 };
891 891
892 mbox_main_r5fss0_core1: mbox-main-r5fs 892 mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 {
893 ti,mbox-rx = <2 0 0>; 893 ti,mbox-rx = <2 0 0>;
894 ti,mbox-tx = <3 0 0>; 894 ti,mbox-tx = <3 0 0>;
895 }; 895 };
896 }; 896 };
897 897
898 &mailbox0_cluster2 { 898 &mailbox0_cluster2 {
899 status = "okay"; 899 status = "okay";
900 interrupts = <428>; 900 interrupts = <428>;
901 901
902 mbox_main_r5fss1_core0: mbox-main-r5fs 902 mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 {
903 ti,mbox-rx = <0 0 0>; 903 ti,mbox-rx = <0 0 0>;
904 ti,mbox-tx = <1 0 0>; 904 ti,mbox-tx = <1 0 0>;
905 }; 905 };
906 906
907 mbox_main_r5fss1_core1: mbox-main-r5fs 907 mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 {
908 ti,mbox-rx = <2 0 0>; 908 ti,mbox-rx = <2 0 0>;
909 ti,mbox-tx = <3 0 0>; 909 ti,mbox-tx = <3 0 0>;
910 }; 910 };
911 }; 911 };
912 912
913 &mailbox0_cluster3 { 913 &mailbox0_cluster3 {
914 status = "okay"; 914 status = "okay";
915 interrupts = <424>; 915 interrupts = <424>;
916 916
917 mbox_c66_0: mbox-c66-0 { 917 mbox_c66_0: mbox-c66-0 {
918 ti,mbox-rx = <0 0 0>; 918 ti,mbox-rx = <0 0 0>;
919 ti,mbox-tx = <1 0 0>; 919 ti,mbox-tx = <1 0 0>;
920 }; 920 };
921 921
922 mbox_c66_1: mbox-c66-1 { 922 mbox_c66_1: mbox-c66-1 {
923 ti,mbox-rx = <2 0 0>; 923 ti,mbox-rx = <2 0 0>;
924 ti,mbox-tx = <3 0 0>; 924 ti,mbox-tx = <3 0 0>;
925 }; 925 };
926 }; 926 };
927 927
928 &mailbox0_cluster4 { 928 &mailbox0_cluster4 {
929 status = "okay"; 929 status = "okay";
930 interrupts = <420>; 930 interrupts = <420>;
931 931
932 mbox_c71_0: mbox-c71-0 { 932 mbox_c71_0: mbox-c71-0 {
933 ti,mbox-rx = <0 0 0>; 933 ti,mbox-rx = <0 0 0>;
934 ti,mbox-tx = <1 0 0>; 934 ti,mbox-tx = <1 0 0>;
935 }; 935 };
936 }; 936 };
937 937
938 &mcu_r5fss0_core0 { 938 &mcu_r5fss0_core0 {
939 mboxes = <&mailbox0_cluster0 &mbox_mcu !! 939 mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core0>;
940 memory-region = <&mcu_r5fss0_core0_dma 940 memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
941 <&mcu_r5fss0_core0_mem 941 <&mcu_r5fss0_core0_memory_region>;
942 }; 942 };
943 943
944 &mcu_r5fss0_core1 { 944 &mcu_r5fss0_core1 {
945 mboxes = <&mailbox0_cluster0 &mbox_mcu !! 945 mboxes = <&mailbox0_cluster0>, <&mbox_mcu_r5fss0_core1>;
946 memory-region = <&mcu_r5fss0_core1_dma 946 memory-region = <&mcu_r5fss0_core1_dma_memory_region>,
947 <&mcu_r5fss0_core1_mem 947 <&mcu_r5fss0_core1_memory_region>;
948 }; 948 };
949 949
950 &main_r5fss0_core0 { 950 &main_r5fss0_core0 {
951 mboxes = <&mailbox0_cluster1 &mbox_mai !! 951 mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core0>;
952 memory-region = <&main_r5fss0_core0_dm 952 memory-region = <&main_r5fss0_core0_dma_memory_region>,
953 <&main_r5fss0_core0_me 953 <&main_r5fss0_core0_memory_region>;
954 }; 954 };
955 955
956 &main_r5fss0_core1 { 956 &main_r5fss0_core1 {
957 mboxes = <&mailbox0_cluster1 &mbox_mai !! 957 mboxes = <&mailbox0_cluster1>, <&mbox_main_r5fss0_core1>;
958 memory-region = <&main_r5fss0_core1_dm 958 memory-region = <&main_r5fss0_core1_dma_memory_region>,
959 <&main_r5fss0_core1_me 959 <&main_r5fss0_core1_memory_region>;
960 }; 960 };
961 961
962 &main_r5fss1_core0 { 962 &main_r5fss1_core0 {
963 mboxes = <&mailbox0_cluster2 &mbox_mai !! 963 mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss1_core0>;
964 memory-region = <&main_r5fss1_core0_dm 964 memory-region = <&main_r5fss1_core0_dma_memory_region>,
965 <&main_r5fss1_core0_me 965 <&main_r5fss1_core0_memory_region>;
966 }; 966 };
967 967
968 &main_r5fss1_core1 { 968 &main_r5fss1_core1 {
969 mboxes = <&mailbox0_cluster2 &mbox_mai !! 969 mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss1_core1>;
970 memory-region = <&main_r5fss1_core1_dm 970 memory-region = <&main_r5fss1_core1_dma_memory_region>,
971 <&main_r5fss1_core1_me 971 <&main_r5fss1_core1_memory_region>;
972 }; 972 };
973 973
974 &c66_0 { 974 &c66_0 {
975 status = "okay"; 975 status = "okay";
976 mboxes = <&mailbox0_cluster3 &mbox_c66 !! 976 mboxes = <&mailbox0_cluster3>, <&mbox_c66_0>;
977 memory-region = <&c66_0_dma_memory_reg 977 memory-region = <&c66_0_dma_memory_region>,
978 <&c66_0_memory_region> 978 <&c66_0_memory_region>;
979 }; 979 };
980 980
981 &c66_1 { 981 &c66_1 {
982 status = "okay"; 982 status = "okay";
983 mboxes = <&mailbox0_cluster3 &mbox_c66 !! 983 mboxes = <&mailbox0_cluster3>, <&mbox_c66_1>;
984 memory-region = <&c66_1_dma_memory_reg 984 memory-region = <&c66_1_dma_memory_region>,
985 <&c66_1_memory_region> 985 <&c66_1_memory_region>;
986 }; 986 };
987 987
988 &c71_0 { 988 &c71_0 {
989 status = "okay"; 989 status = "okay";
990 mboxes = <&mailbox0_cluster4 &mbox_c71 !! 990 mboxes = <&mailbox0_cluster4>, <&mbox_c71_0>;
991 memory-region = <&c71_0_dma_memory_reg 991 memory-region = <&c71_0_dma_memory_region>,
992 <&c71_0_memory_region> 992 <&c71_0_memory_region>;
993 }; 993 };
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