1 // SPDX-License-Identifier: GPL-2.0-only OR MI 1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
2 /* 2 /*
3 * SoM: https://www.ti.com/lit/zip/sprr439 3 * SoM: https://www.ti.com/lit/zip/sprr439
4 * 4 *
5 * Copyright (C) 2021-2024 Texas Instruments I 5 * Copyright (C) 2021-2024 Texas Instruments Incorporated - https://www.ti.com/
6 */ 6 */
7 7
8 /dts-v1/; 8 /dts-v1/;
9 9
10 #include "k3-j721s2.dtsi" 10 #include "k3-j721s2.dtsi"
11 #include <dt-bindings/gpio/gpio.h> 11 #include <dt-bindings/gpio/gpio.h>
12 12
13 / { 13 / {
14 memory@80000000 { 14 memory@80000000 {
15 device_type = "memory"; 15 device_type = "memory";
16 bootph-all; <<
17 /* 16 GB RAM */ 16 /* 16 GB RAM */
18 reg = <0x00000000 0x80000000 0 !! 17 reg = <0x00 0x80000000 0x00 0x80000000>,
19 <0x00000008 0x80000000 0 !! 18 <0x08 0x80000000 0x03 0x80000000>;
20 }; 19 };
21 20
22 /* Reserving memory regions still pend 21 /* Reserving memory regions still pending */
23 reserved_memory: reserved-memory { 22 reserved_memory: reserved-memory {
24 #address-cells = <2>; 23 #address-cells = <2>;
25 #size-cells = <2>; 24 #size-cells = <2>;
26 ranges; 25 ranges;
27 26
28 secure_ddr: optee@9e800000 { 27 secure_ddr: optee@9e800000 {
29 reg = <0x00 0x9e800000 28 reg = <0x00 0x9e800000 0x00 0x01800000>;
30 alignment = <0x1000>; 29 alignment = <0x1000>;
31 no-map; 30 no-map;
32 }; 31 };
33 32
34 mcu_r5fss0_core0_dma_memory_re 33 mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 {
35 compatible = "shared-d 34 compatible = "shared-dma-pool";
36 reg = <0x00 0xa0000000 35 reg = <0x00 0xa0000000 0x00 0x100000>;
37 no-map; 36 no-map;
38 }; 37 };
39 38
40 mcu_r5fss0_core0_memory_region 39 mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 {
41 compatible = "shared-d 40 compatible = "shared-dma-pool";
42 reg = <0x00 0xa0100000 41 reg = <0x00 0xa0100000 0x00 0xf00000>;
43 no-map; 42 no-map;
44 }; 43 };
45 44
46 mcu_r5fss0_core1_dma_memory_re 45 mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 {
47 compatible = "shared-d 46 compatible = "shared-dma-pool";
48 reg = <0x00 0xa1000000 47 reg = <0x00 0xa1000000 0x00 0x100000>;
49 no-map; 48 no-map;
50 }; 49 };
51 50
52 mcu_r5fss0_core1_memory_region 51 mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 {
53 compatible = "shared-d 52 compatible = "shared-dma-pool";
54 reg = <0x00 0xa1100000 53 reg = <0x00 0xa1100000 0x00 0xf00000>;
55 no-map; 54 no-map;
56 }; 55 };
57 56
58 main_r5fss0_core0_dma_memory_r 57 main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a2000000 {
59 compatible = "shared-d 58 compatible = "shared-dma-pool";
60 reg = <0x00 0xa2000000 59 reg = <0x00 0xa2000000 0x00 0x100000>;
61 no-map; 60 no-map;
62 }; 61 };
63 62
64 main_r5fss0_core0_memory_regio 63 main_r5fss0_core0_memory_region: r5f-memory@a2100000 {
65 compatible = "shared-d 64 compatible = "shared-dma-pool";
66 reg = <0x00 0xa2100000 65 reg = <0x00 0xa2100000 0x00 0xf00000>;
67 no-map; 66 no-map;
68 }; 67 };
69 68
70 main_r5fss0_core1_dma_memory_r 69 main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a3000000 {
71 compatible = "shared-d 70 compatible = "shared-dma-pool";
72 reg = <0x00 0xa3000000 71 reg = <0x00 0xa3000000 0x00 0x100000>;
73 no-map; 72 no-map;
74 }; 73 };
75 74
76 main_r5fss0_core1_memory_regio 75 main_r5fss0_core1_memory_region: r5f-memory@a3100000 {
77 compatible = "shared-d 76 compatible = "shared-dma-pool";
78 reg = <0x00 0xa3100000 77 reg = <0x00 0xa3100000 0x00 0xf00000>;
79 no-map; 78 no-map;
80 }; 79 };
81 80
82 main_r5fss1_core0_dma_memory_r 81 main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a4000000 {
83 compatible = "shared-d 82 compatible = "shared-dma-pool";
84 reg = <0x00 0xa4000000 83 reg = <0x00 0xa4000000 0x00 0x100000>;
85 no-map; 84 no-map;
86 }; 85 };
87 86
88 main_r5fss1_core0_memory_regio 87 main_r5fss1_core0_memory_region: r5f-memory@a4100000 {
89 compatible = "shared-d 88 compatible = "shared-dma-pool";
90 reg = <0x00 0xa4100000 89 reg = <0x00 0xa4100000 0x00 0xf00000>;
91 no-map; 90 no-map;
92 }; 91 };
93 92
94 main_r5fss1_core1_dma_memory_r 93 main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a5000000 {
95 compatible = "shared-d 94 compatible = "shared-dma-pool";
96 reg = <0x00 0xa5000000 95 reg = <0x00 0xa5000000 0x00 0x100000>;
97 no-map; 96 no-map;
98 }; 97 };
99 98
100 main_r5fss1_core1_memory_regio 99 main_r5fss1_core1_memory_region: r5f-memory@a5100000 {
101 compatible = "shared-d 100 compatible = "shared-dma-pool";
102 reg = <0x00 0xa5100000 101 reg = <0x00 0xa5100000 0x00 0xf00000>;
103 no-map; 102 no-map;
104 }; 103 };
105 104
106 c71_0_dma_memory_region: c71-d 105 c71_0_dma_memory_region: c71-dma-memory@a6000000 {
107 compatible = "shared-d 106 compatible = "shared-dma-pool";
108 reg = <0x00 0xa6000000 107 reg = <0x00 0xa6000000 0x00 0x100000>;
109 no-map; 108 no-map;
110 }; 109 };
111 110
112 c71_0_memory_region: c71-memor 111 c71_0_memory_region: c71-memory@a6100000 {
113 compatible = "shared-d 112 compatible = "shared-dma-pool";
114 reg = <0x00 0xa6100000 113 reg = <0x00 0xa6100000 0x00 0xf00000>;
115 no-map; 114 no-map;
116 }; 115 };
117 116
118 c71_1_dma_memory_region: c71-d 117 c71_1_dma_memory_region: c71-dma-memory@a7000000 {
119 compatible = "shared-d 118 compatible = "shared-dma-pool";
120 reg = <0x00 0xa7000000 119 reg = <0x00 0xa7000000 0x00 0x100000>;
121 no-map; 120 no-map;
122 }; 121 };
123 122
124 c71_1_memory_region: c71-memor 123 c71_1_memory_region: c71-memory@a7100000 {
125 compatible = "shared-d 124 compatible = "shared-dma-pool";
126 reg = <0x00 0xa7100000 125 reg = <0x00 0xa7100000 0x00 0xf00000>;
127 no-map; 126 no-map;
128 }; 127 };
129 128
130 rtos_ipc_memory_region: ipc-me 129 rtos_ipc_memory_region: ipc-memories@a8000000 {
131 reg = <0x00 0xa8000000 130 reg = <0x00 0xa8000000 0x00 0x01c00000>;
132 alignment = <0x1000>; 131 alignment = <0x1000>;
133 no-map; 132 no-map;
134 }; 133 };
135 }; 134 };
136 135
137 mux0: mux-controller-0 { !! 136 mux0: mux-controller {
138 compatible = "gpio-mux"; 137 compatible = "gpio-mux";
139 #mux-state-cells = <1>; 138 #mux-state-cells = <1>;
140 mux-gpios = <&exp_som 1 GPIO_A 139 mux-gpios = <&exp_som 1 GPIO_ACTIVE_HIGH>;
141 }; 140 };
142 141
143 mux1: mux-controller-1 { !! 142 mux1: mux-controller {
144 compatible = "gpio-mux"; 143 compatible = "gpio-mux";
145 #mux-state-cells = <1>; 144 #mux-state-cells = <1>;
146 mux-gpios = <&exp_som 2 GPIO_A 145 mux-gpios = <&exp_som 2 GPIO_ACTIVE_HIGH>;
147 }; 146 };
148 147
149 transceiver0: can-phy0 { 148 transceiver0: can-phy0 {
150 /* standby pin has been ground 149 /* standby pin has been grounded by default */
151 compatible = "ti,tcan1042"; 150 compatible = "ti,tcan1042";
152 #phy-cells = <0>; 151 #phy-cells = <0>;
153 max-bitrate = <5000000>; 152 max-bitrate = <5000000>;
154 }; 153 };
155 }; 154 };
156 155
157 &wkup_pmx0 { 156 &wkup_pmx0 {
158 mcu_fss0_ospi0_pins_default: mcu-fss0- 157 mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-default-pins {
159 pinctrl-single,pins = < 158 pinctrl-single,pins = <
160 J721S2_WKUP_IOPAD(0x00 159 J721S2_WKUP_IOPAD(0x000, PIN_OUTPUT, 0) /* (D19) MCU_OSPI0_CLK */
161 J721S2_WKUP_IOPAD(0x02 160 J721S2_WKUP_IOPAD(0x02c, PIN_OUTPUT, 0) /* (F15) MCU_OSPI0_CSn0 */
162 J721S2_WKUP_IOPAD(0x00 161 J721S2_WKUP_IOPAD(0x00c, PIN_INPUT, 0) /* (C19) MCU_OSPI0_D0 */
163 J721S2_WKUP_IOPAD(0x01 162 J721S2_WKUP_IOPAD(0x010, PIN_INPUT, 0) /* (F16) MCU_OSPI0_D1 */
164 J721S2_WKUP_IOPAD(0x01 163 J721S2_WKUP_IOPAD(0x014, PIN_INPUT, 0) /* (G15) MCU_OSPI0_D2 */
165 J721S2_WKUP_IOPAD(0x01 164 J721S2_WKUP_IOPAD(0x018, PIN_INPUT, 0) /* (F18) MCU_OSPI0_D3 */
166 J721S2_WKUP_IOPAD(0x01 165 J721S2_WKUP_IOPAD(0x01c, PIN_INPUT, 0) /* (E19) MCU_OSPI0_D4 */
167 J721S2_WKUP_IOPAD(0x02 166 J721S2_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (G19) MCU_OSPI0_D5 */
168 J721S2_WKUP_IOPAD(0x02 167 J721S2_WKUP_IOPAD(0x024, PIN_INPUT, 0) /* (F19) MCU_OSPI0_D6 */
169 J721S2_WKUP_IOPAD(0x02 168 J721S2_WKUP_IOPAD(0x028, PIN_INPUT, 0) /* (F20) MCU_OSPI0_D7 */
170 J721S2_WKUP_IOPAD(0x00 169 J721S2_WKUP_IOPAD(0x008, PIN_INPUT, 0) /* (E18) MCU_OSPI0_DQS */
171 J721S2_WKUP_IOPAD(0x00 170 J721S2_WKUP_IOPAD(0x004, PIN_INPUT, 0) /* (E20) MCU_OSPI0_LBCLKO */
172 >; 171 >;
173 }; 172 };
174 }; 173 };
175 174
176 &wkup_pmx1 { 175 &wkup_pmx1 {
177 pmic_irq_pins_default: pmic-irq-defaul 176 pmic_irq_pins_default: pmic-irq-default-pins {
178 pinctrl-single,pins = < 177 pinctrl-single,pins = <
179 /* (C21) MCU_OSPI1_CSn 178 /* (C21) MCU_OSPI1_CSn1.WKUP_GPIO0_39 */
180 J721S2_WKUP_IOPAD(0x02 179 J721S2_WKUP_IOPAD(0x028, PIN_INPUT, 7)
181 >; 180 >;
182 }; 181 };
183 }; 182 };
184 183
185 &wkup_pmx2 { 184 &wkup_pmx2 {
186 wkup_i2c0_pins_default: wkup-i2c0-defa 185 wkup_i2c0_pins_default: wkup-i2c0-default-pins {
187 pinctrl-single,pins = < 186 pinctrl-single,pins = <
188 J721S2_WKUP_IOPAD(0x98 187 J721S2_WKUP_IOPAD(0x98, PIN_INPUT, 0) /* (H24) WKUP_I2C0_SCL */
189 J721S2_WKUP_IOPAD(0x9c 188 J721S2_WKUP_IOPAD(0x9c, PIN_INPUT, 0) /* (H27) WKUP_I2C0_SDA */
190 >; 189 >;
191 }; 190 };
192 }; 191 };
193 192
194 &main_pmx0 { 193 &main_pmx0 {
195 main_i2c0_pins_default: main-i2c0-defa 194 main_i2c0_pins_default: main-i2c0-default-pins {
196 pinctrl-single,pins = < 195 pinctrl-single,pins = <
197 J721S2_IOPAD(0x0e0, PI 196 J721S2_IOPAD(0x0e0, PIN_INPUT_PULLUP, 0) /* (AH25) I2C0_SCL */
198 J721S2_IOPAD(0x0e4, PI 197 J721S2_IOPAD(0x0e4, PIN_INPUT_PULLUP, 0) /* (AE24) I2C0_SDA */
199 >; 198 >;
200 }; 199 };
201 200
202 main_mcan16_pins_default: main-mcan16- 201 main_mcan16_pins_default: main-mcan16-default-pins {
203 pinctrl-single,pins = < 202 pinctrl-single,pins = <
204 J721S2_IOPAD(0x028, PI 203 J721S2_IOPAD(0x028, PIN_INPUT, 0) /* (AB24) MCAN16_RX */
205 J721S2_IOPAD(0x024, PI 204 J721S2_IOPAD(0x024, PIN_OUTPUT, 0) /* (Y28) MCAN16_TX */
206 >; 205 >;
207 }; 206 };
208 }; 207 };
209 208
210 &wkup_i2c0 { 209 &wkup_i2c0 {
211 status = "okay"; 210 status = "okay";
212 pinctrl-names = "default"; 211 pinctrl-names = "default";
213 pinctrl-0 = <&wkup_i2c0_pins_default>; 212 pinctrl-0 = <&wkup_i2c0_pins_default>;
214 clock-frequency = <400000>; 213 clock-frequency = <400000>;
215 214
216 eeprom@50 { 215 eeprom@50 {
217 /* CAV24C256WE-GT3 */ 216 /* CAV24C256WE-GT3 */
218 compatible = "atmel,24c256"; 217 compatible = "atmel,24c256";
219 reg = <0x50>; 218 reg = <0x50>;
220 }; 219 };
221 220
222 tps659411: pmic@48 { 221 tps659411: pmic@48 {
223 compatible = "ti,tps6594-q1"; 222 compatible = "ti,tps6594-q1";
224 reg = <0x48>; 223 reg = <0x48>;
225 system-power-controller; 224 system-power-controller;
226 pinctrl-names = "default"; 225 pinctrl-names = "default";
227 pinctrl-0 = <&pmic_irq_pins_de 226 pinctrl-0 = <&pmic_irq_pins_default>;
228 interrupt-parent = <&wkup_gpio 227 interrupt-parent = <&wkup_gpio0>;
229 interrupts = <39 IRQ_TYPE_EDGE 228 interrupts = <39 IRQ_TYPE_EDGE_FALLING>;
230 gpio-controller; 229 gpio-controller;
231 #gpio-cells = <2>; 230 #gpio-cells = <2>;
232 ti,primary-pmic; 231 ti,primary-pmic;
233 buck1234-supply = <&vsys_3v3>; 232 buck1234-supply = <&vsys_3v3>;
234 buck5-supply = <&vsys_3v3>; 233 buck5-supply = <&vsys_3v3>;
235 ldo1-supply = <&vsys_3v3>; 234 ldo1-supply = <&vsys_3v3>;
236 ldo2-supply = <&vsys_3v3>; 235 ldo2-supply = <&vsys_3v3>;
237 ldo3-supply = <&vsys_3v3>; 236 ldo3-supply = <&vsys_3v3>;
238 ldo4-supply = <&vsys_3v3>; 237 ldo4-supply = <&vsys_3v3>;
239 238
240 regulators { 239 regulators {
241 bucka1234: buck1234 { 240 bucka1234: buck1234 {
242 regulator-name 241 regulator-name = "vdd_cpu_avs";
243 regulator-min- 242 regulator-min-microvolt = <600000>;
244 regulator-max- 243 regulator-max-microvolt = <900000>;
245 regulator-boot 244 regulator-boot-on;
246 regulator-alwa 245 regulator-always-on;
247 bootph-pre-ram 246 bootph-pre-ram;
248 }; 247 };
249 248
250 bucka5: buck5 { 249 bucka5: buck5 {
251 regulator-name 250 regulator-name = "vdd_mcu_0v85";
252 regulator-min- 251 regulator-min-microvolt = <850000>;
253 regulator-max- 252 regulator-max-microvolt = <850000>;
254 regulator-boot 253 regulator-boot-on;
255 regulator-alwa 254 regulator-always-on;
256 }; 255 };
257 256
258 ldoa1: ldo1 { 257 ldoa1: ldo1 {
259 regulator-name 258 regulator-name = "vdd_mcuwk_0v8";
260 regulator-min- 259 regulator-min-microvolt = <800000>;
261 regulator-max- 260 regulator-max-microvolt = <800000>;
262 regulator-boot 261 regulator-boot-on;
263 regulator-alwa 262 regulator-always-on;
264 }; 263 };
265 264
266 ldoa2: ldo2 { 265 ldoa2: ldo2 {
267 regulator-name 266 regulator-name = "vdd_mcu_gpioret_3v3";
268 regulator-min- 267 regulator-min-microvolt = <3300000>;
269 regulator-max- 268 regulator-max-microvolt = <3300000>;
270 regulator-boot 269 regulator-boot-on;
271 regulator-alwa 270 regulator-always-on;
272 }; 271 };
273 272
274 ldoa3: ldo3 { 273 ldoa3: ldo3 {
275 regulator-name 274 regulator-name = "vdd_mcuio_1v8";
276 regulator-min- 275 regulator-min-microvolt = <1800000>;
277 regulator-max- 276 regulator-max-microvolt = <1800000>;
278 regulator-boot 277 regulator-boot-on;
279 regulator-alwa 278 regulator-always-on;
280 }; 279 };
281 280
282 ldoa4: ldo4 { 281 ldoa4: ldo4 {
283 regulator-name 282 regulator-name = "vda_mcu_1v8";
284 regulator-min- 283 regulator-min-microvolt = <1800000>;
285 regulator-max- 284 regulator-max-microvolt = <1800000>;
286 regulator-boot 285 regulator-boot-on;
287 regulator-alwa 286 regulator-always-on;
288 }; 287 };
289 }; 288 };
290 }; 289 };
291 290
292 tps659414: pmic@4c { 291 tps659414: pmic@4c {
293 compatible = "ti,tps6594-q1"; 292 compatible = "ti,tps6594-q1";
294 reg = <0x4c>; 293 reg = <0x4c>;
295 system-power-controller; 294 system-power-controller;
296 interrupt-parent = <&wkup_gpio 295 interrupt-parent = <&wkup_gpio0>;
297 interrupts = <39 IRQ_TYPE_EDGE 296 interrupts = <39 IRQ_TYPE_EDGE_FALLING>;
298 gpio-controller; 297 gpio-controller;
299 #gpio-cells = <2>; 298 #gpio-cells = <2>;
300 buck1-supply = <&vsys_3v3>; 299 buck1-supply = <&vsys_3v3>;
301 buck2-supply = <&vsys_3v3>; 300 buck2-supply = <&vsys_3v3>;
302 buck3-supply = <&vsys_3v3>; 301 buck3-supply = <&vsys_3v3>;
303 buck4-supply = <&vsys_3v3>; 302 buck4-supply = <&vsys_3v3>;
304 buck5-supply = <&vsys_3v3>; 303 buck5-supply = <&vsys_3v3>;
305 ldo1-supply = <&vsys_3v3>; 304 ldo1-supply = <&vsys_3v3>;
306 ldo2-supply = <&vsys_3v3>; 305 ldo2-supply = <&vsys_3v3>;
307 ldo3-supply = <&vsys_3v3>; 306 ldo3-supply = <&vsys_3v3>;
308 ldo4-supply = <&vsys_3v3>; 307 ldo4-supply = <&vsys_3v3>;
309 308
310 regulators { 309 regulators {
311 buckb1: buck1 { 310 buckb1: buck1 {
312 regulator-name 311 regulator-name = "vdd_io_1v8_reg";
313 regulator-min- 312 regulator-min-microvolt = <1800000>;
314 regulator-max- 313 regulator-max-microvolt = <1800000>;
315 regulator-alwa 314 regulator-always-on;
316 regulator-boot 315 regulator-boot-on;
317 }; 316 };
318 317
319 buckb2: buck2 { 318 buckb2: buck2 {
320 regulator-name 319 regulator-name = "vdd_fpd_1v1";
321 regulator-min- 320 regulator-min-microvolt = <1100000>;
322 regulator-max- 321 regulator-max-microvolt = <1100000>;
323 regulator-boot 322 regulator-boot-on;
324 regulator-alwa 323 regulator-always-on;
325 }; 324 };
326 325
327 buckb3: buck3 { 326 buckb3: buck3 {
328 regulator-name 327 regulator-name = "vdd_phy_1v8";
329 regulator-min- 328 regulator-min-microvolt = <1800000>;
330 regulator-max- 329 regulator-max-microvolt = <1800000>;
331 regulator-boot 330 regulator-boot-on;
332 regulator-alwa 331 regulator-always-on;
333 }; 332 };
334 333
335 buckb4: buck4 { 334 buckb4: buck4 {
336 regulator-name 335 regulator-name = "vdd_ddr_1v1";
337 regulator-min- 336 regulator-min-microvolt = <1100000>;
338 regulator-max- 337 regulator-max-microvolt = <1100000>;
339 regulator-boot 338 regulator-boot-on;
340 regulator-alwa 339 regulator-always-on;
341 }; 340 };
342 341
343 buckb5: buck5 { 342 buckb5: buck5 {
344 regulator-name 343 regulator-name = "vdd_ram_0v85";
345 regulator-min- 344 regulator-min-microvolt = <850000>;
346 regulator-max- 345 regulator-max-microvolt = <850000>;
347 regulator-boot 346 regulator-boot-on;
348 regulator-alwa 347 regulator-always-on;
349 }; 348 };
350 349
351 ldob1: ldo1 { 350 ldob1: ldo1 {
352 regulator-name 351 regulator-name = "vdd_wk_0v8";
353 regulator-min- 352 regulator-min-microvolt = <800000>;
354 regulator-max- 353 regulator-max-microvolt = <800000>;
355 regulator-boot 354 regulator-boot-on;
356 regulator-alwa 355 regulator-always-on;
357 }; 356 };
358 357
359 ldob2: ldo2 { 358 ldob2: ldo2 {
360 regulator-name 359 regulator-name = "vdd_gpioret_3v3";
361 regulator-min- 360 regulator-min-microvolt = <3300000>;
362 regulator-max- 361 regulator-max-microvolt = <3300000>;
363 regulator-boot 362 regulator-boot-on;
364 regulator-alwa 363 regulator-always-on;
365 }; 364 };
366 365
367 ldob3: ldo3 { 366 ldob3: ldo3 {
368 regulator-name 367 regulator-name = "vda_dll_0v8";
369 regulator-min- 368 regulator-min-microvolt = <800000>;
370 regulator-max- 369 regulator-max-microvolt = <800000>;
371 regulator-boot 370 regulator-boot-on;
372 regulator-alwa 371 regulator-always-on;
373 }; 372 };
374 373
375 ldob4: ldo4 { 374 ldob4: ldo4 {
376 regulator-name 375 regulator-name = "vda_pll_1v8";
377 regulator-min- 376 regulator-min-microvolt = <1800000>;
378 regulator-max- 377 regulator-max-microvolt = <1800000>;
379 regulator-boot 378 regulator-boot-on;
380 regulator-alwa 379 regulator-always-on;
381 }; 380 };
382 }; 381 };
383 }; 382 };
384 383
385 lp876411: pmic@58 { 384 lp876411: pmic@58 {
386 compatible = "ti,lp8764-q1"; 385 compatible = "ti,lp8764-q1";
387 reg = <0x58>; 386 reg = <0x58>;
388 system-power-controller; 387 system-power-controller;
389 interrupt-parent = <&wkup_gpio 388 interrupt-parent = <&wkup_gpio0>;
390 interrupts = <39 IRQ_TYPE_EDGE 389 interrupts = <39 IRQ_TYPE_EDGE_FALLING>;
391 gpio-controller; 390 gpio-controller;
392 #gpio-cells = <2>; 391 #gpio-cells = <2>;
393 buck1234-supply = <&vsys_3v3>; 392 buck1234-supply = <&vsys_3v3>;
394 393
395 regulators { 394 regulators {
396 buckc1234: buck1234 { 395 buckc1234: buck1234 {
397 regulator-name 396 regulator-name = "vdd_core_0v8";
398 regulator-min- 397 regulator-min-microvolt = <800000>;
399 regulator-max- 398 regulator-max-microvolt = <800000>;
400 regulator-boot 399 regulator-boot-on;
401 regulator-alwa 400 regulator-always-on;
402 }; 401 };
403 }; 402 };
404 }; 403 };
405 }; 404 };
406 405
407 &main_i2c0 { 406 &main_i2c0 {
408 status = "okay"; 407 status = "okay";
409 pinctrl-names = "default"; 408 pinctrl-names = "default";
410 pinctrl-0 = <&main_i2c0_pins_default>; 409 pinctrl-0 = <&main_i2c0_pins_default>;
411 clock-frequency = <400000>; 410 clock-frequency = <400000>;
412 411
413 exp_som: gpio@21 { 412 exp_som: gpio@21 {
414 compatible = "ti,tca6408"; 413 compatible = "ti,tca6408";
415 reg = <0x21>; 414 reg = <0x21>;
416 gpio-controller; 415 gpio-controller;
417 #gpio-cells = <2>; 416 #gpio-cells = <2>;
418 gpio-line-names = "USB2.0_MUX_ 417 gpio-line-names = "USB2.0_MUX_SEL", "CANUART_MUX1_SEL0",
419 "CANUART_MUX 418 "CANUART_MUX2_SEL0", "CANUART_MUX_SEL1",
420 "GPIO_RGMII1 419 "GPIO_RGMII1_RST", "GPIO_eDP_ENABLE",
421 "GPIO_LIN_E 420 "GPIO_LIN_EN", "CAN_STB";
422 }; 421 };
423 }; 422 };
424 423
425 &main_mcan16 { 424 &main_mcan16 {
426 status = "okay"; 425 status = "okay";
427 pinctrl-0 = <&main_mcan16_pins_default 426 pinctrl-0 = <&main_mcan16_pins_default>;
428 pinctrl-names = "default"; 427 pinctrl-names = "default";
429 phys = <&transceiver0>; 428 phys = <&transceiver0>;
430 }; 429 };
431 430
432 &ospi0 { 431 &ospi0 {
433 status = "okay"; 432 status = "okay";
434 pinctrl-names = "default"; 433 pinctrl-names = "default";
435 pinctrl-0 = <&mcu_fss0_ospi0_pins_defa 434 pinctrl-0 = <&mcu_fss0_ospi0_pins_default>;
436 435
437 flash@0 { 436 flash@0 {
438 compatible = "jedec,spi-nor"; 437 compatible = "jedec,spi-nor";
439 reg = <0x0>; 438 reg = <0x0>;
440 spi-tx-bus-width = <8>; 439 spi-tx-bus-width = <8>;
441 spi-rx-bus-width = <8>; 440 spi-rx-bus-width = <8>;
442 spi-max-frequency = <25000000> 441 spi-max-frequency = <25000000>;
443 cdns,tshsl-ns = <60>; 442 cdns,tshsl-ns = <60>;
444 cdns,tsd2d-ns = <60>; 443 cdns,tsd2d-ns = <60>;
445 cdns,tchsh-ns = <60>; 444 cdns,tchsh-ns = <60>;
446 cdns,tslch-ns = <60>; 445 cdns,tslch-ns = <60>;
447 cdns,read-delay = <4>; 446 cdns,read-delay = <4>;
448 }; 447 };
449 }; 448 };
450 449
451 &mailbox0_cluster0 { 450 &mailbox0_cluster0 {
452 status = "okay"; 451 status = "okay";
453 interrupts = <436>; 452 interrupts = <436>;
454 mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0 453 mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 {
455 ti,mbox-rx = <0 0 0>; 454 ti,mbox-rx = <0 0 0>;
456 ti,mbox-tx = <1 0 0>; 455 ti,mbox-tx = <1 0 0>;
457 }; 456 };
458 457
459 mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0 458 mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 {
460 ti,mbox-rx = <2 0 0>; 459 ti,mbox-rx = <2 0 0>;
461 ti,mbox-tx = <3 0 0>; 460 ti,mbox-tx = <3 0 0>;
462 }; 461 };
463 }; 462 };
464 463
465 &mailbox0_cluster1 { 464 &mailbox0_cluster1 {
466 status = "okay"; 465 status = "okay";
467 interrupts = <432>; 466 interrupts = <432>;
468 mbox_main_r5fss0_core0: mbox-main-r5fs 467 mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
469 ti,mbox-rx = <0 0 0>; 468 ti,mbox-rx = <0 0 0>;
470 ti,mbox-tx = <1 0 0>; 469 ti,mbox-tx = <1 0 0>;
471 }; 470 };
472 471
473 mbox_main_r5fss0_core1: mbox-main-r5fs 472 mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 {
474 ti,mbox-rx = <2 0 0>; 473 ti,mbox-rx = <2 0 0>;
475 ti,mbox-tx = <3 0 0>; 474 ti,mbox-tx = <3 0 0>;
476 }; 475 };
477 }; 476 };
478 477
479 &mailbox0_cluster2 { 478 &mailbox0_cluster2 {
480 status = "okay"; 479 status = "okay";
481 interrupts = <428>; 480 interrupts = <428>;
482 mbox_main_r5fss1_core0: mbox-main-r5fs 481 mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 {
483 ti,mbox-rx = <0 0 0>; 482 ti,mbox-rx = <0 0 0>;
484 ti,mbox-tx = <1 0 0>; 483 ti,mbox-tx = <1 0 0>;
485 }; 484 };
486 485
487 mbox_main_r5fss1_core1: mbox-main-r5fs 486 mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 {
488 ti,mbox-rx = <2 0 0>; 487 ti,mbox-rx = <2 0 0>;
489 ti,mbox-tx = <3 0 0>; 488 ti,mbox-tx = <3 0 0>;
490 }; 489 };
491 }; 490 };
492 491
493 &mailbox0_cluster4 { 492 &mailbox0_cluster4 {
494 status = "okay"; 493 status = "okay";
495 interrupts = <420>; 494 interrupts = <420>;
496 mbox_c71_0: mbox-c71-0 { 495 mbox_c71_0: mbox-c71-0 {
497 ti,mbox-rx = <0 0 0>; 496 ti,mbox-rx = <0 0 0>;
498 ti,mbox-tx = <1 0 0>; 497 ti,mbox-tx = <1 0 0>;
499 }; 498 };
500 499
501 mbox_c71_1: mbox-c71-1 { 500 mbox_c71_1: mbox-c71-1 {
502 ti,mbox-rx = <2 0 0>; 501 ti,mbox-rx = <2 0 0>;
503 ti,mbox-tx = <3 0 0>; 502 ti,mbox-tx = <3 0 0>;
504 }; 503 };
505 }; 504 };
506 505
507 &mcu_r5fss0_core0 { 506 &mcu_r5fss0_core0 {
508 mboxes = <&mailbox0_cluster0 &mbox_mcu 507 mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>;
509 memory-region = <&mcu_r5fss0_core0_dma 508 memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
510 <&mcu_r5fss0_core0_mem 509 <&mcu_r5fss0_core0_memory_region>;
511 }; 510 };
512 511
513 &mcu_r5fss0_core1 { 512 &mcu_r5fss0_core1 {
514 mboxes = <&mailbox0_cluster0 &mbox_mcu 513 mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>;
515 memory-region = <&mcu_r5fss0_core1_dma 514 memory-region = <&mcu_r5fss0_core1_dma_memory_region>,
516 <&mcu_r5fss0_core1_mem 515 <&mcu_r5fss0_core1_memory_region>;
517 }; <<
518 <<
519 &main_r5fss0 { <<
520 ti,cluster-mode = <0>; <<
521 }; <<
522 <<
523 &main_r5fss1 { <<
524 ti,cluster-mode = <0>; <<
525 }; <<
526 <<
527 /* Timers are used by Remoteproc firmware */ <<
528 &main_timer0 { <<
529 status = "reserved"; <<
530 }; <<
531 <<
532 &main_timer1 { <<
533 status = "reserved"; <<
534 }; <<
535 <<
536 &main_timer2 { <<
537 status = "reserved"; <<
538 }; <<
539 <<
540 &main_timer3 { <<
541 status = "reserved"; <<
542 }; <<
543 <<
544 &main_timer4 { <<
545 status = "reserved"; <<
546 }; <<
547 <<
548 &main_timer5 { <<
549 status = "reserved"; <<
550 }; 516 };
551 517
552 &main_r5fss0_core0 { 518 &main_r5fss0_core0 {
553 mboxes = <&mailbox0_cluster1 &mbox_mai 519 mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>;
554 memory-region = <&main_r5fss0_core0_dm 520 memory-region = <&main_r5fss0_core0_dma_memory_region>,
555 <&main_r5fss0_core0_me 521 <&main_r5fss0_core0_memory_region>;
556 }; 522 };
557 523
558 &main_r5fss0_core1 { 524 &main_r5fss0_core1 {
559 mboxes = <&mailbox0_cluster1 &mbox_mai 525 mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>;
560 memory-region = <&main_r5fss0_core1_dm 526 memory-region = <&main_r5fss0_core1_dma_memory_region>,
561 <&main_r5fss0_core1_me 527 <&main_r5fss0_core1_memory_region>;
562 }; 528 };
563 529
564 &main_r5fss1_core0 { 530 &main_r5fss1_core0 {
565 mboxes = <&mailbox0_cluster2 &mbox_mai 531 mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core0>;
566 memory-region = <&main_r5fss1_core0_dm 532 memory-region = <&main_r5fss1_core0_dma_memory_region>,
567 <&main_r5fss1_core0_me 533 <&main_r5fss1_core0_memory_region>;
568 }; 534 };
569 535
570 &main_r5fss1_core1 { 536 &main_r5fss1_core1 {
571 mboxes = <&mailbox0_cluster2 &mbox_mai 537 mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core1>;
572 memory-region = <&main_r5fss1_core1_dm 538 memory-region = <&main_r5fss1_core1_dma_memory_region>,
573 <&main_r5fss1_core1_me 539 <&main_r5fss1_core1_memory_region>;
574 }; 540 };
575 541
576 &c71_0 { 542 &c71_0 {
577 status = "okay"; 543 status = "okay";
578 mboxes = <&mailbox0_cluster4 &mbox_c71 544 mboxes = <&mailbox0_cluster4 &mbox_c71_0>;
579 memory-region = <&c71_0_dma_memory_reg 545 memory-region = <&c71_0_dma_memory_region>,
580 <&c71_0_memory_region> 546 <&c71_0_memory_region>;
581 }; 547 };
582 548
583 &c71_1 { 549 &c71_1 {
584 status = "okay"; 550 status = "okay";
585 mboxes = <&mailbox0_cluster4 &mbox_c71 551 mboxes = <&mailbox0_cluster4 &mbox_c71_1>;
586 memory-region = <&c71_1_dma_memory_reg 552 memory-region = <&c71_1_dma_memory_region>,
587 <&c71_1_memory_region> 553 <&c71_1_memory_region>;
588 }; 554 };
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