1 // SPDX-License-Identifier: GPL-2.0-only OR MI
2 /*
3 * Device Tree file for the J722S MAIN domain
4 *
5 * Copyright (C) 2023-2024 Texas Instruments I
6 */
7
8 #include <dt-bindings/phy/phy-cadence.h>
9 #include <dt-bindings/phy/phy-ti.h>
10
11 / {
12 serdes_refclk: clk-0 {
13 compatible = "fixed-clock";
14 #clock-cells = <0>;
15 clock-frequency = <0>;
16 };
17 };
18
19 &cbass_main {
20 serdes_wiz0: phy@f000000 {
21 compatible = "ti,am64-wiz-10g"
22 ranges = <0x0f000000 0x0 0x0f0
23 #address-cells = <1>;
24 #size-cells = <1>;
25 power-domains = <&k3_pds 279 T
26 clocks = <&k3_clks 279 0>, <&k
27 clock-names = "fck", "core_ref
28 num-lanes = <1>;
29 #reset-cells = <1>;
30 #clock-cells = <1>;
31
32 assigned-clocks = <&k3_clks 27
33 assigned-clock-parents = <&k3_
34
35 serdes0: serdes@f000000 {
36 compatible = "ti,j721e
37 reg = <0x0f000000 0x00
38 reg-names = "torrent_p
39 resets = <&serdes_wiz0
40 reset-names = "torrent
41 clocks = <&serdes_wiz0
42 <&serdes_wiz0
43 clock-names = "refclk"
44 assigned-clocks = <&se
45 <&se
46 <&se
47 assigned-clock-parents
48
49
50 #address-cells = <1>;
51 #size-cells = <0>;
52 #clock-cells = <1>;
53
54 status = "disabled"; /
55 };
56 };
57
58 serdes_wiz1: phy@f010000 {
59 compatible = "ti,am64-wiz-10g"
60 ranges = <0x0f010000 0x0 0x0f0
61 #address-cells = <1>;
62 #size-cells = <1>;
63 power-domains = <&k3_pds 280 T
64 clocks = <&k3_clks 280 0>, <&k
65 clock-names = "fck", "core_ref
66 num-lanes = <1>;
67 #reset-cells = <1>;
68 #clock-cells = <1>;
69
70 assigned-clocks = <&k3_clks 28
71 assigned-clock-parents = <&k3_
72
73 serdes1: serdes@f010000 {
74 compatible = "ti,j721e
75 reg = <0x0f010000 0x00
76 reg-names = "torrent_p
77 resets = <&serdes_wiz1
78 reset-names = "torrent
79 clocks = <&serdes_wiz1
80 <&serdes_wiz1
81 clock-names = "refclk"
82 assigned-clocks = <&se
83 <&se
84 <&se
85 assigned-clock-parents
86
87
88 #address-cells = <1>;
89 #size-cells = <0>;
90 #clock-cells = <1>;
91
92 status = "disabled"; /
93 };
94 };
95
96 pcie0_rc: pcie@f102000 {
97 compatible = "ti,j722s-pcie-ho
98 reg = <0x00 0x0f102000 0x00 0x
99 <0x00 0x0f100000 0x00 0x
100 <0x00 0x0d000000 0x00 0x
101 <0x00 0x68000000 0x00 0x
102 reg-names = "intd_cfg", "user_
103 ranges = <0x01000000 0x00 0x68
104 <0x02000000 0x00 0x68
105 dma-ranges = <0x02000000 0x0 0
106 interrupt-names = "link_state"
107 interrupts = <GIC_SPI 99 IRQ_T
108 device_type = "pci";
109 max-link-speed = <3>;
110 num-lanes = <1>;
111 power-domains = <&k3_pds 259 T
112 clocks = <&k3_clks 259 0>, <&s
113 clock-names = "fck", "pcie_ref
114 #address-cells = <3>;
115 #size-cells = <2>;
116 bus-range = <0x0 0xff>;
117 vendor-id = <0x104c>;
118 device-id = <0xb010>;
119 cdns,no-bar-match-nbits = <64>
120 ti,syscon-pcie-ctrl = <&pcie0_
121 msi-map = <0x0 &gic_its 0x0 0x
122 status = "disabled";
123 };
124
125 usbss1: usb@f920000 {
126 compatible = "ti,j721e-usb";
127 reg = <0x00 0x0f920000 0x00 0x
128 power-domains = <&k3_pds 278 T
129 clocks = <&k3_clks 278 3>, <&k
130 clock-names = "ref", "lpm";
131 assigned-clocks = <&k3_clks 27
132 assigned-clock-parents = <&k3_
133 #address-cells = <2>;
134 #size-cells = <2>;
135 ranges;
136 status = "disabled";
137
138 usb1: usb@31200000{
139 compatible = "cdns,usb
140 reg = <0x00 0x31200000
141 <0x00 0x31210000
142 <0x00 0x31220000
143 reg-names = "otg",
144 "xhci",
145 "dev";
146 interrupts = <GIC_SPI
147 <GIC_SPI
148 <GIC_SPI
149 interrupt-names = "hos
150 "per
151 "otg
152 maximum-speed = "super
153 dr_mode = "otg";
154 };
155 };
156
157 main_r5fss0: r5fss@78400000 {
158 compatible = "ti,am62-r5fss";
159 #address-cells = <1>;
160 #size-cells = <1>;
161 ranges = <0x78400000 0x00 0x78
162 <0x78500000 0x00 0x78
163 power-domains = <&k3_pds 261 T
164 status = "disabled";
165
166 main_r5fss0_core0: r5f@7840000
167 compatible = "ti,am62-
168 reg = <0x78400000 0x00
169 <0x78500000 0x00
170 reg-names = "atcm", "b
171 resets = <&k3_reset 26
172 firmware-name = "j722s
173 ti,sci = <&dmsc>;
174 ti,sci-dev-id = <262>;
175 ti,sci-proc-ids = <0x0
176 ti,atcm-enable = <1>;
177 ti,btcm-enable = <1>;
178 ti,loczrama = <1>;
179 };
180 };
181
182 c7x_0: dsp@7e000000 {
183 compatible = "ti,am62a-c7xv-ds
184 reg = <0x00 0x7e000000 0x00 0x
185 reg-names = "l2sram";
186 resets = <&k3_reset 208 1>;
187 firmware-name = "j722s-c71_0-f
188 ti,sci = <&dmsc>;
189 ti,sci-dev-id = <208>;
190 ti,sci-proc-ids = <0x30 0xff>;
191 status = "disabled";
192 };
193
194 c7x_1: dsp@7e200000 {
195 compatible = "ti,am62a-c7xv-ds
196 reg = <0x00 0x7e200000 0x00 0x
197 reg-names = "l2sram";
198 resets = <&k3_reset 268 1>;
199 firmware-name = "j722s-c71_1-f
200 ti,sci = <&dmsc>;
201 ti,sci-dev-id = <268>;
202 ti,sci-proc-ids = <0x31 0xff>;
203 status = "disabled";
204 };
205 };
206
207 /* MCU domain overrides */
208
209 &mcu_r5fss0_core0 {
210 firmware-name = "j722s-mcu-r5f0_0-fw";
211 };
212
213 /* Wakeup domain overrides */
214
215 &wkup_r5fss0_core0 {
216 firmware-name = "j722s-wkup-r5f0_0-fw"
217 };
218
219 &main_conf {
220 serdes_ln_ctrl: mux-controller@4080 {
221 compatible = "reg-mux";
222 reg = <0x4080 0x14>;
223 #mux-control-cells = <1>;
224 mux-reg-masks = <0x00 0x3>, /*
225 <0x10 0x3>; /*
226 };
227
228 audio_refclk1: clock@82e4 {
229 compatible = "ti,am62-audio-re
230 reg = <0x82e4 0x4>;
231 clocks = <&k3_clks 157 18>;
232 assigned-clocks = <&k3_clks 15
233 assigned-clock-parents = <&k3_
234 #clock-cells = <0>;
235 };
236 };
237
238 &wkup_conf {
239 pcie0_ctrl: pcie0-ctrl@4070 {
240 compatible = "ti,j784s4-pcie-c
241 reg = <0x4070 0x4>;
242 };
243 };
244
245 &oc_sram {
246 reg = <0x00 0x70000000 0x00 0x40000>;
247 ranges = <0x00 0x00 0x70000000 0x40000
248 };
249
250 &inta_main_dmss {
251 ti,interrupt-ranges = <7 71 21>;
252 };
253
254 &main_pmx0 {
255 pinctrl-single,gpio-range =
256 <&main_pmx0_range 0 32 PIN_GPI
257 <&main_pmx0_range 33 38 PIN_GP
258 <&main_pmx0_range 72 17 PIN_GP
259 <&main_pmx0_range 101 25 PIN_G
260 <&main_pmx0_range 137 5 PIN_GP
261 <&main_pmx0_range 143 3 PIN_GP
262 <&main_pmx0_range 149 2 PIN_GP
263
264 main_pmx0_range: gpio-range {
265 #pinctrl-single,gpio-range-cel
266 };
267 };
268
269 &main_gpio0 {
270 gpio-ranges = <&main_pmx0 0 0 32>, <&m
271 <&main_pmx0 70 72 17>;
272 ti,ngpio = <87>;
273 };
274
275 &main_gpio1 {
276 gpio-ranges = <&main_pmx0 7 101 25>, <
277 <&main_pmx0 47 143 3>,
278 gpio-reserved-ranges = <0 7>, <32 10>;
279 ti,ngpio = <73>;
280 };
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