1 // SPDX-License-Identifier: GPL-2.0-only OR MI 1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
2 /* 2 /*
3 * Device Tree file for the J722S MAIN domain 3 * Device Tree file for the J722S MAIN domain peripherals
4 * 4 *
5 * Copyright (C) 2023-2024 Texas Instruments I 5 * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/
6 */ 6 */
7 7
8 #include <dt-bindings/phy/phy-cadence.h> 8 #include <dt-bindings/phy/phy-cadence.h>
9 #include <dt-bindings/phy/phy-ti.h> 9 #include <dt-bindings/phy/phy-ti.h>
10 10
11 / { 11 / {
12 serdes_refclk: clk-0 { 12 serdes_refclk: clk-0 {
13 compatible = "fixed-clock"; 13 compatible = "fixed-clock";
14 #clock-cells = <0>; 14 #clock-cells = <0>;
15 clock-frequency = <0>; 15 clock-frequency = <0>;
16 }; 16 };
17 }; 17 };
18 18
19 &cbass_main { 19 &cbass_main {
20 serdes_wiz0: phy@f000000 { 20 serdes_wiz0: phy@f000000 {
21 compatible = "ti,am64-wiz-10g" 21 compatible = "ti,am64-wiz-10g";
22 ranges = <0x0f000000 0x0 0x0f0 22 ranges = <0x0f000000 0x0 0x0f000000 0x00010000>;
23 #address-cells = <1>; 23 #address-cells = <1>;
24 #size-cells = <1>; 24 #size-cells = <1>;
25 power-domains = <&k3_pds 279 T 25 power-domains = <&k3_pds 279 TI_SCI_PD_EXCLUSIVE>;
26 clocks = <&k3_clks 279 0>, <&k 26 clocks = <&k3_clks 279 0>, <&k3_clks 279 1>, <&serdes_refclk>;
27 clock-names = "fck", "core_ref 27 clock-names = "fck", "core_ref_clk", "ext_ref_clk";
28 num-lanes = <1>; 28 num-lanes = <1>;
29 #reset-cells = <1>; 29 #reset-cells = <1>;
30 #clock-cells = <1>; 30 #clock-cells = <1>;
31 31
32 assigned-clocks = <&k3_clks 27 32 assigned-clocks = <&k3_clks 279 1>;
33 assigned-clock-parents = <&k3_ 33 assigned-clock-parents = <&k3_clks 279 5>;
34 34
35 serdes0: serdes@f000000 { 35 serdes0: serdes@f000000 {
36 compatible = "ti,j721e 36 compatible = "ti,j721e-serdes-10g";
37 reg = <0x0f000000 0x00 37 reg = <0x0f000000 0x00010000>;
38 reg-names = "torrent_p 38 reg-names = "torrent_phy";
39 resets = <&serdes_wiz0 39 resets = <&serdes_wiz0 0>;
40 reset-names = "torrent 40 reset-names = "torrent_reset";
41 clocks = <&serdes_wiz0 41 clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>,
42 <&serdes_wiz0 42 <&serdes_wiz0 TI_WIZ_PHY_EN_REFCLK>;
43 clock-names = "refclk" 43 clock-names = "refclk", "phy_en_refclk";
44 assigned-clocks = <&se 44 assigned-clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>,
45 <&se 45 <&serdes_wiz0 TI_WIZ_PLL1_REFCLK>,
46 <&se 46 <&serdes_wiz0 TI_WIZ_REFCLK_DIG>;
47 assigned-clock-parents 47 assigned-clock-parents = <&k3_clks 279 1>,
48 48 <&k3_clks 279 1>,
49 49 <&k3_clks 279 1>;
50 #address-cells = <1>; 50 #address-cells = <1>;
51 #size-cells = <0>; 51 #size-cells = <0>;
52 #clock-cells = <1>; 52 #clock-cells = <1>;
53 53
54 status = "disabled"; / 54 status = "disabled"; /* Needs lane config */
55 }; 55 };
56 }; 56 };
57 57
58 serdes_wiz1: phy@f010000 { 58 serdes_wiz1: phy@f010000 {
59 compatible = "ti,am64-wiz-10g" 59 compatible = "ti,am64-wiz-10g";
60 ranges = <0x0f010000 0x0 0x0f0 60 ranges = <0x0f010000 0x0 0x0f010000 0x00010000>;
61 #address-cells = <1>; 61 #address-cells = <1>;
62 #size-cells = <1>; 62 #size-cells = <1>;
63 power-domains = <&k3_pds 280 T 63 power-domains = <&k3_pds 280 TI_SCI_PD_EXCLUSIVE>;
64 clocks = <&k3_clks 280 0>, <&k 64 clocks = <&k3_clks 280 0>, <&k3_clks 280 1>, <&serdes_refclk>;
65 clock-names = "fck", "core_ref 65 clock-names = "fck", "core_ref_clk", "ext_ref_clk";
66 num-lanes = <1>; 66 num-lanes = <1>;
67 #reset-cells = <1>; 67 #reset-cells = <1>;
68 #clock-cells = <1>; 68 #clock-cells = <1>;
69 69
70 assigned-clocks = <&k3_clks 28 70 assigned-clocks = <&k3_clks 280 1>;
71 assigned-clock-parents = <&k3_ 71 assigned-clock-parents = <&k3_clks 280 5>;
72 72
73 serdes1: serdes@f010000 { 73 serdes1: serdes@f010000 {
74 compatible = "ti,j721e 74 compatible = "ti,j721e-serdes-10g";
75 reg = <0x0f010000 0x00 75 reg = <0x0f010000 0x00010000>;
76 reg-names = "torrent_p 76 reg-names = "torrent_phy";
77 resets = <&serdes_wiz1 77 resets = <&serdes_wiz1 0>;
78 reset-names = "torrent 78 reset-names = "torrent_reset";
79 clocks = <&serdes_wiz1 79 clocks = <&serdes_wiz1 TI_WIZ_PLL0_REFCLK>,
80 <&serdes_wiz1 80 <&serdes_wiz1 TI_WIZ_PHY_EN_REFCLK>;
81 clock-names = "refclk" 81 clock-names = "refclk", "phy_en_refclk";
82 assigned-clocks = <&se 82 assigned-clocks = <&serdes_wiz1 TI_WIZ_PLL0_REFCLK>,
83 <&se 83 <&serdes_wiz1 TI_WIZ_PLL1_REFCLK>,
84 <&se 84 <&serdes_wiz1 TI_WIZ_REFCLK_DIG>;
85 assigned-clock-parents 85 assigned-clock-parents = <&k3_clks 280 1>,
86 86 <&k3_clks 280 1>,
87 87 <&k3_clks 280 1>;
88 #address-cells = <1>; 88 #address-cells = <1>;
89 #size-cells = <0>; 89 #size-cells = <0>;
90 #clock-cells = <1>; 90 #clock-cells = <1>;
91 91
92 status = "disabled"; / 92 status = "disabled"; /* Needs lane config */
93 }; 93 };
94 }; 94 };
95 95
96 pcie0_rc: pcie@f102000 { 96 pcie0_rc: pcie@f102000 {
97 compatible = "ti,j722s-pcie-ho 97 compatible = "ti,j722s-pcie-host", "ti,j721e-pcie-host";
98 reg = <0x00 0x0f102000 0x00 0x 98 reg = <0x00 0x0f102000 0x00 0x1000>,
99 <0x00 0x0f100000 0x00 0x 99 <0x00 0x0f100000 0x00 0x400>,
100 <0x00 0x0d000000 0x00 0x 100 <0x00 0x0d000000 0x00 0x00800000>,
101 <0x00 0x68000000 0x00 0x 101 <0x00 0x68000000 0x00 0x00001000>;
102 reg-names = "intd_cfg", "user_ 102 reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
103 ranges = <0x01000000 0x00 0x68 103 ranges = <0x01000000 0x00 0x68001000 0x00 0x68001000 0x00 0x0010000>,
104 <0x02000000 0x00 0x68 104 <0x02000000 0x00 0x68011000 0x00 0x68011000 0x00 0x7fef000>;
105 dma-ranges = <0x02000000 0x0 0 105 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
106 interrupt-names = "link_state" 106 interrupt-names = "link_state";
107 interrupts = <GIC_SPI 99 IRQ_T 107 interrupts = <GIC_SPI 99 IRQ_TYPE_EDGE_RISING>;
108 device_type = "pci"; 108 device_type = "pci";
109 max-link-speed = <3>; 109 max-link-speed = <3>;
110 num-lanes = <1>; 110 num-lanes = <1>;
111 power-domains = <&k3_pds 259 T 111 power-domains = <&k3_pds 259 TI_SCI_PD_EXCLUSIVE>;
112 clocks = <&k3_clks 259 0>, <&s 112 clocks = <&k3_clks 259 0>, <&serdes1 CDNS_TORRENT_REFCLK_DRIVER>;
113 clock-names = "fck", "pcie_ref 113 clock-names = "fck", "pcie_refclk";
114 #address-cells = <3>; 114 #address-cells = <3>;
115 #size-cells = <2>; 115 #size-cells = <2>;
116 bus-range = <0x0 0xff>; 116 bus-range = <0x0 0xff>;
117 vendor-id = <0x104c>; 117 vendor-id = <0x104c>;
118 device-id = <0xb010>; 118 device-id = <0xb010>;
119 cdns,no-bar-match-nbits = <64> 119 cdns,no-bar-match-nbits = <64>;
120 ti,syscon-pcie-ctrl = <&pcie0_ 120 ti,syscon-pcie-ctrl = <&pcie0_ctrl 0x0>;
121 msi-map = <0x0 &gic_its 0x0 0x 121 msi-map = <0x0 &gic_its 0x0 0x10000>;
122 status = "disabled"; 122 status = "disabled";
123 }; 123 };
124 124
125 usbss1: usb@f920000 { 125 usbss1: usb@f920000 {
126 compatible = "ti,j721e-usb"; 126 compatible = "ti,j721e-usb";
127 reg = <0x00 0x0f920000 0x00 0x 127 reg = <0x00 0x0f920000 0x00 0x100>;
128 power-domains = <&k3_pds 278 T 128 power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>;
129 clocks = <&k3_clks 278 3>, <&k 129 clocks = <&k3_clks 278 3>, <&k3_clks 278 1>;
130 clock-names = "ref", "lpm"; 130 clock-names = "ref", "lpm";
131 assigned-clocks = <&k3_clks 27 131 assigned-clocks = <&k3_clks 278 3>; /* USB2_REFCLK */
132 assigned-clock-parents = <&k3_ 132 assigned-clock-parents = <&k3_clks 278 4>; /* HF0SC0 */
133 #address-cells = <2>; 133 #address-cells = <2>;
134 #size-cells = <2>; 134 #size-cells = <2>;
135 ranges; 135 ranges;
136 status = "disabled"; 136 status = "disabled";
137 137
138 usb1: usb@31200000{ 138 usb1: usb@31200000{
139 compatible = "cdns,usb 139 compatible = "cdns,usb3";
140 reg = <0x00 0x31200000 140 reg = <0x00 0x31200000 0x00 0x10000>,
141 <0x00 0x31210000 141 <0x00 0x31210000 0x00 0x10000>,
142 <0x00 0x31220000 142 <0x00 0x31220000 0x00 0x10000>;
143 reg-names = "otg", 143 reg-names = "otg",
144 "xhci", 144 "xhci",
145 "dev"; 145 "dev";
146 interrupts = <GIC_SPI 146 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */
147 <GIC_SPI 147 <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>, /* irq.6 */
148 <GIC_SPI 148 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>; /* otgirq */
149 interrupt-names = "hos 149 interrupt-names = "host",
150 "per 150 "peripheral",
151 "otg 151 "otg";
152 maximum-speed = "super 152 maximum-speed = "super-speed";
153 dr_mode = "otg"; 153 dr_mode = "otg";
154 }; 154 };
155 }; 155 };
156 156
157 main_r5fss0: r5fss@78400000 { 157 main_r5fss0: r5fss@78400000 {
158 compatible = "ti,am62-r5fss"; 158 compatible = "ti,am62-r5fss";
159 #address-cells = <1>; 159 #address-cells = <1>;
160 #size-cells = <1>; 160 #size-cells = <1>;
161 ranges = <0x78400000 0x00 0x78 161 ranges = <0x78400000 0x00 0x78400000 0x8000>,
162 <0x78500000 0x00 0x78 162 <0x78500000 0x00 0x78500000 0x8000>;
163 power-domains = <&k3_pds 261 T 163 power-domains = <&k3_pds 261 TI_SCI_PD_EXCLUSIVE>;
164 status = "disabled"; 164 status = "disabled";
165 165
166 main_r5fss0_core0: r5f@7840000 166 main_r5fss0_core0: r5f@78400000 {
167 compatible = "ti,am62- 167 compatible = "ti,am62-r5f";
168 reg = <0x78400000 0x00 168 reg = <0x78400000 0x00008000>,
169 <0x78500000 0x00 169 <0x78500000 0x00008000>;
170 reg-names = "atcm", "b 170 reg-names = "atcm", "btcm";
171 resets = <&k3_reset 26 171 resets = <&k3_reset 262 1>;
172 firmware-name = "j722s 172 firmware-name = "j722s-main-r5f0_0-fw";
173 ti,sci = <&dmsc>; 173 ti,sci = <&dmsc>;
174 ti,sci-dev-id = <262>; 174 ti,sci-dev-id = <262>;
175 ti,sci-proc-ids = <0x0 175 ti,sci-proc-ids = <0x04 0xff>;
176 ti,atcm-enable = <1>; 176 ti,atcm-enable = <1>;
177 ti,btcm-enable = <1>; 177 ti,btcm-enable = <1>;
178 ti,loczrama = <1>; 178 ti,loczrama = <1>;
179 }; 179 };
180 }; 180 };
181 181
182 c7x_0: dsp@7e000000 { 182 c7x_0: dsp@7e000000 {
183 compatible = "ti,am62a-c7xv-ds 183 compatible = "ti,am62a-c7xv-dsp";
184 reg = <0x00 0x7e000000 0x00 0x 184 reg = <0x00 0x7e000000 0x00 0x00200000>;
185 reg-names = "l2sram"; 185 reg-names = "l2sram";
186 resets = <&k3_reset 208 1>; 186 resets = <&k3_reset 208 1>;
187 firmware-name = "j722s-c71_0-f 187 firmware-name = "j722s-c71_0-fw";
188 ti,sci = <&dmsc>; 188 ti,sci = <&dmsc>;
189 ti,sci-dev-id = <208>; 189 ti,sci-dev-id = <208>;
190 ti,sci-proc-ids = <0x30 0xff>; 190 ti,sci-proc-ids = <0x30 0xff>;
191 status = "disabled"; 191 status = "disabled";
192 }; 192 };
193 193
194 c7x_1: dsp@7e200000 { 194 c7x_1: dsp@7e200000 {
195 compatible = "ti,am62a-c7xv-ds 195 compatible = "ti,am62a-c7xv-dsp";
196 reg = <0x00 0x7e200000 0x00 0x 196 reg = <0x00 0x7e200000 0x00 0x00200000>;
197 reg-names = "l2sram"; 197 reg-names = "l2sram";
198 resets = <&k3_reset 268 1>; 198 resets = <&k3_reset 268 1>;
199 firmware-name = "j722s-c71_1-f 199 firmware-name = "j722s-c71_1-fw";
200 ti,sci = <&dmsc>; 200 ti,sci = <&dmsc>;
201 ti,sci-dev-id = <268>; 201 ti,sci-dev-id = <268>;
202 ti,sci-proc-ids = <0x31 0xff>; 202 ti,sci-proc-ids = <0x31 0xff>;
203 status = "disabled"; 203 status = "disabled";
204 }; 204 };
205 }; 205 };
206 206
207 /* MCU domain overrides */ 207 /* MCU domain overrides */
208 208
209 &mcu_r5fss0_core0 { 209 &mcu_r5fss0_core0 {
210 firmware-name = "j722s-mcu-r5f0_0-fw"; 210 firmware-name = "j722s-mcu-r5f0_0-fw";
211 }; 211 };
212 212
213 /* Wakeup domain overrides */ 213 /* Wakeup domain overrides */
214 214
215 &wkup_r5fss0_core0 { 215 &wkup_r5fss0_core0 {
216 firmware-name = "j722s-wkup-r5f0_0-fw" 216 firmware-name = "j722s-wkup-r5f0_0-fw";
217 }; 217 };
218 218
219 &main_conf { 219 &main_conf {
220 serdes_ln_ctrl: mux-controller@4080 { 220 serdes_ln_ctrl: mux-controller@4080 {
221 compatible = "reg-mux"; 221 compatible = "reg-mux";
222 reg = <0x4080 0x14>; 222 reg = <0x4080 0x14>;
223 #mux-control-cells = <1>; 223 #mux-control-cells = <1>;
224 mux-reg-masks = <0x00 0x3>, /* 224 mux-reg-masks = <0x00 0x3>, /* SERDES0 lane0 select */
225 <0x10 0x3>; /* 225 <0x10 0x3>; /* SERDES1 lane0 select */
226 }; 226 };
227 227
228 audio_refclk1: clock@82e4 { 228 audio_refclk1: clock@82e4 {
229 compatible = "ti,am62-audio-re 229 compatible = "ti,am62-audio-refclk";
230 reg = <0x82e4 0x4>; 230 reg = <0x82e4 0x4>;
231 clocks = <&k3_clks 157 18>; 231 clocks = <&k3_clks 157 18>;
232 assigned-clocks = <&k3_clks 15 232 assigned-clocks = <&k3_clks 157 18>;
233 assigned-clock-parents = <&k3_ 233 assigned-clock-parents = <&k3_clks 157 33>;
234 #clock-cells = <0>; 234 #clock-cells = <0>;
235 }; 235 };
236 }; 236 };
237 237
238 &wkup_conf { 238 &wkup_conf {
239 pcie0_ctrl: pcie0-ctrl@4070 { 239 pcie0_ctrl: pcie0-ctrl@4070 {
240 compatible = "ti,j784s4-pcie-c 240 compatible = "ti,j784s4-pcie-ctrl", "syscon";
241 reg = <0x4070 0x4>; 241 reg = <0x4070 0x4>;
242 }; 242 };
243 }; 243 };
244 244
245 &oc_sram { 245 &oc_sram {
246 reg = <0x00 0x70000000 0x00 0x40000>; 246 reg = <0x00 0x70000000 0x00 0x40000>;
247 ranges = <0x00 0x00 0x70000000 0x40000 247 ranges = <0x00 0x00 0x70000000 0x40000>;
248 }; 248 };
249 249
250 &inta_main_dmss { 250 &inta_main_dmss {
251 ti,interrupt-ranges = <7 71 21>; 251 ti,interrupt-ranges = <7 71 21>;
252 }; 252 };
253 253
254 &main_pmx0 { 254 &main_pmx0 {
255 pinctrl-single,gpio-range = 255 pinctrl-single,gpio-range =
256 <&main_pmx0_range 0 32 PIN_GPI 256 <&main_pmx0_range 0 32 PIN_GPIO_RANGE_IOPAD>,
257 <&main_pmx0_range 33 38 PIN_GP 257 <&main_pmx0_range 33 38 PIN_GPIO_RANGE_IOPAD>,
258 <&main_pmx0_range 72 17 PIN_GP 258 <&main_pmx0_range 72 17 PIN_GPIO_RANGE_IOPAD>,
259 <&main_pmx0_range 101 25 PIN_G 259 <&main_pmx0_range 101 25 PIN_GPIO_RANGE_IOPAD>,
260 <&main_pmx0_range 137 5 PIN_GP 260 <&main_pmx0_range 137 5 PIN_GPIO_RANGE_IOPAD>,
261 <&main_pmx0_range 143 3 PIN_GP 261 <&main_pmx0_range 143 3 PIN_GPIO_RANGE_IOPAD>,
262 <&main_pmx0_range 149 2 PIN_GP 262 <&main_pmx0_range 149 2 PIN_GPIO_RANGE_IOPAD>;
263 263
264 main_pmx0_range: gpio-range { 264 main_pmx0_range: gpio-range {
265 #pinctrl-single,gpio-range-cel 265 #pinctrl-single,gpio-range-cells = <3>;
266 }; 266 };
267 }; 267 };
268 268
269 &main_gpio0 { 269 &main_gpio0 {
270 gpio-ranges = <&main_pmx0 0 0 32>, <&m 270 gpio-ranges = <&main_pmx0 0 0 32>, <&main_pmx0 32 33 38>,
271 <&main_pmx0 70 72 17>; 271 <&main_pmx0 70 72 17>;
272 ti,ngpio = <87>; 272 ti,ngpio = <87>;
273 }; 273 };
274 274
275 &main_gpio1 { 275 &main_gpio1 {
276 gpio-ranges = <&main_pmx0 7 101 25>, < 276 gpio-ranges = <&main_pmx0 7 101 25>, <&main_pmx0 42 137 5>,
277 <&main_pmx0 47 143 3>, 277 <&main_pmx0 47 143 3>, <&main_pmx0 50 149 2>;
278 gpio-reserved-ranges = <0 7>, <32 10>; 278 gpio-reserved-ranges = <0 7>, <32 10>;
279 ti,ngpio = <73>; 279 ti,ngpio = <73>;
280 }; 280 };
Linux® is a registered trademark of Linus Torvalds in the United States and other countries.
TOMOYO® is a registered trademark of NTT DATA CORPORATION.