1 // SPDX-License-Identifier: GPL-2.0-only OR MI !! 1 // SPDX-License-Identifier: GPL-2.0
2 /* 2 /*
3 * Device Tree Source for J784S4 SoC Family MC 3 * Device Tree Source for J784S4 SoC Family MCU/WAKEUP Domain peripherals
4 * 4 *
5 * Copyright (C) 2022-2024 Texas Instruments I !! 5 * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
6 */ 6 */
7 7
8 &cbass_mcu_wakeup { 8 &cbass_mcu_wakeup {
9 sms: system-controller@44083000 { 9 sms: system-controller@44083000 {
10 bootph-all; <<
11 compatible = "ti,k2g-sci"; 10 compatible = "ti,k2g-sci";
12 ti,host-id = <12>; 11 ti,host-id = <12>;
13 12
14 mbox-names = "rx", "tx"; 13 mbox-names = "rx", "tx";
15 14
16 mboxes = <&secure_proxy_main 1 15 mboxes = <&secure_proxy_main 11>,
17 <&secure_proxy_main 1 16 <&secure_proxy_main 13>;
18 17
19 reg-names = "debug_messages"; 18 reg-names = "debug_messages";
20 reg = <0x00 0x44083000 0x00 0x 19 reg = <0x00 0x44083000 0x00 0x1000>;
21 20
22 k3_pds: power-controller { 21 k3_pds: power-controller {
23 bootph-all; <<
24 compatible = "ti,sci-p 22 compatible = "ti,sci-pm-domain";
25 #power-domain-cells = 23 #power-domain-cells = <2>;
26 }; 24 };
27 25
28 k3_clks: clock-controller { 26 k3_clks: clock-controller {
29 bootph-all; <<
30 compatible = "ti,k2g-s 27 compatible = "ti,k2g-sci-clk";
31 #clock-cells = <2>; 28 #clock-cells = <2>;
32 }; 29 };
33 30
34 k3_reset: reset-controller { 31 k3_reset: reset-controller {
35 bootph-all; <<
36 compatible = "ti,sci-r 32 compatible = "ti,sci-reset";
37 #reset-cells = <2>; 33 #reset-cells = <2>;
38 }; 34 };
39 }; 35 };
40 36
41 wkup_conf: bus@43000000 { !! 37 chipid@43000014 {
42 bootph-all; !! 38 compatible = "ti,am654-chipid";
43 compatible = "simple-bus"; !! 39 reg = <0x00 0x43000014 0x00 0x4>;
44 #address-cells = <1>; <<
45 #size-cells = <1>; <<
46 ranges = <0x0 0x00 0x43000000 <<
47 <<
48 chipid: chipid@14 { <<
49 bootph-all; <<
50 compatible = "ti,am654 <<
51 reg = <0x14 0x4>; <<
52 }; <<
53 }; <<
54 <<
55 secure_proxy_sa3: mailbox@43600000 { <<
56 compatible = "ti,am654-secure- <<
57 #mbox-cells = <1>; <<
58 reg-names = "target_data", "rt <<
59 reg = <0x00 0x43600000 0x00 0x <<
60 <0x00 0x44880000 0x00 0x <<
61 <0x00 0x44860000 0x00 0x <<
62 /* <<
63 * Marked Disabled: <<
64 * Node is incomplete as it is <<
65 * firmware on non-MPU process <<
66 */ <<
67 status = "disabled"; <<
68 }; 40 };
69 41
70 mcu_ram: sram@41c00000 { 42 mcu_ram: sram@41c00000 {
71 compatible = "mmio-sram"; 43 compatible = "mmio-sram";
72 reg = <0x00 0x41c00000 0x00 0x 44 reg = <0x00 0x41c00000 0x00 0x100000>;
73 ranges = <0x00 0x00 0x41c00000 45 ranges = <0x00 0x00 0x41c00000 0x100000>;
74 #address-cells = <1>; 46 #address-cells = <1>;
75 #size-cells = <1>; 47 #size-cells = <1>;
76 }; 48 };
77 49
78 wkup_pmx0: pinctrl@4301c000 { 50 wkup_pmx0: pinctrl@4301c000 {
79 compatible = "pinctrl-single"; 51 compatible = "pinctrl-single";
80 /* Proxy 0 addressing */ 52 /* Proxy 0 addressing */
81 reg = <0x00 0x4301c000 0x00 0x 53 reg = <0x00 0x4301c000 0x00 0x034>;
82 #pinctrl-cells = <1>; 54 #pinctrl-cells = <1>;
83 pinctrl-single,register-width 55 pinctrl-single,register-width = <32>;
84 pinctrl-single,function-mask = 56 pinctrl-single,function-mask = <0xffffffff>;
85 }; 57 };
86 58
87 wkup_pmx1: pinctrl@4301c038 { 59 wkup_pmx1: pinctrl@4301c038 {
88 compatible = "pinctrl-single"; 60 compatible = "pinctrl-single";
89 /* Proxy 0 addressing */ 61 /* Proxy 0 addressing */
90 reg = <0x00 0x4301c038 0x00 0x 62 reg = <0x00 0x4301c038 0x00 0x02c>;
91 #pinctrl-cells = <1>; 63 #pinctrl-cells = <1>;
92 pinctrl-single,register-width 64 pinctrl-single,register-width = <32>;
93 pinctrl-single,function-mask = 65 pinctrl-single,function-mask = <0xffffffff>;
94 }; 66 };
95 67
96 wkup_pmx2: pinctrl@4301c068 { 68 wkup_pmx2: pinctrl@4301c068 {
97 compatible = "pinctrl-single"; 69 compatible = "pinctrl-single";
98 /* Proxy 0 addressing */ 70 /* Proxy 0 addressing */
99 reg = <0x00 0x4301c068 0x00 0x 71 reg = <0x00 0x4301c068 0x00 0x120>;
100 #pinctrl-cells = <1>; 72 #pinctrl-cells = <1>;
101 pinctrl-single,register-width 73 pinctrl-single,register-width = <32>;
102 pinctrl-single,function-mask = 74 pinctrl-single,function-mask = <0xffffffff>;
103 }; 75 };
104 76
105 wkup_pmx3: pinctrl@4301c190 { 77 wkup_pmx3: pinctrl@4301c190 {
106 compatible = "pinctrl-single"; 78 compatible = "pinctrl-single";
107 /* Proxy 0 addressing */ 79 /* Proxy 0 addressing */
108 reg = <0x00 0x4301c190 0x00 0x 80 reg = <0x00 0x4301c190 0x00 0x004>;
109 #pinctrl-cells = <1>; 81 #pinctrl-cells = <1>;
110 pinctrl-single,register-width 82 pinctrl-single,register-width = <32>;
111 pinctrl-single,function-mask = 83 pinctrl-single,function-mask = <0xffffffff>;
112 }; 84 };
113 85
114 wkup_gpio_intr: interrupt-controller@4 86 wkup_gpio_intr: interrupt-controller@42200000 {
115 compatible = "ti,sci-intr"; 87 compatible = "ti,sci-intr";
116 reg = <0x00 0x42200000 0x00 0x 88 reg = <0x00 0x42200000 0x00 0x400>;
117 ti,intr-trigger-type = <1>; 89 ti,intr-trigger-type = <1>;
118 interrupt-controller; 90 interrupt-controller;
119 interrupt-parent = <&gic500>; 91 interrupt-parent = <&gic500>;
120 #interrupt-cells = <1>; 92 #interrupt-cells = <1>;
121 ti,sci = <&sms>; 93 ti,sci = <&sms>;
122 ti,sci-dev-id = <177>; 94 ti,sci-dev-id = <177>;
123 ti,interrupt-ranges = <16 960 !! 95 ti,interrupt-ranges = <16 928 16>;
124 }; <<
125 <<
126 /* MCU_TIMERIO pad input CTRLMMR_MCU_T <<
127 mcu_timerio_input: pinctrl@40f04200 { <<
128 compatible = "pinctrl-single"; <<
129 reg = <0x00 0x40f04200 0x00 0x <<
130 #pinctrl-cells = <1>; <<
131 pinctrl-single,register-width <<
132 pinctrl-single,function-mask = <<
133 /* Non-MPU Firmware usage */ <<
134 status = "reserved"; <<
135 }; 96 };
136 97
137 /* MCU_TIMERIO pad output CTRLMMR_MCU_ !! 98 mcu_conf: syscon@40f00000 {
138 mcu_timerio_output: pinctrl@40f04280 { !! 99 compatible = "ti,j721e-system-controller", "syscon", "simple-mfd";
139 compatible = "pinctrl-single"; !! 100 reg = <0x00 0x40f00000 0x00 0x20000>;
140 reg = <0x00 0x40f04280 0x00 0x <<
141 #pinctrl-cells = <1>; <<
142 pinctrl-single,register-width <<
143 pinctrl-single,function-mask = <<
144 /* Non-MPU Firmware usage */ <<
145 status = "reserved"; <<
146 }; <<
147 <<
148 mcu_conf: bus@40f00000 { <<
149 compatible = "simple-bus"; <<
150 #address-cells = <1>; 101 #address-cells = <1>;
151 #size-cells = <1>; 102 #size-cells = <1>;
152 ranges = <0x0 0x0 0x40f00000 0 !! 103 ranges = <0x00 0x00 0x40f00000 0x20000>;
153 <<
154 cpsw_mac_syscon: ethernet-mac- <<
155 compatible = "ti,am62p <<
156 reg = <0x200 0x8>; <<
157 }; <<
158 104
159 phy_gmii_sel: phy@4040 { 105 phy_gmii_sel: phy@4040 {
160 compatible = "ti,am654 106 compatible = "ti,am654-phy-gmii-sel";
161 reg = <0x4040 0x4>; 107 reg = <0x4040 0x4>;
162 #phy-cells = <1>; 108 #phy-cells = <1>;
163 }; 109 };
164 }; 110 };
165 111
166 mcu_timer0: timer@40400000 { <<
167 compatible = "ti,am654-timer"; <<
168 reg = <0x00 0x40400000 0x00 0x <<
169 interrupts = <GIC_SPI 816 IRQ_ <<
170 clocks = <&k3_clks 35 2>; <<
171 clock-names = "fck"; <<
172 assigned-clocks = <&k3_clks 35 <<
173 assigned-clock-parents = <&k3_ <<
174 power-domains = <&k3_pds 35 TI <<
175 ti,timer-pwm; <<
176 /* Non-MPU Firmware usage */ <<
177 status = "reserved"; <<
178 }; <<
179 <<
180 mcu_timer1: timer@40410000 { <<
181 bootph-all; <<
182 compatible = "ti,am654-timer"; <<
183 reg = <0x00 0x40410000 0x00 0x <<
184 interrupts = <GIC_SPI 817 IRQ_ <<
185 clocks = <&k3_clks 117 2>; <<
186 clock-names = "fck"; <<
187 assigned-clocks = <&k3_clks 11 <<
188 assigned-clock-parents = <&k3_ <<
189 power-domains = <&k3_pds 117 T <<
190 ti,timer-pwm; <<
191 /* Non-MPU Firmware usage */ <<
192 status = "reserved"; <<
193 }; <<
194 <<
195 mcu_timer2: timer@40420000 { <<
196 compatible = "ti,am654-timer"; <<
197 reg = <0x00 0x40420000 0x00 0x <<
198 interrupts = <GIC_SPI 818 IRQ_ <<
199 clocks = <&k3_clks 118 2>; <<
200 clock-names = "fck"; <<
201 assigned-clocks = <&k3_clks 11 <<
202 assigned-clock-parents = <&k3_ <<
203 power-domains = <&k3_pds 118 T <<
204 ti,timer-pwm; <<
205 /* Non-MPU Firmware usage */ <<
206 status = "reserved"; <<
207 }; <<
208 <<
209 mcu_timer3: timer@40430000 { <<
210 compatible = "ti,am654-timer"; <<
211 reg = <0x00 0x40430000 0x00 0x <<
212 interrupts = <GIC_SPI 819 IRQ_ <<
213 clocks = <&k3_clks 119 2>; <<
214 clock-names = "fck"; <<
215 assigned-clocks = <&k3_clks 11 <<
216 assigned-clock-parents = <&k3_ <<
217 power-domains = <&k3_pds 119 T <<
218 ti,timer-pwm; <<
219 /* Non-MPU Firmware usage */ <<
220 status = "reserved"; <<
221 }; <<
222 <<
223 mcu_timer4: timer@40440000 { <<
224 compatible = "ti,am654-timer"; <<
225 reg = <0x00 0x40440000 0x00 0x <<
226 interrupts = <GIC_SPI 820 IRQ_ <<
227 clocks = <&k3_clks 120 2>; <<
228 clock-names = "fck"; <<
229 assigned-clocks = <&k3_clks 12 <<
230 assigned-clock-parents = <&k3_ <<
231 power-domains = <&k3_pds 120 T <<
232 ti,timer-pwm; <<
233 /* Non-MPU Firmware usage */ <<
234 status = "reserved"; <<
235 }; <<
236 <<
237 mcu_timer5: timer@40450000 { <<
238 compatible = "ti,am654-timer"; <<
239 reg = <0x00 0x40450000 0x00 0x <<
240 interrupts = <GIC_SPI 821 IRQ_ <<
241 clocks = <&k3_clks 121 2>; <<
242 clock-names = "fck"; <<
243 assigned-clocks = <&k3_clks 12 <<
244 assigned-clock-parents = <&k3_ <<
245 power-domains = <&k3_pds 121 T <<
246 ti,timer-pwm; <<
247 /* Non-MPU Firmware usage */ <<
248 status = "reserved"; <<
249 }; <<
250 <<
251 mcu_timer6: timer@40460000 { <<
252 compatible = "ti,am654-timer"; <<
253 reg = <0x00 0x40460000 0x00 0x <<
254 interrupts = <GIC_SPI 822 IRQ_ <<
255 clocks = <&k3_clks 122 2>; <<
256 clock-names = "fck"; <<
257 assigned-clocks = <&k3_clks 12 <<
258 assigned-clock-parents = <&k3_ <<
259 power-domains = <&k3_pds 122 T <<
260 ti,timer-pwm; <<
261 /* Non-MPU Firmware usage */ <<
262 status = "reserved"; <<
263 }; <<
264 <<
265 mcu_timer7: timer@40470000 { <<
266 compatible = "ti,am654-timer"; <<
267 reg = <0x00 0x40470000 0x00 0x <<
268 interrupts = <GIC_SPI 823 IRQ_ <<
269 clocks = <&k3_clks 123 2>; <<
270 clock-names = "fck"; <<
271 assigned-clocks = <&k3_clks 12 <<
272 assigned-clock-parents = <&k3_ <<
273 power-domains = <&k3_pds 123 T <<
274 ti,timer-pwm; <<
275 /* Non-MPU Firmware usage */ <<
276 status = "reserved"; <<
277 }; <<
278 <<
279 mcu_timer8: timer@40480000 { <<
280 compatible = "ti,am654-timer"; <<
281 reg = <0x00 0x40480000 0x00 0x <<
282 interrupts = <GIC_SPI 824 IRQ_ <<
283 clocks = <&k3_clks 124 2>; <<
284 clock-names = "fck"; <<
285 assigned-clocks = <&k3_clks 12 <<
286 assigned-clock-parents = <&k3_ <<
287 power-domains = <&k3_pds 124 T <<
288 ti,timer-pwm; <<
289 /* Non-MPU Firmware usage */ <<
290 status = "reserved"; <<
291 }; <<
292 <<
293 mcu_timer9: timer@40490000 { <<
294 compatible = "ti,am654-timer"; <<
295 reg = <0x00 0x40490000 0x00 0x <<
296 interrupts = <GIC_SPI 825 IRQ_ <<
297 clocks = <&k3_clks 125 2>; <<
298 clock-names = "fck"; <<
299 assigned-clocks = <&k3_clks 12 <<
300 assigned-clock-parents = <&k3_ <<
301 power-domains = <&k3_pds 125 T <<
302 ti,timer-pwm; <<
303 /* Non-MPU Firmware usage */ <<
304 status = "reserved"; <<
305 }; <<
306 <<
307 wkup_uart0: serial@42300000 { 112 wkup_uart0: serial@42300000 {
308 compatible = "ti,j721e-uart", 113 compatible = "ti,j721e-uart", "ti,am654-uart";
309 reg = <0x00 0x42300000 0x00 0x 114 reg = <0x00 0x42300000 0x00 0x200>;
310 interrupts = <GIC_SPI 897 IRQ_ 115 interrupts = <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>;
>> 116 current-speed = <115200>;
311 clocks = <&k3_clks 397 0>; 117 clocks = <&k3_clks 397 0>;
312 clock-names = "fclk"; 118 clock-names = "fclk";
313 power-domains = <&k3_pds 397 T 119 power-domains = <&k3_pds 397 TI_SCI_PD_EXCLUSIVE>;
314 status = "disabled"; 120 status = "disabled";
315 }; 121 };
316 122
317 mcu_uart0: serial@40a00000 { 123 mcu_uart0: serial@40a00000 {
318 compatible = "ti,j721e-uart", 124 compatible = "ti,j721e-uart", "ti,am654-uart";
319 reg = <0x00 0x40a00000 0x00 0x 125 reg = <0x00 0x40a00000 0x00 0x200>;
320 interrupts = <GIC_SPI 846 IRQ_ 126 interrupts = <GIC_SPI 846 IRQ_TYPE_LEVEL_HIGH>;
>> 127 current-speed = <115200>;
321 clocks = <&k3_clks 149 0>; 128 clocks = <&k3_clks 149 0>;
322 clock-names = "fclk"; 129 clock-names = "fclk";
323 power-domains = <&k3_pds 149 T 130 power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>;
324 status = "disabled"; 131 status = "disabled";
325 }; 132 };
326 133
327 wkup_gpio0: gpio@42110000 { 134 wkup_gpio0: gpio@42110000 {
328 compatible = "ti,j721e-gpio", 135 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
329 reg = <0x00 0x42110000 0x00 0x 136 reg = <0x00 0x42110000 0x00 0x100>;
330 gpio-controller; 137 gpio-controller;
331 #gpio-cells = <2>; 138 #gpio-cells = <2>;
332 interrupt-parent = <&wkup_gpio 139 interrupt-parent = <&wkup_gpio_intr>;
333 interrupts = <103>, <104>, <10 140 interrupts = <103>, <104>, <105>, <106>, <107>, <108>;
334 interrupt-controller; 141 interrupt-controller;
335 #interrupt-cells = <2>; 142 #interrupt-cells = <2>;
336 ti,ngpio = <89>; 143 ti,ngpio = <89>;
337 ti,davinci-gpio-unbanked = <0> 144 ti,davinci-gpio-unbanked = <0>;
338 power-domains = <&k3_pds 167 T 145 power-domains = <&k3_pds 167 TI_SCI_PD_EXCLUSIVE>;
339 clocks = <&k3_clks 167 0>; 146 clocks = <&k3_clks 167 0>;
340 clock-names = "gpio"; 147 clock-names = "gpio";
341 status = "disabled"; 148 status = "disabled";
342 }; 149 };
343 150
344 wkup_gpio1: gpio@42100000 { 151 wkup_gpio1: gpio@42100000 {
345 compatible = "ti,j721e-gpio", 152 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
346 reg = <0x00 0x42100000 0x00 0x 153 reg = <0x00 0x42100000 0x00 0x100>;
347 gpio-controller; 154 gpio-controller;
348 #gpio-cells = <2>; 155 #gpio-cells = <2>;
349 interrupt-parent = <&wkup_gpio 156 interrupt-parent = <&wkup_gpio_intr>;
350 interrupts = <112>, <113>, <11 157 interrupts = <112>, <113>, <114>, <115>, <116>, <117>;
351 interrupt-controller; 158 interrupt-controller;
352 #interrupt-cells = <2>; 159 #interrupt-cells = <2>;
353 ti,ngpio = <89>; 160 ti,ngpio = <89>;
354 ti,davinci-gpio-unbanked = <0> 161 ti,davinci-gpio-unbanked = <0>;
355 power-domains = <&k3_pds 168 T 162 power-domains = <&k3_pds 168 TI_SCI_PD_EXCLUSIVE>;
356 clocks = <&k3_clks 168 0>; 163 clocks = <&k3_clks 168 0>;
357 clock-names = "gpio"; 164 clock-names = "gpio";
358 status = "disabled"; 165 status = "disabled";
359 }; 166 };
360 167
361 wkup_i2c0: i2c@42120000 { 168 wkup_i2c0: i2c@42120000 {
362 compatible = "ti,j721e-i2c", " 169 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
363 reg = <0x00 0x42120000 0x00 0x 170 reg = <0x00 0x42120000 0x00 0x100>;
364 interrupts = <GIC_SPI 896 IRQ_ 171 interrupts = <GIC_SPI 896 IRQ_TYPE_LEVEL_HIGH>;
365 #address-cells = <1>; 172 #address-cells = <1>;
366 #size-cells = <0>; 173 #size-cells = <0>;
367 clocks = <&k3_clks 279 2>; 174 clocks = <&k3_clks 279 2>;
368 clock-names = "fck"; 175 clock-names = "fck";
369 power-domains = <&k3_pds 279 T 176 power-domains = <&k3_pds 279 TI_SCI_PD_EXCLUSIVE>;
370 status = "disabled"; 177 status = "disabled";
371 }; 178 };
372 179
373 mcu_i2c0: i2c@40b00000 { 180 mcu_i2c0: i2c@40b00000 {
374 compatible = "ti,j721e-i2c", " 181 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
375 reg = <0x00 0x40b00000 0x00 0x 182 reg = <0x00 0x40b00000 0x00 0x100>;
376 interrupts = <GIC_SPI 852 IRQ_ 183 interrupts = <GIC_SPI 852 IRQ_TYPE_LEVEL_HIGH>;
377 #address-cells = <1>; 184 #address-cells = <1>;
378 #size-cells = <0>; 185 #size-cells = <0>;
379 clocks = <&k3_clks 277 2>; 186 clocks = <&k3_clks 277 2>;
380 clock-names = "fck"; 187 clock-names = "fck";
381 power-domains = <&k3_pds 277 T 188 power-domains = <&k3_pds 277 TI_SCI_PD_EXCLUSIVE>;
382 status = "disabled"; 189 status = "disabled";
383 }; 190 };
384 191
385 mcu_i2c1: i2c@40b10000 { 192 mcu_i2c1: i2c@40b10000 {
386 compatible = "ti,j721e-i2c", " 193 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
387 reg = <0x00 0x40b10000 0x00 0x 194 reg = <0x00 0x40b10000 0x00 0x100>;
388 interrupts = <GIC_SPI 853 IRQ_ 195 interrupts = <GIC_SPI 853 IRQ_TYPE_LEVEL_HIGH>;
389 #address-cells = <1>; 196 #address-cells = <1>;
390 #size-cells = <0>; 197 #size-cells = <0>;
391 clocks = <&k3_clks 278 2>; 198 clocks = <&k3_clks 278 2>;
392 clock-names = "fck"; 199 clock-names = "fck";
393 power-domains = <&k3_pds 278 T 200 power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>;
394 status = "disabled"; 201 status = "disabled";
395 }; 202 };
396 203
397 mcu_mcan0: can@40528000 { 204 mcu_mcan0: can@40528000 {
398 compatible = "bosch,m_can"; 205 compatible = "bosch,m_can";
399 reg = <0x00 0x40528000 0x00 0x 206 reg = <0x00 0x40528000 0x00 0x200>,
400 <0x00 0x40500000 0x00 0x 207 <0x00 0x40500000 0x00 0x8000>;
401 reg-names = "m_can", "message_ 208 reg-names = "m_can", "message_ram";
402 power-domains = <&k3_pds 263 T 209 power-domains = <&k3_pds 263 TI_SCI_PD_EXCLUSIVE>;
403 clocks = <&k3_clks 263 6>, <&k 210 clocks = <&k3_clks 263 6>, <&k3_clks 263 1>;
404 clock-names = "hclk", "cclk"; 211 clock-names = "hclk", "cclk";
405 interrupts = <GIC_SPI 832 IRQ_ 212 interrupts = <GIC_SPI 832 IRQ_TYPE_LEVEL_HIGH>,
406 <GIC_SPI 833 IRQ_ 213 <GIC_SPI 833 IRQ_TYPE_LEVEL_HIGH>;
407 interrupt-names = "int0", "int 214 interrupt-names = "int0", "int1";
408 bosch,mram-cfg = <0x00 128 64 215 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>;
409 status = "disabled"; 216 status = "disabled";
410 }; 217 };
411 218
412 mcu_mcan1: can@40568000 { 219 mcu_mcan1: can@40568000 {
413 compatible = "bosch,m_can"; 220 compatible = "bosch,m_can";
414 reg = <0x00 0x40568000 0x00 0x 221 reg = <0x00 0x40568000 0x00 0x200>,
415 <0x00 0x40540000 0x00 0x 222 <0x00 0x40540000 0x00 0x8000>;
416 reg-names = "m_can", "message_ 223 reg-names = "m_can", "message_ram";
417 power-domains = <&k3_pds 264 T 224 power-domains = <&k3_pds 264 TI_SCI_PD_EXCLUSIVE>;
418 clocks = <&k3_clks 264 6>, <&k 225 clocks = <&k3_clks 264 6>, <&k3_clks 264 1>;
419 clock-names = "hclk", "cclk"; 226 clock-names = "hclk", "cclk";
420 interrupts = <GIC_SPI 835 IRQ_ 227 interrupts = <GIC_SPI 835 IRQ_TYPE_LEVEL_HIGH>,
421 <GIC_SPI 836 IRQ_ 228 <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>;
422 interrupt-names = "int0", "int 229 interrupt-names = "int0", "int1";
423 bosch,mram-cfg = <0x00 128 64 230 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>;
424 status = "disabled"; 231 status = "disabled";
425 }; 232 };
426 233
427 mcu_spi0: spi@40300000 { !! 234 mcu_navss: bus@28380000{
428 compatible = "ti,am654-mcspi", <<
429 reg = <0x00 0x040300000 0x00 0 <<
430 interrupts = <GIC_SPI 848 IRQ_ <<
431 #address-cells = <1>; <<
432 #size-cells = <0>; <<
433 power-domains = <&k3_pds 384 T <<
434 clocks = <&k3_clks 384 0>; <<
435 status = "disabled"; <<
436 }; <<
437 <<
438 mcu_spi1: spi@40310000 { <<
439 compatible = "ti,am654-mcspi", <<
440 reg = <0x00 0x040310000 0x00 0 <<
441 interrupts = <GIC_SPI 849 IRQ_ <<
442 #address-cells = <1>; <<
443 #size-cells = <0>; <<
444 power-domains = <&k3_pds 385 T <<
445 clocks = <&k3_clks 385 0>; <<
446 status = "disabled"; <<
447 }; <<
448 <<
449 mcu_spi2: spi@40320000 { <<
450 compatible = "ti,am654-mcspi", <<
451 reg = <0x00 0x040320000 0x00 0 <<
452 interrupts = <GIC_SPI 850 IRQ_ <<
453 #address-cells = <1>; <<
454 #size-cells = <0>; <<
455 power-domains = <&k3_pds 386 T <<
456 clocks = <&k3_clks 386 0>; <<
457 status = "disabled"; <<
458 }; <<
459 <<
460 mcu_navss: bus@28380000 { <<
461 bootph-all; <<
462 compatible = "simple-bus"; 235 compatible = "simple-bus";
463 #address-cells = <2>; 236 #address-cells = <2>;
464 #size-cells = <2>; 237 #size-cells = <2>;
465 ranges = <0x00 0x28380000 0x00 238 ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>;
466 ti,sci-dev-id = <323>; 239 ti,sci-dev-id = <323>;
467 dma-coherent; 240 dma-coherent;
468 dma-ranges; 241 dma-ranges;
469 242
470 mcu_ringacc: ringacc@2b800000 243 mcu_ringacc: ringacc@2b800000 {
471 bootph-all; <<
472 compatible = "ti,am654 244 compatible = "ti,am654-navss-ringacc";
473 reg = <0x00 0x2b800000 245 reg = <0x00 0x2b800000 0x00 0x400000>,
474 <0x00 0x2b000000 246 <0x00 0x2b000000 0x00 0x400000>,
475 <0x00 0x28590000 247 <0x00 0x28590000 0x00 0x100>,
476 <0x00 0x2a500000 !! 248 <0x00 0x2a500000 0x00 0x40000>;
477 <0x00 0x28440000 !! 249 reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target";
478 reg-names = "rt", "fif <<
479 ti,num-rings = <286>; 250 ti,num-rings = <286>;
480 ti,sci-rm-range-gp-rin 251 ti,sci-rm-range-gp-rings = <0x1>;
481 ti,sci = <&sms>; 252 ti,sci = <&sms>;
482 ti,sci-dev-id = <328>; 253 ti,sci-dev-id = <328>;
483 msi-parent = <&main_ud 254 msi-parent = <&main_udmass_inta>;
484 }; 255 };
485 256
486 mcu_udmap: dma-controller@285c 257 mcu_udmap: dma-controller@285c0000 {
487 bootph-all; <<
488 compatible = "ti,j721e 258 compatible = "ti,j721e-navss-mcu-udmap";
489 reg = <0x00 0x285c0000 259 reg = <0x00 0x285c0000 0x00 0x100>,
490 <0x00 0x2a800000 260 <0x00 0x2a800000 0x00 0x40000>,
491 <0x00 0x2aa00000 !! 261 <0x00 0x2aa00000 0x00 0x40000>;
492 <0x00 0x284a0000 !! 262 reg-names = "gcfg", "rchanrt", "tchanrt";
493 <0x00 0x284c0000 <<
494 <0x00 0x28400000 <<
495 reg-names = "gcfg", "r <<
496 "tchan", " <<
497 msi-parent = <&main_ud 263 msi-parent = <&main_udmass_inta>;
498 #dma-cells = <1>; 264 #dma-cells = <1>;
499 265
500 ti,sci = <&sms>; 266 ti,sci = <&sms>;
501 ti,sci-dev-id = <329>; 267 ti,sci-dev-id = <329>;
502 ti,ringacc = <&mcu_rin 268 ti,ringacc = <&mcu_ringacc>;
503 ti,sci-rm-range-tchan 269 ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */
504 270 <0x0f>; /* TX_HCHAN */
505 ti,sci-rm-range-rchan 271 ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */
506 272 <0x0b>; /* RX_HCHAN */
507 ti,sci-rm-range-rflow 273 ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */
508 }; 274 };
509 }; 275 };
510 276
511 secure_proxy_mcu: mailbox@2a480000 { <<
512 compatible = "ti,am654-secure- <<
513 #mbox-cells = <1>; <<
514 reg-names = "target_data", "rt <<
515 reg = <0x00 0x2a480000 0x00 0x <<
516 <0x00 0x2a380000 0x00 0x <<
517 <0x00 0x2a400000 0x00 0x <<
518 /* <<
519 * Marked Disabled: <<
520 * Node is incomplete as it is <<
521 * firmware on non-MPU process <<
522 */ <<
523 status = "disabled"; <<
524 }; <<
525 <<
526 mcu_cpsw: ethernet@46000000 { 277 mcu_cpsw: ethernet@46000000 {
527 compatible = "ti,j721e-cpsw-nu 278 compatible = "ti,j721e-cpsw-nuss";
528 #address-cells = <2>; 279 #address-cells = <2>;
529 #size-cells = <2>; 280 #size-cells = <2>;
530 reg = <0x00 0x46000000 0x00 0x 281 reg = <0x00 0x46000000 0x00 0x200000>;
531 reg-names = "cpsw_nuss"; 282 reg-names = "cpsw_nuss";
532 ranges = <0x00 0x00 0x00 0x460 283 ranges = <0x00 0x00 0x00 0x46000000 0x00 0x200000>;
533 dma-coherent; 284 dma-coherent;
534 clocks = <&k3_clks 63 0>; 285 clocks = <&k3_clks 63 0>;
535 clock-names = "fck"; 286 clock-names = "fck";
536 power-domains = <&k3_pds 63 TI 287 power-domains = <&k3_pds 63 TI_SCI_PD_EXCLUSIVE>;
537 288
538 dmas = <&mcu_udmap 0xf000>, 289 dmas = <&mcu_udmap 0xf000>,
539 <&mcu_udmap 0xf001>, 290 <&mcu_udmap 0xf001>,
540 <&mcu_udmap 0xf002>, 291 <&mcu_udmap 0xf002>,
541 <&mcu_udmap 0xf003>, 292 <&mcu_udmap 0xf003>,
542 <&mcu_udmap 0xf004>, 293 <&mcu_udmap 0xf004>,
543 <&mcu_udmap 0xf005>, 294 <&mcu_udmap 0xf005>,
544 <&mcu_udmap 0xf006>, 295 <&mcu_udmap 0xf006>,
545 <&mcu_udmap 0xf007>, 296 <&mcu_udmap 0xf007>,
546 <&mcu_udmap 0x7000>; 297 <&mcu_udmap 0x7000>;
547 dma-names = "tx0", "tx1", "tx2 298 dma-names = "tx0", "tx1", "tx2", "tx3",
548 "tx4", "tx5", "tx6 299 "tx4", "tx5", "tx6", "tx7",
549 "rx"; 300 "rx";
550 status = "disabled"; 301 status = "disabled";
551 302
552 ethernet-ports { 303 ethernet-ports {
553 #address-cells = <1>; 304 #address-cells = <1>;
554 #size-cells = <0>; 305 #size-cells = <0>;
555 306
556 mcu_cpsw_port1: port@1 307 mcu_cpsw_port1: port@1 {
557 reg = <1>; 308 reg = <1>;
558 ti,mac-only; 309 ti,mac-only;
559 label = "port1 310 label = "port1";
560 ti,syscon-efus !! 311 ti,syscon-efuse = <&mcu_conf 0x200>;
561 phys = <&phy_g 312 phys = <&phy_gmii_sel 1>;
562 }; 313 };
563 }; 314 };
564 315
565 davinci_mdio: mdio@f00 { 316 davinci_mdio: mdio@f00 {
566 compatible = "ti,cpsw- 317 compatible = "ti,cpsw-mdio","ti,davinci_mdio";
567 reg = <0x00 0xf00 0x00 318 reg = <0x00 0xf00 0x00 0x100>;
568 #address-cells = <1>; 319 #address-cells = <1>;
569 #size-cells = <0>; 320 #size-cells = <0>;
570 clocks = <&k3_clks 63 321 clocks = <&k3_clks 63 0>;
571 clock-names = "fck"; 322 clock-names = "fck";
572 bus_freq = <1000000>; 323 bus_freq = <1000000>;
573 }; 324 };
574 325
575 cpts@3d000 { 326 cpts@3d000 {
576 compatible = "ti,am65- 327 compatible = "ti,am65-cpts";
577 reg = <0x00 0x3d000 0x 328 reg = <0x00 0x3d000 0x00 0x400>;
578 clocks = <&k3_clks 63 329 clocks = <&k3_clks 63 3>;
579 clock-names = "cpts"; 330 clock-names = "cpts";
580 assigned-clocks = <&k3 331 assigned-clocks = <&k3_clks 63 3>; /* CPTS_RFT_CLK */
581 assigned-clock-parents 332 assigned-clock-parents = <&k3_clks 63 5>; /* MAIN_0_HSDIV6_CLK */
582 interrupts-extended = 333 interrupts-extended = <&gic500 GIC_SPI 858 IRQ_TYPE_LEVEL_HIGH>;
583 interrupt-names = "cpt 334 interrupt-names = "cpts";
584 ti,cpts-ext-ts-inputs 335 ti,cpts-ext-ts-inputs = <4>;
585 ti,cpts-periodic-outpu 336 ti,cpts-periodic-outputs = <2>;
586 }; 337 };
587 }; <<
588 <<
589 mcu_r5fss0: r5fss@41000000 { <<
590 compatible = "ti,j721s2-r5fss" <<
591 ti,cluster-mode = <1>; <<
592 #address-cells = <1>; <<
593 #size-cells = <1>; <<
594 ranges = <0x41000000 0x00 0x41 <<
595 <0x41400000 0x00 0x41 <<
596 power-domains = <&k3_pds 345 T <<
597 <<
598 mcu_r5fss0_core0: r5f@41000000 <<
599 compatible = "ti,j721s <<
600 reg = <0x41000000 0x00 <<
601 <0x41010000 0x00 <<
602 reg-names = "atcm", "b <<
603 ti,sci = <&sms>; <<
604 ti,sci-dev-id = <346>; <<
605 ti,sci-proc-ids = <0x0 <<
606 resets = <&k3_reset 34 <<
607 firmware-name = "j784s <<
608 ti,atcm-enable = <1>; <<
609 ti,btcm-enable = <1>; <<
610 ti,loczrama = <1>; <<
611 }; <<
612 <<
613 mcu_r5fss0_core1: r5f@41400000 <<
614 compatible = "ti,j721s <<
615 reg = <0x41400000 0x00 <<
616 <0x41410000 0x00 <<
617 reg-names = "atcm", "b <<
618 ti,sci = <&sms>; <<
619 ti,sci-dev-id = <347>; <<
620 ti,sci-proc-ids = <0x0 <<
621 resets = <&k3_reset 34 <<
622 firmware-name = "j784s <<
623 ti,atcm-enable = <1>; <<
624 ti,btcm-enable = <1>; <<
625 ti,loczrama = <1>; <<
626 }; <<
627 }; <<
628 <<
629 wkup_vtm0: temperature-sensor@42040000 <<
630 compatible = "ti,j7200-vtm"; <<
631 reg = <0x00 0x42040000 0x00 0x <<
632 <0x00 0x42050000 0x00 0x <<
633 power-domains = <&k3_pds 243 T <<
634 #thermal-sensor-cells = <1>; <<
635 }; <<
636 <<
637 tscadc0: tscadc@40200000 { <<
638 compatible = "ti,am3359-tscadc <<
639 reg = <0x00 0x40200000 0x00 0x <<
640 interrupts = <GIC_SPI 860 IRQ_ <<
641 power-domains = <&k3_pds 0 TI_ <<
642 clocks = <&k3_clks 0 0>; <<
643 assigned-clocks = <&k3_clks 0 <<
644 assigned-clock-rates = <600000 <<
645 clock-names = "fck"; <<
646 dmas = <&main_udmap 0x7400>, <<
647 <&main_udmap 0x7401>; <<
648 dma-names = "fifo0", "fifo1"; <<
649 status = "disabled"; <<
650 <<
651 adc { <<
652 #io-channel-cells = <1 <<
653 compatible = "ti,am335 <<
654 }; <<
655 }; <<
656 <<
657 tscadc1: tscadc@40210000 { <<
658 compatible = "ti,am3359-tscadc <<
659 reg = <0x00 0x40210000 0x00 0x <<
660 interrupts = <GIC_SPI 861 IRQ_ <<
661 power-domains = <&k3_pds 1 TI_ <<
662 clocks = <&k3_clks 1 0>; <<
663 assigned-clocks = <&k3_clks 1 <<
664 assigned-clock-rates = <600000 <<
665 clock-names = "fck"; <<
666 dmas = <&main_udmap 0x7402>, <<
667 <&main_udmap 0x7403>; <<
668 dma-names = "fifo0", "fifo1"; <<
669 status = "disabled"; <<
670 <<
671 adc { <<
672 #io-channel-cells = <1 <<
673 compatible = "ti,am335 <<
674 }; <<
675 }; <<
676 <<
677 fss: bus@47000000 { <<
678 compatible = "simple-bus"; <<
679 #address-cells = <2>; <<
680 #size-cells = <2>; <<
681 ranges = <0x00 0x47000000 0x00 <<
682 <0x00 0x47040000 0x00 <<
683 <0x00 0x47050000 0x00 <<
684 <0x00 0x50000000 0x00 <<
685 <0x04 0x00000000 0x04 <<
686 <<
687 ospi0: spi@47040000 { <<
688 compatible = "ti,am654 <<
689 reg = <0x00 0x47040000 <<
690 <0x05 0x00000000 <<
691 interrupts = <GIC_SPI <<
692 cdns,fifo-depth = <256 <<
693 cdns,fifo-width = <4>; <<
694 cdns,trigger-address = <<
695 clocks = <&k3_clks 161 <<
696 assigned-clocks = <&k3 <<
697 assigned-clock-parents <<
698 assigned-clock-rates = <<
699 power-domains = <&k3_p <<
700 #address-cells = <1>; <<
701 #size-cells = <0>; <<
702 status = "disabled"; <<
703 }; <<
704 <<
705 ospi1: spi@47050000 { <<
706 compatible = "ti,am654 <<
707 reg = <0x00 0x47050000 <<
708 <0x07 0x00000000 <<
709 interrupts = <GIC_SPI <<
710 cdns,fifo-depth = <256 <<
711 cdns,fifo-width = <4>; <<
712 cdns,trigger-address = <<
713 clocks = <&k3_clks 162 <<
714 power-domains = <&k3_p <<
715 #address-cells = <1>; <<
716 #size-cells = <0>; <<
717 status = "disabled"; <<
718 }; <<
719 }; <<
720 <<
721 mcu_esm: esm@40800000 { <<
722 compatible = "ti,j721e-esm"; <<
723 reg = <0x00 0x40800000 0x00 0x <<
724 ti,esm-pins = <95>; <<
725 bootph-pre-ram; <<
726 }; <<
727 <<
728 wkup_esm: esm@42080000 { <<
729 compatible = "ti,j721e-esm"; <<
730 reg = <0x00 0x42080000 0x00 0x <<
731 ti,esm-pins = <63>; <<
732 bootph-pre-ram; <<
733 }; <<
734 <<
735 /* <<
736 * The 2 RTI instances are couple with <<
737 * reserved as these will be used by t <<
738 */ <<
739 mcu_watchdog0: watchdog@40600000 { <<
740 compatible = "ti,j7-rti-wdt"; <<
741 reg = <0x00 0x40600000 0x00 0x <<
742 clocks = <&k3_clks 367 1>; <<
743 power-domains = <&k3_pds 367 T <<
744 assigned-clocks = <&k3_clks 36 <<
745 assigned-clock-parents = <&k3_ <<
746 /* reserved for MCU_R5F0_0 */ <<
747 status = "reserved"; <<
748 }; <<
749 <<
750 mcu_watchdog1: watchdog@40610000 { <<
751 compatible = "ti,j7-rti-wdt"; <<
752 reg = <0x00 0x40610000 0x00 0x <<
753 clocks = <&k3_clks 368 1>; <<
754 power-domains = <&k3_pds 368 T <<
755 assigned-clocks = <&k3_clks 36 <<
756 assigned-clock-parents = <&k3_ <<
757 /* reserved for MCU_R5F0_1 */ <<
758 status = "reserved"; <<
759 }; 338 };
760 }; 339 };
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