1 // SPDX-License-Identifier: GPL-2.0-only OR MI !! 1 // SPDX-License-Identifier: GPL-2.0
2 /* 2 /*
3 * Device Tree Source for J784S4 SoC Family MC 3 * Device Tree Source for J784S4 SoC Family MCU/WAKEUP Domain peripherals
4 * 4 *
5 * Copyright (C) 2022-2024 Texas Instruments I !! 5 * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
6 */ 6 */
7 7
8 &cbass_mcu_wakeup { 8 &cbass_mcu_wakeup {
9 sms: system-controller@44083000 { 9 sms: system-controller@44083000 {
10 bootph-all; <<
11 compatible = "ti,k2g-sci"; 10 compatible = "ti,k2g-sci";
12 ti,host-id = <12>; 11 ti,host-id = <12>;
13 12
14 mbox-names = "rx", "tx"; 13 mbox-names = "rx", "tx";
15 14
16 mboxes = <&secure_proxy_main 1 15 mboxes = <&secure_proxy_main 11>,
17 <&secure_proxy_main 1 16 <&secure_proxy_main 13>;
18 17
19 reg-names = "debug_messages"; 18 reg-names = "debug_messages";
20 reg = <0x00 0x44083000 0x00 0x 19 reg = <0x00 0x44083000 0x00 0x1000>;
21 20
22 k3_pds: power-controller { 21 k3_pds: power-controller {
23 bootph-all; <<
24 compatible = "ti,sci-p 22 compatible = "ti,sci-pm-domain";
25 #power-domain-cells = 23 #power-domain-cells = <2>;
26 }; 24 };
27 25
28 k3_clks: clock-controller { 26 k3_clks: clock-controller {
29 bootph-all; <<
30 compatible = "ti,k2g-s 27 compatible = "ti,k2g-sci-clk";
31 #clock-cells = <2>; 28 #clock-cells = <2>;
32 }; 29 };
33 30
34 k3_reset: reset-controller { 31 k3_reset: reset-controller {
35 bootph-all; <<
36 compatible = "ti,sci-r 32 compatible = "ti,sci-reset";
37 #reset-cells = <2>; 33 #reset-cells = <2>;
38 }; 34 };
39 }; 35 };
40 36
41 wkup_conf: bus@43000000 { !! 37 chipid@43000014 {
42 bootph-all; !! 38 compatible = "ti,am654-chipid";
43 compatible = "simple-bus"; !! 39 reg = <0x00 0x43000014 0x00 0x4>;
44 #address-cells = <1>; <<
45 #size-cells = <1>; <<
46 ranges = <0x0 0x00 0x43000000 <<
47 <<
48 chipid: chipid@14 { <<
49 bootph-all; <<
50 compatible = "ti,am654 <<
51 reg = <0x14 0x4>; <<
52 }; <<
53 }; 40 };
54 41
55 secure_proxy_sa3: mailbox@43600000 { 42 secure_proxy_sa3: mailbox@43600000 {
56 compatible = "ti,am654-secure- 43 compatible = "ti,am654-secure-proxy";
57 #mbox-cells = <1>; 44 #mbox-cells = <1>;
58 reg-names = "target_data", "rt 45 reg-names = "target_data", "rt", "scfg";
59 reg = <0x00 0x43600000 0x00 0x 46 reg = <0x00 0x43600000 0x00 0x10000>,
60 <0x00 0x44880000 0x00 0x 47 <0x00 0x44880000 0x00 0x20000>,
61 <0x00 0x44860000 0x00 0x 48 <0x00 0x44860000 0x00 0x20000>;
62 /* 49 /*
63 * Marked Disabled: 50 * Marked Disabled:
64 * Node is incomplete as it is 51 * Node is incomplete as it is meant for bootloaders and
65 * firmware on non-MPU process 52 * firmware on non-MPU processors
66 */ 53 */
67 status = "disabled"; 54 status = "disabled";
68 }; 55 };
69 56
70 mcu_ram: sram@41c00000 { 57 mcu_ram: sram@41c00000 {
71 compatible = "mmio-sram"; 58 compatible = "mmio-sram";
72 reg = <0x00 0x41c00000 0x00 0x 59 reg = <0x00 0x41c00000 0x00 0x100000>;
73 ranges = <0x00 0x00 0x41c00000 60 ranges = <0x00 0x00 0x41c00000 0x100000>;
74 #address-cells = <1>; 61 #address-cells = <1>;
75 #size-cells = <1>; 62 #size-cells = <1>;
76 }; 63 };
77 64
78 wkup_pmx0: pinctrl@4301c000 { 65 wkup_pmx0: pinctrl@4301c000 {
79 compatible = "pinctrl-single"; 66 compatible = "pinctrl-single";
80 /* Proxy 0 addressing */ 67 /* Proxy 0 addressing */
81 reg = <0x00 0x4301c000 0x00 0x 68 reg = <0x00 0x4301c000 0x00 0x034>;
82 #pinctrl-cells = <1>; 69 #pinctrl-cells = <1>;
83 pinctrl-single,register-width 70 pinctrl-single,register-width = <32>;
84 pinctrl-single,function-mask = 71 pinctrl-single,function-mask = <0xffffffff>;
85 }; 72 };
86 73
87 wkup_pmx1: pinctrl@4301c038 { 74 wkup_pmx1: pinctrl@4301c038 {
88 compatible = "pinctrl-single"; 75 compatible = "pinctrl-single";
89 /* Proxy 0 addressing */ 76 /* Proxy 0 addressing */
90 reg = <0x00 0x4301c038 0x00 0x 77 reg = <0x00 0x4301c038 0x00 0x02c>;
91 #pinctrl-cells = <1>; 78 #pinctrl-cells = <1>;
92 pinctrl-single,register-width 79 pinctrl-single,register-width = <32>;
93 pinctrl-single,function-mask = 80 pinctrl-single,function-mask = <0xffffffff>;
94 }; 81 };
95 82
96 wkup_pmx2: pinctrl@4301c068 { 83 wkup_pmx2: pinctrl@4301c068 {
97 compatible = "pinctrl-single"; 84 compatible = "pinctrl-single";
98 /* Proxy 0 addressing */ 85 /* Proxy 0 addressing */
99 reg = <0x00 0x4301c068 0x00 0x 86 reg = <0x00 0x4301c068 0x00 0x120>;
100 #pinctrl-cells = <1>; 87 #pinctrl-cells = <1>;
101 pinctrl-single,register-width 88 pinctrl-single,register-width = <32>;
102 pinctrl-single,function-mask = 89 pinctrl-single,function-mask = <0xffffffff>;
103 }; 90 };
104 91
105 wkup_pmx3: pinctrl@4301c190 { 92 wkup_pmx3: pinctrl@4301c190 {
106 compatible = "pinctrl-single"; 93 compatible = "pinctrl-single";
107 /* Proxy 0 addressing */ 94 /* Proxy 0 addressing */
108 reg = <0x00 0x4301c190 0x00 0x 95 reg = <0x00 0x4301c190 0x00 0x004>;
109 #pinctrl-cells = <1>; 96 #pinctrl-cells = <1>;
110 pinctrl-single,register-width 97 pinctrl-single,register-width = <32>;
111 pinctrl-single,function-mask = 98 pinctrl-single,function-mask = <0xffffffff>;
112 }; 99 };
113 100
114 wkup_gpio_intr: interrupt-controller@4 101 wkup_gpio_intr: interrupt-controller@42200000 {
115 compatible = "ti,sci-intr"; 102 compatible = "ti,sci-intr";
116 reg = <0x00 0x42200000 0x00 0x 103 reg = <0x00 0x42200000 0x00 0x400>;
117 ti,intr-trigger-type = <1>; 104 ti,intr-trigger-type = <1>;
118 interrupt-controller; 105 interrupt-controller;
119 interrupt-parent = <&gic500>; 106 interrupt-parent = <&gic500>;
120 #interrupt-cells = <1>; 107 #interrupt-cells = <1>;
121 ti,sci = <&sms>; 108 ti,sci = <&sms>;
122 ti,sci-dev-id = <177>; 109 ti,sci-dev-id = <177>;
123 ti,interrupt-ranges = <16 960 110 ti,interrupt-ranges = <16 960 16>;
124 }; 111 };
125 112
126 /* MCU_TIMERIO pad input CTRLMMR_MCU_T 113 /* MCU_TIMERIO pad input CTRLMMR_MCU_TIMER*_CTRL registers */
127 mcu_timerio_input: pinctrl@40f04200 { 114 mcu_timerio_input: pinctrl@40f04200 {
128 compatible = "pinctrl-single"; 115 compatible = "pinctrl-single";
129 reg = <0x00 0x40f04200 0x00 0x 116 reg = <0x00 0x40f04200 0x00 0x28>;
130 #pinctrl-cells = <1>; 117 #pinctrl-cells = <1>;
131 pinctrl-single,register-width 118 pinctrl-single,register-width = <32>;
132 pinctrl-single,function-mask = 119 pinctrl-single,function-mask = <0x0000000f>;
133 /* Non-MPU Firmware usage */ 120 /* Non-MPU Firmware usage */
134 status = "reserved"; 121 status = "reserved";
135 }; 122 };
136 123
137 /* MCU_TIMERIO pad output CTRLMMR_MCU_ 124 /* MCU_TIMERIO pad output CTRLMMR_MCU_TIMERIO*_CTRL registers */
138 mcu_timerio_output: pinctrl@40f04280 { 125 mcu_timerio_output: pinctrl@40f04280 {
139 compatible = "pinctrl-single"; 126 compatible = "pinctrl-single";
140 reg = <0x00 0x40f04280 0x00 0x 127 reg = <0x00 0x40f04280 0x00 0x28>;
141 #pinctrl-cells = <1>; 128 #pinctrl-cells = <1>;
142 pinctrl-single,register-width 129 pinctrl-single,register-width = <32>;
143 pinctrl-single,function-mask = 130 pinctrl-single,function-mask = <0x0000000f>;
144 /* Non-MPU Firmware usage */ 131 /* Non-MPU Firmware usage */
145 status = "reserved"; 132 status = "reserved";
146 }; 133 };
147 134
148 mcu_conf: bus@40f00000 { !! 135 mcu_conf: syscon@40f00000 {
149 compatible = "simple-bus"; !! 136 compatible = "ti,j721e-system-controller", "syscon", "simple-mfd";
>> 137 reg = <0x00 0x40f00000 0x00 0x20000>;
150 #address-cells = <1>; 138 #address-cells = <1>;
151 #size-cells = <1>; 139 #size-cells = <1>;
152 ranges = <0x0 0x0 0x40f00000 0 !! 140 ranges = <0x00 0x00 0x40f00000 0x20000>;
153 <<
154 cpsw_mac_syscon: ethernet-mac- <<
155 compatible = "ti,am62p <<
156 reg = <0x200 0x8>; <<
157 }; <<
158 141
159 phy_gmii_sel: phy@4040 { 142 phy_gmii_sel: phy@4040 {
160 compatible = "ti,am654 143 compatible = "ti,am654-phy-gmii-sel";
161 reg = <0x4040 0x4>; 144 reg = <0x4040 0x4>;
162 #phy-cells = <1>; 145 #phy-cells = <1>;
163 }; 146 };
164 }; 147 };
165 148
166 mcu_timer0: timer@40400000 { 149 mcu_timer0: timer@40400000 {
167 compatible = "ti,am654-timer"; 150 compatible = "ti,am654-timer";
168 reg = <0x00 0x40400000 0x00 0x 151 reg = <0x00 0x40400000 0x00 0x400>;
169 interrupts = <GIC_SPI 816 IRQ_ 152 interrupts = <GIC_SPI 816 IRQ_TYPE_LEVEL_HIGH>;
170 clocks = <&k3_clks 35 2>; 153 clocks = <&k3_clks 35 2>;
171 clock-names = "fck"; 154 clock-names = "fck";
172 assigned-clocks = <&k3_clks 35 155 assigned-clocks = <&k3_clks 35 2>;
173 assigned-clock-parents = <&k3_ 156 assigned-clock-parents = <&k3_clks 35 3>;
174 power-domains = <&k3_pds 35 TI 157 power-domains = <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>;
175 ti,timer-pwm; 158 ti,timer-pwm;
176 /* Non-MPU Firmware usage */ 159 /* Non-MPU Firmware usage */
177 status = "reserved"; 160 status = "reserved";
178 }; 161 };
179 162
180 mcu_timer1: timer@40410000 { 163 mcu_timer1: timer@40410000 {
181 bootph-all; <<
182 compatible = "ti,am654-timer"; 164 compatible = "ti,am654-timer";
183 reg = <0x00 0x40410000 0x00 0x 165 reg = <0x00 0x40410000 0x00 0x400>;
184 interrupts = <GIC_SPI 817 IRQ_ 166 interrupts = <GIC_SPI 817 IRQ_TYPE_LEVEL_HIGH>;
185 clocks = <&k3_clks 117 2>; 167 clocks = <&k3_clks 117 2>;
186 clock-names = "fck"; 168 clock-names = "fck";
187 assigned-clocks = <&k3_clks 11 169 assigned-clocks = <&k3_clks 117 2>;
188 assigned-clock-parents = <&k3_ 170 assigned-clock-parents = <&k3_clks 117 3>;
189 power-domains = <&k3_pds 117 T 171 power-domains = <&k3_pds 117 TI_SCI_PD_EXCLUSIVE>;
190 ti,timer-pwm; 172 ti,timer-pwm;
191 /* Non-MPU Firmware usage */ 173 /* Non-MPU Firmware usage */
192 status = "reserved"; 174 status = "reserved";
193 }; 175 };
194 176
195 mcu_timer2: timer@40420000 { 177 mcu_timer2: timer@40420000 {
196 compatible = "ti,am654-timer"; 178 compatible = "ti,am654-timer";
197 reg = <0x00 0x40420000 0x00 0x 179 reg = <0x00 0x40420000 0x00 0x400>;
198 interrupts = <GIC_SPI 818 IRQ_ 180 interrupts = <GIC_SPI 818 IRQ_TYPE_LEVEL_HIGH>;
199 clocks = <&k3_clks 118 2>; 181 clocks = <&k3_clks 118 2>;
200 clock-names = "fck"; 182 clock-names = "fck";
201 assigned-clocks = <&k3_clks 11 183 assigned-clocks = <&k3_clks 118 2>;
202 assigned-clock-parents = <&k3_ 184 assigned-clock-parents = <&k3_clks 118 3>;
203 power-domains = <&k3_pds 118 T 185 power-domains = <&k3_pds 118 TI_SCI_PD_EXCLUSIVE>;
204 ti,timer-pwm; 186 ti,timer-pwm;
205 /* Non-MPU Firmware usage */ 187 /* Non-MPU Firmware usage */
206 status = "reserved"; 188 status = "reserved";
207 }; 189 };
208 190
209 mcu_timer3: timer@40430000 { 191 mcu_timer3: timer@40430000 {
210 compatible = "ti,am654-timer"; 192 compatible = "ti,am654-timer";
211 reg = <0x00 0x40430000 0x00 0x 193 reg = <0x00 0x40430000 0x00 0x400>;
212 interrupts = <GIC_SPI 819 IRQ_ 194 interrupts = <GIC_SPI 819 IRQ_TYPE_LEVEL_HIGH>;
213 clocks = <&k3_clks 119 2>; 195 clocks = <&k3_clks 119 2>;
214 clock-names = "fck"; 196 clock-names = "fck";
215 assigned-clocks = <&k3_clks 11 197 assigned-clocks = <&k3_clks 119 2>;
216 assigned-clock-parents = <&k3_ 198 assigned-clock-parents = <&k3_clks 119 3>;
217 power-domains = <&k3_pds 119 T 199 power-domains = <&k3_pds 119 TI_SCI_PD_EXCLUSIVE>;
218 ti,timer-pwm; 200 ti,timer-pwm;
219 /* Non-MPU Firmware usage */ 201 /* Non-MPU Firmware usage */
220 status = "reserved"; 202 status = "reserved";
221 }; 203 };
222 204
223 mcu_timer4: timer@40440000 { 205 mcu_timer4: timer@40440000 {
224 compatible = "ti,am654-timer"; 206 compatible = "ti,am654-timer";
225 reg = <0x00 0x40440000 0x00 0x 207 reg = <0x00 0x40440000 0x00 0x400>;
226 interrupts = <GIC_SPI 820 IRQ_ 208 interrupts = <GIC_SPI 820 IRQ_TYPE_LEVEL_HIGH>;
227 clocks = <&k3_clks 120 2>; 209 clocks = <&k3_clks 120 2>;
228 clock-names = "fck"; 210 clock-names = "fck";
229 assigned-clocks = <&k3_clks 12 211 assigned-clocks = <&k3_clks 120 2>;
230 assigned-clock-parents = <&k3_ 212 assigned-clock-parents = <&k3_clks 120 3>;
231 power-domains = <&k3_pds 120 T 213 power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>;
232 ti,timer-pwm; 214 ti,timer-pwm;
233 /* Non-MPU Firmware usage */ 215 /* Non-MPU Firmware usage */
234 status = "reserved"; 216 status = "reserved";
235 }; 217 };
236 218
237 mcu_timer5: timer@40450000 { 219 mcu_timer5: timer@40450000 {
238 compatible = "ti,am654-timer"; 220 compatible = "ti,am654-timer";
239 reg = <0x00 0x40450000 0x00 0x 221 reg = <0x00 0x40450000 0x00 0x400>;
240 interrupts = <GIC_SPI 821 IRQ_ 222 interrupts = <GIC_SPI 821 IRQ_TYPE_LEVEL_HIGH>;
241 clocks = <&k3_clks 121 2>; 223 clocks = <&k3_clks 121 2>;
242 clock-names = "fck"; 224 clock-names = "fck";
243 assigned-clocks = <&k3_clks 12 225 assigned-clocks = <&k3_clks 121 2>;
244 assigned-clock-parents = <&k3_ 226 assigned-clock-parents = <&k3_clks 121 3>;
245 power-domains = <&k3_pds 121 T 227 power-domains = <&k3_pds 121 TI_SCI_PD_EXCLUSIVE>;
246 ti,timer-pwm; 228 ti,timer-pwm;
247 /* Non-MPU Firmware usage */ 229 /* Non-MPU Firmware usage */
248 status = "reserved"; 230 status = "reserved";
249 }; 231 };
250 232
251 mcu_timer6: timer@40460000 { 233 mcu_timer6: timer@40460000 {
252 compatible = "ti,am654-timer"; 234 compatible = "ti,am654-timer";
253 reg = <0x00 0x40460000 0x00 0x 235 reg = <0x00 0x40460000 0x00 0x400>;
254 interrupts = <GIC_SPI 822 IRQ_ 236 interrupts = <GIC_SPI 822 IRQ_TYPE_LEVEL_HIGH>;
255 clocks = <&k3_clks 122 2>; 237 clocks = <&k3_clks 122 2>;
256 clock-names = "fck"; 238 clock-names = "fck";
257 assigned-clocks = <&k3_clks 12 239 assigned-clocks = <&k3_clks 122 2>;
258 assigned-clock-parents = <&k3_ 240 assigned-clock-parents = <&k3_clks 122 3>;
259 power-domains = <&k3_pds 122 T 241 power-domains = <&k3_pds 122 TI_SCI_PD_EXCLUSIVE>;
260 ti,timer-pwm; 242 ti,timer-pwm;
261 /* Non-MPU Firmware usage */ 243 /* Non-MPU Firmware usage */
262 status = "reserved"; 244 status = "reserved";
263 }; 245 };
264 246
265 mcu_timer7: timer@40470000 { 247 mcu_timer7: timer@40470000 {
266 compatible = "ti,am654-timer"; 248 compatible = "ti,am654-timer";
267 reg = <0x00 0x40470000 0x00 0x 249 reg = <0x00 0x40470000 0x00 0x400>;
268 interrupts = <GIC_SPI 823 IRQ_ 250 interrupts = <GIC_SPI 823 IRQ_TYPE_LEVEL_HIGH>;
269 clocks = <&k3_clks 123 2>; 251 clocks = <&k3_clks 123 2>;
270 clock-names = "fck"; 252 clock-names = "fck";
271 assigned-clocks = <&k3_clks 12 253 assigned-clocks = <&k3_clks 123 2>;
272 assigned-clock-parents = <&k3_ 254 assigned-clock-parents = <&k3_clks 123 3>;
273 power-domains = <&k3_pds 123 T 255 power-domains = <&k3_pds 123 TI_SCI_PD_EXCLUSIVE>;
274 ti,timer-pwm; 256 ti,timer-pwm;
275 /* Non-MPU Firmware usage */ 257 /* Non-MPU Firmware usage */
276 status = "reserved"; 258 status = "reserved";
277 }; 259 };
278 260
279 mcu_timer8: timer@40480000 { 261 mcu_timer8: timer@40480000 {
280 compatible = "ti,am654-timer"; 262 compatible = "ti,am654-timer";
281 reg = <0x00 0x40480000 0x00 0x 263 reg = <0x00 0x40480000 0x00 0x400>;
282 interrupts = <GIC_SPI 824 IRQ_ 264 interrupts = <GIC_SPI 824 IRQ_TYPE_LEVEL_HIGH>;
283 clocks = <&k3_clks 124 2>; 265 clocks = <&k3_clks 124 2>;
284 clock-names = "fck"; 266 clock-names = "fck";
285 assigned-clocks = <&k3_clks 12 267 assigned-clocks = <&k3_clks 124 2>;
286 assigned-clock-parents = <&k3_ 268 assigned-clock-parents = <&k3_clks 124 3>;
287 power-domains = <&k3_pds 124 T 269 power-domains = <&k3_pds 124 TI_SCI_PD_EXCLUSIVE>;
288 ti,timer-pwm; 270 ti,timer-pwm;
289 /* Non-MPU Firmware usage */ 271 /* Non-MPU Firmware usage */
290 status = "reserved"; 272 status = "reserved";
291 }; 273 };
292 274
293 mcu_timer9: timer@40490000 { 275 mcu_timer9: timer@40490000 {
294 compatible = "ti,am654-timer"; 276 compatible = "ti,am654-timer";
295 reg = <0x00 0x40490000 0x00 0x 277 reg = <0x00 0x40490000 0x00 0x400>;
296 interrupts = <GIC_SPI 825 IRQ_ 278 interrupts = <GIC_SPI 825 IRQ_TYPE_LEVEL_HIGH>;
297 clocks = <&k3_clks 125 2>; 279 clocks = <&k3_clks 125 2>;
298 clock-names = "fck"; 280 clock-names = "fck";
299 assigned-clocks = <&k3_clks 12 281 assigned-clocks = <&k3_clks 125 2>;
300 assigned-clock-parents = <&k3_ 282 assigned-clock-parents = <&k3_clks 125 3>;
301 power-domains = <&k3_pds 125 T 283 power-domains = <&k3_pds 125 TI_SCI_PD_EXCLUSIVE>;
302 ti,timer-pwm; 284 ti,timer-pwm;
303 /* Non-MPU Firmware usage */ 285 /* Non-MPU Firmware usage */
304 status = "reserved"; 286 status = "reserved";
305 }; 287 };
306 288
307 wkup_uart0: serial@42300000 { 289 wkup_uart0: serial@42300000 {
308 compatible = "ti,j721e-uart", 290 compatible = "ti,j721e-uart", "ti,am654-uart";
309 reg = <0x00 0x42300000 0x00 0x 291 reg = <0x00 0x42300000 0x00 0x200>;
310 interrupts = <GIC_SPI 897 IRQ_ 292 interrupts = <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>;
>> 293 current-speed = <115200>;
311 clocks = <&k3_clks 397 0>; 294 clocks = <&k3_clks 397 0>;
312 clock-names = "fclk"; 295 clock-names = "fclk";
313 power-domains = <&k3_pds 397 T 296 power-domains = <&k3_pds 397 TI_SCI_PD_EXCLUSIVE>;
314 status = "disabled"; 297 status = "disabled";
315 }; 298 };
316 299
317 mcu_uart0: serial@40a00000 { 300 mcu_uart0: serial@40a00000 {
318 compatible = "ti,j721e-uart", 301 compatible = "ti,j721e-uart", "ti,am654-uart";
319 reg = <0x00 0x40a00000 0x00 0x 302 reg = <0x00 0x40a00000 0x00 0x200>;
320 interrupts = <GIC_SPI 846 IRQ_ 303 interrupts = <GIC_SPI 846 IRQ_TYPE_LEVEL_HIGH>;
>> 304 current-speed = <115200>;
321 clocks = <&k3_clks 149 0>; 305 clocks = <&k3_clks 149 0>;
322 clock-names = "fclk"; 306 clock-names = "fclk";
323 power-domains = <&k3_pds 149 T 307 power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>;
324 status = "disabled"; 308 status = "disabled";
325 }; 309 };
326 310
327 wkup_gpio0: gpio@42110000 { 311 wkup_gpio0: gpio@42110000 {
328 compatible = "ti,j721e-gpio", 312 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
329 reg = <0x00 0x42110000 0x00 0x 313 reg = <0x00 0x42110000 0x00 0x100>;
330 gpio-controller; 314 gpio-controller;
331 #gpio-cells = <2>; 315 #gpio-cells = <2>;
332 interrupt-parent = <&wkup_gpio 316 interrupt-parent = <&wkup_gpio_intr>;
333 interrupts = <103>, <104>, <10 317 interrupts = <103>, <104>, <105>, <106>, <107>, <108>;
334 interrupt-controller; 318 interrupt-controller;
335 #interrupt-cells = <2>; 319 #interrupt-cells = <2>;
336 ti,ngpio = <89>; 320 ti,ngpio = <89>;
337 ti,davinci-gpio-unbanked = <0> 321 ti,davinci-gpio-unbanked = <0>;
338 power-domains = <&k3_pds 167 T 322 power-domains = <&k3_pds 167 TI_SCI_PD_EXCLUSIVE>;
339 clocks = <&k3_clks 167 0>; 323 clocks = <&k3_clks 167 0>;
340 clock-names = "gpio"; 324 clock-names = "gpio";
341 status = "disabled"; 325 status = "disabled";
342 }; 326 };
343 327
344 wkup_gpio1: gpio@42100000 { 328 wkup_gpio1: gpio@42100000 {
345 compatible = "ti,j721e-gpio", 329 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
346 reg = <0x00 0x42100000 0x00 0x 330 reg = <0x00 0x42100000 0x00 0x100>;
347 gpio-controller; 331 gpio-controller;
348 #gpio-cells = <2>; 332 #gpio-cells = <2>;
349 interrupt-parent = <&wkup_gpio 333 interrupt-parent = <&wkup_gpio_intr>;
350 interrupts = <112>, <113>, <11 334 interrupts = <112>, <113>, <114>, <115>, <116>, <117>;
351 interrupt-controller; 335 interrupt-controller;
352 #interrupt-cells = <2>; 336 #interrupt-cells = <2>;
353 ti,ngpio = <89>; 337 ti,ngpio = <89>;
354 ti,davinci-gpio-unbanked = <0> 338 ti,davinci-gpio-unbanked = <0>;
355 power-domains = <&k3_pds 168 T 339 power-domains = <&k3_pds 168 TI_SCI_PD_EXCLUSIVE>;
356 clocks = <&k3_clks 168 0>; 340 clocks = <&k3_clks 168 0>;
357 clock-names = "gpio"; 341 clock-names = "gpio";
358 status = "disabled"; 342 status = "disabled";
359 }; 343 };
360 344
361 wkup_i2c0: i2c@42120000 { 345 wkup_i2c0: i2c@42120000 {
362 compatible = "ti,j721e-i2c", " 346 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
363 reg = <0x00 0x42120000 0x00 0x 347 reg = <0x00 0x42120000 0x00 0x100>;
364 interrupts = <GIC_SPI 896 IRQ_ 348 interrupts = <GIC_SPI 896 IRQ_TYPE_LEVEL_HIGH>;
365 #address-cells = <1>; 349 #address-cells = <1>;
366 #size-cells = <0>; 350 #size-cells = <0>;
367 clocks = <&k3_clks 279 2>; 351 clocks = <&k3_clks 279 2>;
368 clock-names = "fck"; 352 clock-names = "fck";
369 power-domains = <&k3_pds 279 T 353 power-domains = <&k3_pds 279 TI_SCI_PD_EXCLUSIVE>;
370 status = "disabled"; 354 status = "disabled";
371 }; 355 };
372 356
373 mcu_i2c0: i2c@40b00000 { 357 mcu_i2c0: i2c@40b00000 {
374 compatible = "ti,j721e-i2c", " 358 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
375 reg = <0x00 0x40b00000 0x00 0x 359 reg = <0x00 0x40b00000 0x00 0x100>;
376 interrupts = <GIC_SPI 852 IRQ_ 360 interrupts = <GIC_SPI 852 IRQ_TYPE_LEVEL_HIGH>;
377 #address-cells = <1>; 361 #address-cells = <1>;
378 #size-cells = <0>; 362 #size-cells = <0>;
379 clocks = <&k3_clks 277 2>; 363 clocks = <&k3_clks 277 2>;
380 clock-names = "fck"; 364 clock-names = "fck";
381 power-domains = <&k3_pds 277 T 365 power-domains = <&k3_pds 277 TI_SCI_PD_EXCLUSIVE>;
382 status = "disabled"; 366 status = "disabled";
383 }; 367 };
384 368
385 mcu_i2c1: i2c@40b10000 { 369 mcu_i2c1: i2c@40b10000 {
386 compatible = "ti,j721e-i2c", " 370 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
387 reg = <0x00 0x40b10000 0x00 0x 371 reg = <0x00 0x40b10000 0x00 0x100>;
388 interrupts = <GIC_SPI 853 IRQ_ 372 interrupts = <GIC_SPI 853 IRQ_TYPE_LEVEL_HIGH>;
389 #address-cells = <1>; 373 #address-cells = <1>;
390 #size-cells = <0>; 374 #size-cells = <0>;
391 clocks = <&k3_clks 278 2>; 375 clocks = <&k3_clks 278 2>;
392 clock-names = "fck"; 376 clock-names = "fck";
393 power-domains = <&k3_pds 278 T 377 power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>;
394 status = "disabled"; 378 status = "disabled";
395 }; 379 };
396 380
397 mcu_mcan0: can@40528000 { 381 mcu_mcan0: can@40528000 {
398 compatible = "bosch,m_can"; 382 compatible = "bosch,m_can";
399 reg = <0x00 0x40528000 0x00 0x 383 reg = <0x00 0x40528000 0x00 0x200>,
400 <0x00 0x40500000 0x00 0x 384 <0x00 0x40500000 0x00 0x8000>;
401 reg-names = "m_can", "message_ 385 reg-names = "m_can", "message_ram";
402 power-domains = <&k3_pds 263 T 386 power-domains = <&k3_pds 263 TI_SCI_PD_EXCLUSIVE>;
403 clocks = <&k3_clks 263 6>, <&k 387 clocks = <&k3_clks 263 6>, <&k3_clks 263 1>;
404 clock-names = "hclk", "cclk"; 388 clock-names = "hclk", "cclk";
405 interrupts = <GIC_SPI 832 IRQ_ 389 interrupts = <GIC_SPI 832 IRQ_TYPE_LEVEL_HIGH>,
406 <GIC_SPI 833 IRQ_ 390 <GIC_SPI 833 IRQ_TYPE_LEVEL_HIGH>;
407 interrupt-names = "int0", "int 391 interrupt-names = "int0", "int1";
408 bosch,mram-cfg = <0x00 128 64 392 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>;
409 status = "disabled"; 393 status = "disabled";
410 }; 394 };
411 395
412 mcu_mcan1: can@40568000 { 396 mcu_mcan1: can@40568000 {
413 compatible = "bosch,m_can"; 397 compatible = "bosch,m_can";
414 reg = <0x00 0x40568000 0x00 0x 398 reg = <0x00 0x40568000 0x00 0x200>,
415 <0x00 0x40540000 0x00 0x 399 <0x00 0x40540000 0x00 0x8000>;
416 reg-names = "m_can", "message_ 400 reg-names = "m_can", "message_ram";
417 power-domains = <&k3_pds 264 T 401 power-domains = <&k3_pds 264 TI_SCI_PD_EXCLUSIVE>;
418 clocks = <&k3_clks 264 6>, <&k 402 clocks = <&k3_clks 264 6>, <&k3_clks 264 1>;
419 clock-names = "hclk", "cclk"; 403 clock-names = "hclk", "cclk";
420 interrupts = <GIC_SPI 835 IRQ_ 404 interrupts = <GIC_SPI 835 IRQ_TYPE_LEVEL_HIGH>,
421 <GIC_SPI 836 IRQ_ 405 <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>;
422 interrupt-names = "int0", "int 406 interrupt-names = "int0", "int1";
423 bosch,mram-cfg = <0x00 128 64 407 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>;
424 status = "disabled"; 408 status = "disabled";
425 }; 409 };
426 410
427 mcu_spi0: spi@40300000 { 411 mcu_spi0: spi@40300000 {
428 compatible = "ti,am654-mcspi", 412 compatible = "ti,am654-mcspi", "ti,omap4-mcspi";
429 reg = <0x00 0x040300000 0x00 0 413 reg = <0x00 0x040300000 0x00 0x400>;
430 interrupts = <GIC_SPI 848 IRQ_ 414 interrupts = <GIC_SPI 848 IRQ_TYPE_LEVEL_HIGH>;
431 #address-cells = <1>; 415 #address-cells = <1>;
432 #size-cells = <0>; 416 #size-cells = <0>;
433 power-domains = <&k3_pds 384 T 417 power-domains = <&k3_pds 384 TI_SCI_PD_EXCLUSIVE>;
434 clocks = <&k3_clks 384 0>; 418 clocks = <&k3_clks 384 0>;
435 status = "disabled"; 419 status = "disabled";
436 }; 420 };
437 421
438 mcu_spi1: spi@40310000 { 422 mcu_spi1: spi@40310000 {
439 compatible = "ti,am654-mcspi", 423 compatible = "ti,am654-mcspi", "ti,omap4-mcspi";
440 reg = <0x00 0x040310000 0x00 0 424 reg = <0x00 0x040310000 0x00 0x400>;
441 interrupts = <GIC_SPI 849 IRQ_ 425 interrupts = <GIC_SPI 849 IRQ_TYPE_LEVEL_HIGH>;
442 #address-cells = <1>; 426 #address-cells = <1>;
443 #size-cells = <0>; 427 #size-cells = <0>;
444 power-domains = <&k3_pds 385 T 428 power-domains = <&k3_pds 385 TI_SCI_PD_EXCLUSIVE>;
445 clocks = <&k3_clks 385 0>; 429 clocks = <&k3_clks 385 0>;
446 status = "disabled"; 430 status = "disabled";
447 }; 431 };
448 432
449 mcu_spi2: spi@40320000 { 433 mcu_spi2: spi@40320000 {
450 compatible = "ti,am654-mcspi", 434 compatible = "ti,am654-mcspi", "ti,omap4-mcspi";
451 reg = <0x00 0x040320000 0x00 0 435 reg = <0x00 0x040320000 0x00 0x400>;
452 interrupts = <GIC_SPI 850 IRQ_ 436 interrupts = <GIC_SPI 850 IRQ_TYPE_LEVEL_HIGH>;
453 #address-cells = <1>; 437 #address-cells = <1>;
454 #size-cells = <0>; 438 #size-cells = <0>;
455 power-domains = <&k3_pds 386 T 439 power-domains = <&k3_pds 386 TI_SCI_PD_EXCLUSIVE>;
456 clocks = <&k3_clks 386 0>; 440 clocks = <&k3_clks 386 0>;
457 status = "disabled"; 441 status = "disabled";
458 }; 442 };
459 443
460 mcu_navss: bus@28380000 { !! 444 mcu_navss: bus@28380000{
461 bootph-all; <<
462 compatible = "simple-bus"; 445 compatible = "simple-bus";
463 #address-cells = <2>; 446 #address-cells = <2>;
464 #size-cells = <2>; 447 #size-cells = <2>;
465 ranges = <0x00 0x28380000 0x00 448 ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>;
466 ti,sci-dev-id = <323>; 449 ti,sci-dev-id = <323>;
467 dma-coherent; 450 dma-coherent;
468 dma-ranges; 451 dma-ranges;
469 452
470 mcu_ringacc: ringacc@2b800000 453 mcu_ringacc: ringacc@2b800000 {
471 bootph-all; <<
472 compatible = "ti,am654 454 compatible = "ti,am654-navss-ringacc";
473 reg = <0x00 0x2b800000 455 reg = <0x00 0x2b800000 0x00 0x400000>,
474 <0x00 0x2b000000 456 <0x00 0x2b000000 0x00 0x400000>,
475 <0x00 0x28590000 457 <0x00 0x28590000 0x00 0x100>,
476 <0x00 0x2a500000 !! 458 <0x00 0x2a500000 0x00 0x40000>;
477 <0x00 0x28440000 !! 459 reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target";
478 reg-names = "rt", "fif <<
479 ti,num-rings = <286>; 460 ti,num-rings = <286>;
480 ti,sci-rm-range-gp-rin 461 ti,sci-rm-range-gp-rings = <0x1>;
481 ti,sci = <&sms>; 462 ti,sci = <&sms>;
482 ti,sci-dev-id = <328>; 463 ti,sci-dev-id = <328>;
483 msi-parent = <&main_ud 464 msi-parent = <&main_udmass_inta>;
484 }; 465 };
485 466
486 mcu_udmap: dma-controller@285c 467 mcu_udmap: dma-controller@285c0000 {
487 bootph-all; <<
488 compatible = "ti,j721e 468 compatible = "ti,j721e-navss-mcu-udmap";
489 reg = <0x00 0x285c0000 469 reg = <0x00 0x285c0000 0x00 0x100>,
490 <0x00 0x2a800000 470 <0x00 0x2a800000 0x00 0x40000>,
491 <0x00 0x2aa00000 !! 471 <0x00 0x2aa00000 0x00 0x40000>;
492 <0x00 0x284a0000 !! 472 reg-names = "gcfg", "rchanrt", "tchanrt";
493 <0x00 0x284c0000 <<
494 <0x00 0x28400000 <<
495 reg-names = "gcfg", "r <<
496 "tchan", " <<
497 msi-parent = <&main_ud 473 msi-parent = <&main_udmass_inta>;
498 #dma-cells = <1>; 474 #dma-cells = <1>;
499 475
500 ti,sci = <&sms>; 476 ti,sci = <&sms>;
501 ti,sci-dev-id = <329>; 477 ti,sci-dev-id = <329>;
502 ti,ringacc = <&mcu_rin 478 ti,ringacc = <&mcu_ringacc>;
503 ti,sci-rm-range-tchan 479 ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */
504 480 <0x0f>; /* TX_HCHAN */
505 ti,sci-rm-range-rchan 481 ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */
506 482 <0x0b>; /* RX_HCHAN */
507 ti,sci-rm-range-rflow 483 ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */
508 }; 484 };
509 }; 485 };
510 486
511 secure_proxy_mcu: mailbox@2a480000 { 487 secure_proxy_mcu: mailbox@2a480000 {
512 compatible = "ti,am654-secure- 488 compatible = "ti,am654-secure-proxy";
513 #mbox-cells = <1>; 489 #mbox-cells = <1>;
514 reg-names = "target_data", "rt 490 reg-names = "target_data", "rt", "scfg";
515 reg = <0x00 0x2a480000 0x00 0x 491 reg = <0x00 0x2a480000 0x00 0x80000>,
516 <0x00 0x2a380000 0x00 0x 492 <0x00 0x2a380000 0x00 0x80000>,
517 <0x00 0x2a400000 0x00 0x 493 <0x00 0x2a400000 0x00 0x80000>;
518 /* 494 /*
519 * Marked Disabled: 495 * Marked Disabled:
520 * Node is incomplete as it is 496 * Node is incomplete as it is meant for bootloaders and
521 * firmware on non-MPU process 497 * firmware on non-MPU processors
522 */ 498 */
523 status = "disabled"; 499 status = "disabled";
524 }; 500 };
525 501
526 mcu_cpsw: ethernet@46000000 { 502 mcu_cpsw: ethernet@46000000 {
527 compatible = "ti,j721e-cpsw-nu 503 compatible = "ti,j721e-cpsw-nuss";
528 #address-cells = <2>; 504 #address-cells = <2>;
529 #size-cells = <2>; 505 #size-cells = <2>;
530 reg = <0x00 0x46000000 0x00 0x 506 reg = <0x00 0x46000000 0x00 0x200000>;
531 reg-names = "cpsw_nuss"; 507 reg-names = "cpsw_nuss";
532 ranges = <0x00 0x00 0x00 0x460 508 ranges = <0x00 0x00 0x00 0x46000000 0x00 0x200000>;
533 dma-coherent; 509 dma-coherent;
534 clocks = <&k3_clks 63 0>; 510 clocks = <&k3_clks 63 0>;
535 clock-names = "fck"; 511 clock-names = "fck";
536 power-domains = <&k3_pds 63 TI 512 power-domains = <&k3_pds 63 TI_SCI_PD_EXCLUSIVE>;
537 513
538 dmas = <&mcu_udmap 0xf000>, 514 dmas = <&mcu_udmap 0xf000>,
539 <&mcu_udmap 0xf001>, 515 <&mcu_udmap 0xf001>,
540 <&mcu_udmap 0xf002>, 516 <&mcu_udmap 0xf002>,
541 <&mcu_udmap 0xf003>, 517 <&mcu_udmap 0xf003>,
542 <&mcu_udmap 0xf004>, 518 <&mcu_udmap 0xf004>,
543 <&mcu_udmap 0xf005>, 519 <&mcu_udmap 0xf005>,
544 <&mcu_udmap 0xf006>, 520 <&mcu_udmap 0xf006>,
545 <&mcu_udmap 0xf007>, 521 <&mcu_udmap 0xf007>,
546 <&mcu_udmap 0x7000>; 522 <&mcu_udmap 0x7000>;
547 dma-names = "tx0", "tx1", "tx2 523 dma-names = "tx0", "tx1", "tx2", "tx3",
548 "tx4", "tx5", "tx6 524 "tx4", "tx5", "tx6", "tx7",
549 "rx"; 525 "rx";
550 status = "disabled"; 526 status = "disabled";
551 527
552 ethernet-ports { 528 ethernet-ports {
553 #address-cells = <1>; 529 #address-cells = <1>;
554 #size-cells = <0>; 530 #size-cells = <0>;
555 531
556 mcu_cpsw_port1: port@1 532 mcu_cpsw_port1: port@1 {
557 reg = <1>; 533 reg = <1>;
558 ti,mac-only; 534 ti,mac-only;
559 label = "port1 535 label = "port1";
560 ti,syscon-efus !! 536 ti,syscon-efuse = <&mcu_conf 0x200>;
561 phys = <&phy_g 537 phys = <&phy_gmii_sel 1>;
562 }; 538 };
563 }; 539 };
564 540
565 davinci_mdio: mdio@f00 { 541 davinci_mdio: mdio@f00 {
566 compatible = "ti,cpsw- 542 compatible = "ti,cpsw-mdio","ti,davinci_mdio";
567 reg = <0x00 0xf00 0x00 543 reg = <0x00 0xf00 0x00 0x100>;
568 #address-cells = <1>; 544 #address-cells = <1>;
569 #size-cells = <0>; 545 #size-cells = <0>;
570 clocks = <&k3_clks 63 546 clocks = <&k3_clks 63 0>;
571 clock-names = "fck"; 547 clock-names = "fck";
572 bus_freq = <1000000>; 548 bus_freq = <1000000>;
573 }; 549 };
574 550
575 cpts@3d000 { 551 cpts@3d000 {
576 compatible = "ti,am65- 552 compatible = "ti,am65-cpts";
577 reg = <0x00 0x3d000 0x 553 reg = <0x00 0x3d000 0x00 0x400>;
578 clocks = <&k3_clks 63 554 clocks = <&k3_clks 63 3>;
579 clock-names = "cpts"; 555 clock-names = "cpts";
580 assigned-clocks = <&k3 556 assigned-clocks = <&k3_clks 63 3>; /* CPTS_RFT_CLK */
581 assigned-clock-parents 557 assigned-clock-parents = <&k3_clks 63 5>; /* MAIN_0_HSDIV6_CLK */
582 interrupts-extended = 558 interrupts-extended = <&gic500 GIC_SPI 858 IRQ_TYPE_LEVEL_HIGH>;
583 interrupt-names = "cpt 559 interrupt-names = "cpts";
584 ti,cpts-ext-ts-inputs 560 ti,cpts-ext-ts-inputs = <4>;
585 ti,cpts-periodic-outpu 561 ti,cpts-periodic-outputs = <2>;
586 }; 562 };
587 }; 563 };
588 564
589 mcu_r5fss0: r5fss@41000000 { 565 mcu_r5fss0: r5fss@41000000 {
590 compatible = "ti,j721s2-r5fss" 566 compatible = "ti,j721s2-r5fss";
591 ti,cluster-mode = <1>; 567 ti,cluster-mode = <1>;
592 #address-cells = <1>; 568 #address-cells = <1>;
593 #size-cells = <1>; 569 #size-cells = <1>;
594 ranges = <0x41000000 0x00 0x41 570 ranges = <0x41000000 0x00 0x41000000 0x20000>,
595 <0x41400000 0x00 0x41 571 <0x41400000 0x00 0x41400000 0x20000>;
596 power-domains = <&k3_pds 345 T 572 power-domains = <&k3_pds 345 TI_SCI_PD_EXCLUSIVE>;
597 573
598 mcu_r5fss0_core0: r5f@41000000 574 mcu_r5fss0_core0: r5f@41000000 {
599 compatible = "ti,j721s 575 compatible = "ti,j721s2-r5f";
600 reg = <0x41000000 0x00 576 reg = <0x41000000 0x00010000>,
601 <0x41010000 0x00 577 <0x41010000 0x00010000>;
602 reg-names = "atcm", "b 578 reg-names = "atcm", "btcm";
603 ti,sci = <&sms>; 579 ti,sci = <&sms>;
604 ti,sci-dev-id = <346>; 580 ti,sci-dev-id = <346>;
605 ti,sci-proc-ids = <0x0 581 ti,sci-proc-ids = <0x01 0xff>;
606 resets = <&k3_reset 34 582 resets = <&k3_reset 346 1>;
607 firmware-name = "j784s 583 firmware-name = "j784s4-mcu-r5f0_0-fw";
608 ti,atcm-enable = <1>; 584 ti,atcm-enable = <1>;
609 ti,btcm-enable = <1>; 585 ti,btcm-enable = <1>;
610 ti,loczrama = <1>; 586 ti,loczrama = <1>;
611 }; 587 };
612 588
613 mcu_r5fss0_core1: r5f@41400000 589 mcu_r5fss0_core1: r5f@41400000 {
614 compatible = "ti,j721s 590 compatible = "ti,j721s2-r5f";
615 reg = <0x41400000 0x00 591 reg = <0x41400000 0x00010000>,
616 <0x41410000 0x00 592 <0x41410000 0x00010000>;
617 reg-names = "atcm", "b 593 reg-names = "atcm", "btcm";
618 ti,sci = <&sms>; 594 ti,sci = <&sms>;
619 ti,sci-dev-id = <347>; 595 ti,sci-dev-id = <347>;
620 ti,sci-proc-ids = <0x0 596 ti,sci-proc-ids = <0x02 0xff>;
621 resets = <&k3_reset 34 597 resets = <&k3_reset 347 1>;
622 firmware-name = "j784s 598 firmware-name = "j784s4-mcu-r5f0_1-fw";
623 ti,atcm-enable = <1>; 599 ti,atcm-enable = <1>;
624 ti,btcm-enable = <1>; 600 ti,btcm-enable = <1>;
625 ti,loczrama = <1>; 601 ti,loczrama = <1>;
626 }; 602 };
627 }; 603 };
628 604
629 wkup_vtm0: temperature-sensor@42040000 605 wkup_vtm0: temperature-sensor@42040000 {
630 compatible = "ti,j7200-vtm"; 606 compatible = "ti,j7200-vtm";
631 reg = <0x00 0x42040000 0x00 0x 607 reg = <0x00 0x42040000 0x00 0x350>,
632 <0x00 0x42050000 0x00 0x 608 <0x00 0x42050000 0x00 0x350>;
633 power-domains = <&k3_pds 243 T !! 609 power-domains = <&k3_pds 154 TI_SCI_PD_SHARED>;
634 #thermal-sensor-cells = <1>; 610 #thermal-sensor-cells = <1>;
635 }; 611 };
636 612
637 tscadc0: tscadc@40200000 { 613 tscadc0: tscadc@40200000 {
638 compatible = "ti,am3359-tscadc 614 compatible = "ti,am3359-tscadc";
639 reg = <0x00 0x40200000 0x00 0x 615 reg = <0x00 0x40200000 0x00 0x1000>;
640 interrupts = <GIC_SPI 860 IRQ_ 616 interrupts = <GIC_SPI 860 IRQ_TYPE_LEVEL_HIGH>;
641 power-domains = <&k3_pds 0 TI_ 617 power-domains = <&k3_pds 0 TI_SCI_PD_EXCLUSIVE>;
642 clocks = <&k3_clks 0 0>; 618 clocks = <&k3_clks 0 0>;
643 assigned-clocks = <&k3_clks 0 619 assigned-clocks = <&k3_clks 0 2>;
644 assigned-clock-rates = <600000 620 assigned-clock-rates = <60000000>;
645 clock-names = "fck"; 621 clock-names = "fck";
646 dmas = <&main_udmap 0x7400>, 622 dmas = <&main_udmap 0x7400>,
647 <&main_udmap 0x7401>; 623 <&main_udmap 0x7401>;
648 dma-names = "fifo0", "fifo1"; 624 dma-names = "fifo0", "fifo1";
649 status = "disabled"; 625 status = "disabled";
650 626
651 adc { 627 adc {
652 #io-channel-cells = <1 628 #io-channel-cells = <1>;
653 compatible = "ti,am335 629 compatible = "ti,am3359-adc";
654 }; 630 };
655 }; 631 };
656 632
657 tscadc1: tscadc@40210000 { 633 tscadc1: tscadc@40210000 {
658 compatible = "ti,am3359-tscadc 634 compatible = "ti,am3359-tscadc";
659 reg = <0x00 0x40210000 0x00 0x 635 reg = <0x00 0x40210000 0x00 0x1000>;
660 interrupts = <GIC_SPI 861 IRQ_ 636 interrupts = <GIC_SPI 861 IRQ_TYPE_LEVEL_HIGH>;
661 power-domains = <&k3_pds 1 TI_ 637 power-domains = <&k3_pds 1 TI_SCI_PD_EXCLUSIVE>;
662 clocks = <&k3_clks 1 0>; 638 clocks = <&k3_clks 1 0>;
663 assigned-clocks = <&k3_clks 1 639 assigned-clocks = <&k3_clks 1 2>;
664 assigned-clock-rates = <600000 640 assigned-clock-rates = <60000000>;
665 clock-names = "fck"; 641 clock-names = "fck";
666 dmas = <&main_udmap 0x7402>, 642 dmas = <&main_udmap 0x7402>,
667 <&main_udmap 0x7403>; 643 <&main_udmap 0x7403>;
668 dma-names = "fifo0", "fifo1"; 644 dma-names = "fifo0", "fifo1";
669 status = "disabled"; 645 status = "disabled";
670 646
671 adc { 647 adc {
672 #io-channel-cells = <1 648 #io-channel-cells = <1>;
673 compatible = "ti,am335 649 compatible = "ti,am3359-adc";
674 }; 650 };
675 }; 651 };
676 652
677 fss: bus@47000000 { 653 fss: bus@47000000 {
678 compatible = "simple-bus"; 654 compatible = "simple-bus";
>> 655 reg = <0x00 0x47000000 0x00 0x100>;
679 #address-cells = <2>; 656 #address-cells = <2>;
680 #size-cells = <2>; 657 #size-cells = <2>;
681 ranges = <0x00 0x47000000 0x00 !! 658 ranges;
682 <0x00 0x47040000 0x00 <<
683 <0x00 0x47050000 0x00 <<
684 <0x00 0x50000000 0x00 <<
685 <0x04 0x00000000 0x04 <<
686 659
687 ospi0: spi@47040000 { 660 ospi0: spi@47040000 {
688 compatible = "ti,am654 661 compatible = "ti,am654-ospi", "cdns,qspi-nor";
689 reg = <0x00 0x47040000 662 reg = <0x00 0x47040000 0x00 0x100>,
690 <0x05 0x00000000 !! 663 <0x05 0x0000000 0x01 0x0000000>;
691 interrupts = <GIC_SPI 664 interrupts = <GIC_SPI 840 IRQ_TYPE_LEVEL_HIGH>;
692 cdns,fifo-depth = <256 665 cdns,fifo-depth = <256>;
693 cdns,fifo-width = <4>; 666 cdns,fifo-width = <4>;
694 cdns,trigger-address = 667 cdns,trigger-address = <0x0>;
695 clocks = <&k3_clks 161 668 clocks = <&k3_clks 161 7>;
696 assigned-clocks = <&k3 669 assigned-clocks = <&k3_clks 161 7>;
697 assigned-clock-parents 670 assigned-clock-parents = <&k3_clks 161 9>;
698 assigned-clock-rates = 671 assigned-clock-rates = <166666666>;
699 power-domains = <&k3_p 672 power-domains = <&k3_pds 161 TI_SCI_PD_EXCLUSIVE>;
700 #address-cells = <1>; 673 #address-cells = <1>;
701 #size-cells = <0>; 674 #size-cells = <0>;
702 status = "disabled"; 675 status = "disabled";
703 }; 676 };
704 677
705 ospi1: spi@47050000 { 678 ospi1: spi@47050000 {
706 compatible = "ti,am654 679 compatible = "ti,am654-ospi", "cdns,qspi-nor";
707 reg = <0x00 0x47050000 680 reg = <0x00 0x47050000 0x00 0x100>,
708 <0x07 0x00000000 !! 681 <0x07 0x0000000 0x01 0x0000000>;
709 interrupts = <GIC_SPI 682 interrupts = <GIC_SPI 841 IRQ_TYPE_LEVEL_HIGH>;
710 cdns,fifo-depth = <256 683 cdns,fifo-depth = <256>;
711 cdns,fifo-width = <4>; 684 cdns,fifo-width = <4>;
712 cdns,trigger-address = 685 cdns,trigger-address = <0x0>;
713 clocks = <&k3_clks 162 686 clocks = <&k3_clks 162 7>;
714 power-domains = <&k3_p 687 power-domains = <&k3_pds 162 TI_SCI_PD_EXCLUSIVE>;
715 #address-cells = <1>; 688 #address-cells = <1>;
716 #size-cells = <0>; 689 #size-cells = <0>;
717 status = "disabled"; 690 status = "disabled";
718 }; 691 };
719 }; <<
720 <<
721 mcu_esm: esm@40800000 { <<
722 compatible = "ti,j721e-esm"; <<
723 reg = <0x00 0x40800000 0x00 0x <<
724 ti,esm-pins = <95>; <<
725 bootph-pre-ram; <<
726 }; <<
727 <<
728 wkup_esm: esm@42080000 { <<
729 compatible = "ti,j721e-esm"; <<
730 reg = <0x00 0x42080000 0x00 0x <<
731 ti,esm-pins = <63>; <<
732 bootph-pre-ram; <<
733 }; <<
734 <<
735 /* <<
736 * The 2 RTI instances are couple with <<
737 * reserved as these will be used by t <<
738 */ <<
739 mcu_watchdog0: watchdog@40600000 { <<
740 compatible = "ti,j7-rti-wdt"; <<
741 reg = <0x00 0x40600000 0x00 0x <<
742 clocks = <&k3_clks 367 1>; <<
743 power-domains = <&k3_pds 367 T <<
744 assigned-clocks = <&k3_clks 36 <<
745 assigned-clock-parents = <&k3_ <<
746 /* reserved for MCU_R5F0_0 */ <<
747 status = "reserved"; <<
748 }; <<
749 <<
750 mcu_watchdog1: watchdog@40610000 { <<
751 compatible = "ti,j7-rti-wdt"; <<
752 reg = <0x00 0x40610000 0x00 0x <<
753 clocks = <&k3_clks 368 1>; <<
754 power-domains = <&k3_pds 368 T <<
755 assigned-clocks = <&k3_clks 36 <<
756 assigned-clock-parents = <&k3_ <<
757 /* reserved for MCU_R5F0_1 */ <<
758 status = "reserved"; <<
759 }; 692 };
760 }; 693 };
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