1 // SPDX-License-Identifier: GPL-2.0 1 // SPDX-License-Identifier: GPL-2.0
2 /* 2 /*
3 * dts file for KV260 revA Carrier Card 3 * dts file for KV260 revA Carrier Card
4 * 4 *
5 * (C) Copyright 2020 - 2022, Xilinx, Inc. !! 5 * (C) Copyright 2020 - 2021, Xilinx, Inc.
6 * (C) Copyright 2022 - 2023, Advanced Micro D <<
7 * 6 *
8 * SD level shifter: 7 * SD level shifter:
9 * "A" - A01 board un-modified (NXP) !! 8 * "A" – A01 board un-modified (NXP)
10 * "Y" - A01 board modified with legacy interp !! 9 * "Y" – A01 board modified with legacy interposer (Nexperia)
11 * "Z" - A01 board modified with Diode interpo !! 10 * "Z" – A01 board modified with Diode interposer
12 * 11 *
13 * Michal Simek <michal.simek@amd.com> !! 12 * Michal Simek <michal.simek@xilinx.com>
14 */ 13 */
15 14
16 #include <dt-bindings/gpio/gpio.h> 15 #include <dt-bindings/gpio/gpio.h>
17 #include <dt-bindings/net/ti-dp83867.h> 16 #include <dt-bindings/net/ti-dp83867.h>
18 #include <dt-bindings/phy/phy.h> 17 #include <dt-bindings/phy/phy.h>
19 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h 18 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
20 19
21 /dts-v1/; 20 /dts-v1/;
22 /plugin/; 21 /plugin/;
23 22
24 &{/} { !! 23 &i2c1 { /* I2C_SCK C23/C24 - MIO from SOM */
25 compatible = "xlnx,zynqmp-sk-kv260-rev !! 24 #address-cells = <1>;
26 "xlnx,zynqmp-sk-kv260-rev !! 25 #size-cells = <0>;
27 "xlnx,zynqmp-sk-kv260-rev !! 26 pinctrl-names = "default", "gpio";
28 "xlnx,zynqmp-sk-kv260", " !! 27 pinctrl-0 = <&pinctrl_i2c1_default>;
29 model = "ZynqMP KV260 revA"; !! 28 pinctrl-1 = <&pinctrl_i2c1_gpio>;
30 !! 29 scl-gpios = <&gpio 24 GPIO_ACTIVE_HIGH>;
31 ina260-u14 { !! 30 sda-gpios = <&gpio 25 GPIO_ACTIVE_HIGH>;
32 compatible = "iio-hwmon"; <<
33 io-channels = <&u14 0>, <&u14 <<
34 }; <<
35 31
36 si5332_0: si5332-0 { /* u17 */ !! 32 /* u14 - 0x40 - ina260 */
>> 33 /* u27 - 0xe0 - STDP4320 DP/HDMI splitter */
>> 34 };
>> 35
>> 36 &amba {
>> 37 si5332_0: si5332_0 { /* u17 */
37 compatible = "fixed-clock"; 38 compatible = "fixed-clock";
38 #clock-cells = <0>; 39 #clock-cells = <0>;
39 clock-frequency = <125000000>; 40 clock-frequency = <125000000>;
40 }; 41 };
41 42
42 si5332_1: si5332-1 { /* u17 */ !! 43 si5332_1: si5332_1 { /* u17 */
43 compatible = "fixed-clock"; 44 compatible = "fixed-clock";
44 #clock-cells = <0>; 45 #clock-cells = <0>;
45 clock-frequency = <25000000>; 46 clock-frequency = <25000000>;
46 }; 47 };
47 48
48 si5332_2: si5332-2 { /* u17 */ !! 49 si5332_2: si5332_2 { /* u17 */
49 compatible = "fixed-clock"; 50 compatible = "fixed-clock";
50 #clock-cells = <0>; 51 #clock-cells = <0>;
51 clock-frequency = <48000000>; 52 clock-frequency = <48000000>;
52 }; 53 };
53 54
54 si5332_3: si5332-3 { /* u17 */ !! 55 si5332_3: si5332_3 { /* u17 */
55 compatible = "fixed-clock"; 56 compatible = "fixed-clock";
56 #clock-cells = <0>; 57 #clock-cells = <0>;
57 clock-frequency = <24000000>; 58 clock-frequency = <24000000>;
58 }; 59 };
59 60
60 si5332_4: si5332-4 { /* u17 */ !! 61 si5332_4: si5332_4 { /* u17 */
61 compatible = "fixed-clock"; 62 compatible = "fixed-clock";
62 #clock-cells = <0>; 63 #clock-cells = <0>;
63 clock-frequency = <26000000>; 64 clock-frequency = <26000000>;
64 }; 65 };
65 66
66 si5332_5: si5332-5 { /* u17 */ !! 67 si5332_5: si5332_5 { /* u17 */
67 compatible = "fixed-clock"; 68 compatible = "fixed-clock";
68 #clock-cells = <0>; 69 #clock-cells = <0>;
69 clock-frequency = <27000000>; 70 clock-frequency = <27000000>;
70 }; 71 };
71 }; 72 };
72 73
73 &i2c1 { /* I2C_SCK C23/C24 - MIO from SOM */ <<
74 #address-cells = <1>; <<
75 #size-cells = <0>; <<
76 pinctrl-names = "default", "gpio"; <<
77 pinctrl-0 = <&pinctrl_i2c1_default>; <<
78 pinctrl-1 = <&pinctrl_i2c1_gpio>; <<
79 scl-gpios = <&gpio 24 (GPIO_ACTIVE_HIG <<
80 sda-gpios = <&gpio 25 (GPIO_ACTIVE_HIG <<
81 <<
82 u14: ina260@40 { /* u14 */ <<
83 compatible = "ti,ina260"; <<
84 #io-channel-cells = <1>; <<
85 label = "ina260-u14"; <<
86 reg = <0x40>; <<
87 }; <<
88 /* u27 - 0xe0 - STDP4320 DP/HDMI split <<
89 }; <<
90 <<
91 /* DP/USB 3.0 and SATA */ 74 /* DP/USB 3.0 and SATA */
92 &psgtr { 75 &psgtr {
93 status = "okay"; 76 status = "okay";
94 /* pcie, usb3, sata */ 77 /* pcie, usb3, sata */
95 clocks = <&si5332_5>, <&si5332_4>, <&s 78 clocks = <&si5332_5>, <&si5332_4>, <&si5332_0>;
96 clock-names = "ref0", "ref1", "ref2"; 79 clock-names = "ref0", "ref1", "ref2";
97 }; 80 };
98 81
99 &sata { 82 &sata {
100 status = "okay"; 83 status = "okay";
101 /* SATA OOB timing settings */ 84 /* SATA OOB timing settings */
102 ceva,p0-cominit-params = /bits/ 8 <0x1 85 ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
103 ceva,p0-comwake-params = /bits/ 8 <0x0 86 ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
104 ceva,p0-burst-params = /bits/ 8 <0x13 87 ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
105 ceva,p0-retry-params = /bits/ 16 <0x96 88 ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
106 ceva,p1-cominit-params = /bits/ 8 <0x1 89 ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
107 ceva,p1-comwake-params = /bits/ 8 <0x0 90 ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
108 ceva,p1-burst-params = /bits/ 8 <0x13 91 ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
109 ceva,p1-retry-params = /bits/ 16 <0x96 92 ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
110 phy-names = "sata-phy"; 93 phy-names = "sata-phy";
111 phys = <&psgtr 3 PHY_TYPE_SATA 1 2>; 94 phys = <&psgtr 3 PHY_TYPE_SATA 1 2>;
112 }; 95 };
113 96
114 &zynqmp_dpsub { 97 &zynqmp_dpsub {
115 status = "okay"; !! 98 status = "disabled";
116 phy-names = "dp-phy0", "dp-phy1"; 99 phy-names = "dp-phy0", "dp-phy1";
117 phys = <&psgtr 1 PHY_TYPE_DP 0 0>, <&p 100 phys = <&psgtr 1 PHY_TYPE_DP 0 0>, <&psgtr 0 PHY_TYPE_DP 1 0>;
118 assigned-clock-rates = <27000000>, <25 <<
119 }; 101 };
120 102
121 &zynqmp_dpdma { 103 &zynqmp_dpdma {
122 status = "okay"; 104 status = "okay";
123 assigned-clock-rates = <600000000>; <<
124 }; 105 };
125 106
126 &usb0 { 107 &usb0 {
127 status = "okay"; 108 status = "okay";
128 pinctrl-names = "default"; 109 pinctrl-names = "default";
129 pinctrl-0 = <&pinctrl_usb0_default>; 110 pinctrl-0 = <&pinctrl_usb0_default>;
130 phy-names = "usb3-phy"; 111 phy-names = "usb3-phy";
131 phys = <&psgtr 2 PHY_TYPE_USB3 0 1>; 112 phys = <&psgtr 2 PHY_TYPE_USB3 0 1>;
132 /* missing usb5744 - u43 */ 113 /* missing usb5744 - u43 */
133 }; 114 };
134 115
135 &dwc3_0 { 116 &dwc3_0 {
136 status = "okay"; 117 status = "okay";
137 dr_mode = "host"; 118 dr_mode = "host";
138 snps,usb3_lpm_capable; 119 snps,usb3_lpm_capable;
139 maximum-speed = "super-speed"; 120 maximum-speed = "super-speed";
140 }; 121 };
141 122
142 &sdhci1 { /* on CC with tuned parameters */ 123 &sdhci1 { /* on CC with tuned parameters */
143 status = "okay"; 124 status = "okay";
144 pinctrl-names = "default"; 125 pinctrl-names = "default";
145 pinctrl-0 = <&pinctrl_sdhci1_default>; 126 pinctrl-0 = <&pinctrl_sdhci1_default>;
146 /* 127 /*
147 * SD 3.0 requires level shifter and t 128 * SD 3.0 requires level shifter and this property
148 * should be removed if the board has 129 * should be removed if the board has level shifter and
149 * need to work in UHS mode 130 * need to work in UHS mode
150 */ 131 */
151 no-1-8-v; 132 no-1-8-v;
152 disable-wp; 133 disable-wp;
153 xlnx,mio-bank = <1>; 134 xlnx,mio-bank = <1>;
154 assigned-clock-rates = <187498123>; <<
155 bus-width = <4>; <<
156 }; 135 };
157 136
158 &gem3 { !! 137 &gem3 { /* required by spec */
159 status = "okay"; 138 status = "okay";
160 pinctrl-names = "default"; 139 pinctrl-names = "default";
161 pinctrl-0 = <&pinctrl_gem3_default>; 140 pinctrl-0 = <&pinctrl_gem3_default>;
162 phy-handle = <&phy0>; 141 phy-handle = <&phy0>;
163 phy-mode = "rgmii-id"; 142 phy-mode = "rgmii-id";
164 assigned-clock-rates = <250000000>; <<
165 143
166 mdio: mdio { 144 mdio: mdio {
167 #address-cells = <1>; 145 #address-cells = <1>;
168 #size-cells = <0>; 146 #size-cells = <0>;
>> 147 reset-gpios = <&gpio 38 GPIO_ACTIVE_LOW>;
>> 148 reset-delay-us = <2>;
169 149
170 phy0: ethernet-phy@1 { 150 phy0: ethernet-phy@1 {
171 #phy-cells = <1>; 151 #phy-cells = <1>;
172 reg = <1>; 152 reg = <1>;
173 compatible = "ethernet <<
174 ti,rx-internal-delay = 153 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
175 ti,tx-internal-delay = 154 ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_75_NS>;
176 ti,fifo-depth = <DP838 155 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
177 ti,dp83867-rxctrl-stra 156 ti,dp83867-rxctrl-strap-quirk;
178 reset-assert-us = <100 <<
179 reset-deassert-us = <2 <<
180 reset-gpios = <&gpio 3 <<
181 }; 157 };
182 }; 158 };
183 }; 159 };
184 160
185 &pinctrl0 { !! 161 &pinctrl0 { /* required by spec */
186 status = "okay"; 162 status = "okay";
187 163
188 pinctrl_gpio0_default: gpio0-default { <<
189 conf { <<
190 groups = "gpio0_38_grp <<
191 bias-pull-up; <<
192 power-source = <IO_STA <<
193 }; <<
194 <<
195 mux { <<
196 groups = "gpio0_38_grp <<
197 function = "gpio0"; <<
198 }; <<
199 <<
200 conf-tx { <<
201 pins = "MIO38"; <<
202 bias-disable; <<
203 output-enable; <<
204 }; <<
205 }; <<
206 <<
207 pinctrl_uart1_default: uart1-default { 164 pinctrl_uart1_default: uart1-default {
208 conf { 165 conf {
209 groups = "uart1_9_grp" 166 groups = "uart1_9_grp";
210 slew-rate = <SLEW_RATE 167 slew-rate = <SLEW_RATE_SLOW>;
211 power-source = <IO_STA 168 power-source = <IO_STANDARD_LVCMOS18>;
212 drive-strength = <12>; 169 drive-strength = <12>;
213 }; 170 };
214 171
215 conf-rx { 172 conf-rx {
216 pins = "MIO37"; 173 pins = "MIO37";
217 bias-high-impedance; 174 bias-high-impedance;
218 }; 175 };
219 176
220 conf-tx { 177 conf-tx {
221 pins = "MIO36"; 178 pins = "MIO36";
222 bias-disable; 179 bias-disable;
223 output-enable; <<
224 }; 180 };
225 181
226 mux { 182 mux {
227 groups = "uart1_9_grp" 183 groups = "uart1_9_grp";
228 function = "uart1"; 184 function = "uart1";
229 }; 185 };
230 }; 186 };
231 187
232 pinctrl_i2c1_default: i2c1-default { 188 pinctrl_i2c1_default: i2c1-default {
233 conf { 189 conf {
234 groups = "i2c1_6_grp"; 190 groups = "i2c1_6_grp";
235 bias-pull-up; 191 bias-pull-up;
236 slew-rate = <SLEW_RATE 192 slew-rate = <SLEW_RATE_SLOW>;
237 power-source = <IO_STA 193 power-source = <IO_STANDARD_LVCMOS18>;
238 }; 194 };
239 195
240 mux { 196 mux {
241 groups = "i2c1_6_grp"; 197 groups = "i2c1_6_grp";
242 function = "i2c1"; 198 function = "i2c1";
243 }; 199 };
244 }; 200 };
245 201
246 pinctrl_i2c1_gpio: i2c1-gpio-grp { !! 202 pinctrl_i2c1_gpio: i2c1-gpio {
247 conf { 203 conf {
248 groups = "gpio0_24_grp 204 groups = "gpio0_24_grp", "gpio0_25_grp";
249 slew-rate = <SLEW_RATE 205 slew-rate = <SLEW_RATE_SLOW>;
250 power-source = <IO_STA 206 power-source = <IO_STANDARD_LVCMOS18>;
251 }; 207 };
252 208
253 mux { 209 mux {
254 groups = "gpio0_24_grp 210 groups = "gpio0_24_grp", "gpio0_25_grp";
255 function = "gpio0"; 211 function = "gpio0";
256 }; 212 };
257 }; 213 };
258 214
259 pinctrl_gem3_default: gem3-default { 215 pinctrl_gem3_default: gem3-default {
260 conf { 216 conf {
261 groups = "ethernet3_0_ 217 groups = "ethernet3_0_grp";
262 slew-rate = <SLEW_RATE 218 slew-rate = <SLEW_RATE_SLOW>;
263 power-source = <IO_STA 219 power-source = <IO_STANDARD_LVCMOS18>;
264 }; 220 };
265 221
266 conf-rx { 222 conf-rx {
267 pins = "MIO70", "MIO72 223 pins = "MIO70", "MIO72", "MIO74";
268 bias-high-impedance; 224 bias-high-impedance;
269 low-power-disable; 225 low-power-disable;
270 }; 226 };
271 227
272 conf-bootstrap { 228 conf-bootstrap {
273 pins = "MIO71", "MIO73 229 pins = "MIO71", "MIO73", "MIO75";
274 bias-disable; 230 bias-disable;
275 output-enable; <<
276 low-power-disable; 231 low-power-disable;
277 }; 232 };
278 233
279 conf-tx { 234 conf-tx {
280 pins = "MIO64", "MIO65 235 pins = "MIO64", "MIO65", "MIO66",
281 "MIO67", "MIO6 236 "MIO67", "MIO68", "MIO69";
282 bias-disable; 237 bias-disable;
283 output-enable; <<
284 low-power-enable; 238 low-power-enable;
285 }; 239 };
286 240
287 conf-mdio { 241 conf-mdio {
288 groups = "mdio3_0_grp" 242 groups = "mdio3_0_grp";
289 slew-rate = <SLEW_RATE 243 slew-rate = <SLEW_RATE_SLOW>;
290 power-source = <IO_STA 244 power-source = <IO_STANDARD_LVCMOS18>;
291 bias-disable; 245 bias-disable;
292 output-enable; <<
293 }; 246 };
294 247
295 mux-mdio { 248 mux-mdio {
296 function = "mdio3"; 249 function = "mdio3";
297 groups = "mdio3_0_grp" 250 groups = "mdio3_0_grp";
298 }; 251 };
299 252
300 mux { 253 mux {
301 function = "ethernet3" 254 function = "ethernet3";
302 groups = "ethernet3_0_ 255 groups = "ethernet3_0_grp";
303 }; 256 };
304 }; 257 };
305 258
306 pinctrl_usb0_default: usb0-default { 259 pinctrl_usb0_default: usb0-default {
307 conf { 260 conf {
308 groups = "usb0_0_grp"; 261 groups = "usb0_0_grp";
>> 262 slew-rate = <SLEW_RATE_SLOW>;
309 power-source = <IO_STA 263 power-source = <IO_STANDARD_LVCMOS18>;
310 }; 264 };
311 265
312 conf-rx { 266 conf-rx {
313 pins = "MIO52", "MIO53 267 pins = "MIO52", "MIO53", "MIO55";
314 bias-high-impedance; 268 bias-high-impedance;
315 drive-strength = <12>; <<
316 slew-rate = <SLEW_RATE <<
317 }; 269 };
318 270
319 conf-tx { 271 conf-tx {
320 pins = "MIO54", "MIO56 272 pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
321 "MIO60", "MIO61", "MIO 273 "MIO60", "MIO61", "MIO62", "MIO63";
322 bias-disable; 274 bias-disable;
323 output-enable; <<
324 drive-strength = <4>; <<
325 slew-rate = <SLEW_RATE <<
326 }; 275 };
327 276
328 mux { 277 mux {
329 groups = "usb0_0_grp"; 278 groups = "usb0_0_grp";
330 function = "usb0"; 279 function = "usb0";
331 }; 280 };
332 }; 281 };
333 282
334 pinctrl_sdhci1_default: sdhci1-default 283 pinctrl_sdhci1_default: sdhci1-default {
335 conf { 284 conf {
336 groups = "sdio1_0_grp" 285 groups = "sdio1_0_grp";
337 slew-rate = <SLEW_RATE 286 slew-rate = <SLEW_RATE_SLOW>;
338 power-source = <IO_STA 287 power-source = <IO_STANDARD_LVCMOS18>;
339 bias-disable; 288 bias-disable;
340 output-enable; <<
341 }; 289 };
342 290
343 conf-cd { 291 conf-cd {
344 groups = "sdio1_cd_0_g 292 groups = "sdio1_cd_0_grp";
345 bias-high-impedance; 293 bias-high-impedance;
346 bias-pull-up; 294 bias-pull-up;
347 slew-rate = <SLEW_RATE 295 slew-rate = <SLEW_RATE_SLOW>;
348 power-source = <IO_STA 296 power-source = <IO_STANDARD_LVCMOS18>;
349 }; 297 };
350 298
351 mux-cd { 299 mux-cd {
352 groups = "sdio1_cd_0_g 300 groups = "sdio1_cd_0_grp";
353 function = "sdio1_cd"; 301 function = "sdio1_cd";
354 }; 302 };
355 303
356 mux { 304 mux {
357 groups = "sdio1_0_grp" 305 groups = "sdio1_0_grp";
358 function = "sdio1"; 306 function = "sdio1";
359 }; 307 };
360 }; 308 };
361 }; <<
362 <<
363 &gpio { <<
364 status = "okay"; <<
365 pinctrl-names = "default"; <<
366 pinctrl-0 = <&pinctrl_gpio0_default>; <<
367 }; 309 };
368 310
369 &uart1 { 311 &uart1 {
370 status = "okay"; 312 status = "okay";
371 pinctrl-names = "default"; 313 pinctrl-names = "default";
372 pinctrl-0 = <&pinctrl_uart1_default>; 314 pinctrl-0 = <&pinctrl_uart1_default>;
373 }; 315 };
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