1 // SPDX-License-Identifier: GPL-2.0 1 // SPDX-License-Identifier: GPL-2.0
2 /* 2 /*
3 * dts file for KV260 revA Carrier Card 3 * dts file for KV260 revA Carrier Card
4 * 4 *
5 * (C) Copyright 2020 - 2022, Xilinx, Inc. 5 * (C) Copyright 2020 - 2022, Xilinx, Inc.
6 * (C) Copyright 2022 - 2023, Advanced Micro D 6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
7 * 7 *
8 * SD level shifter: 8 * SD level shifter:
9 * "A" - A01 board un-modified (NXP) 9 * "A" - A01 board un-modified (NXP)
10 * "Y" - A01 board modified with legacy interp 10 * "Y" - A01 board modified with legacy interposer (Nexperia)
11 * "Z" - A01 board modified with Diode interpo 11 * "Z" - A01 board modified with Diode interposer
12 * 12 *
13 * Michal Simek <michal.simek@amd.com> 13 * Michal Simek <michal.simek@amd.com>
14 */ 14 */
15 15
16 #include <dt-bindings/gpio/gpio.h> 16 #include <dt-bindings/gpio/gpio.h>
17 #include <dt-bindings/net/ti-dp83867.h> 17 #include <dt-bindings/net/ti-dp83867.h>
18 #include <dt-bindings/phy/phy.h> 18 #include <dt-bindings/phy/phy.h>
19 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h 19 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
20 20
21 /dts-v1/; 21 /dts-v1/;
22 /plugin/; 22 /plugin/;
23 23
24 &{/} { !! 24 &i2c1 { /* I2C_SCK C23/C24 - MIO from SOM */
25 compatible = "xlnx,zynqmp-sk-kv260-rev !! 25 #address-cells = <1>;
26 "xlnx,zynqmp-sk-kv260-rev !! 26 #size-cells = <0>;
27 "xlnx,zynqmp-sk-kv260-rev !! 27 pinctrl-names = "default", "gpio";
28 "xlnx,zynqmp-sk-kv260", " !! 28 pinctrl-0 = <&pinctrl_i2c1_default>;
29 model = "ZynqMP KV260 revA"; !! 29 pinctrl-1 = <&pinctrl_i2c1_gpio>;
30 !! 30 scl-gpios = <&gpio 24 GPIO_ACTIVE_HIGH>;
31 ina260-u14 { !! 31 sda-gpios = <&gpio 25 GPIO_ACTIVE_HIGH>;
32 compatible = "iio-hwmon"; !! 32
33 io-channels = <&u14 0>, <&u14 !! 33 /* u14 - 0x40 - ina260 */
34 }; !! 34 /* u27 - 0xe0 - STDP4320 DP/HDMI splitter */
>> 35 };
35 36
36 si5332_0: si5332-0 { /* u17 */ !! 37 &amba {
>> 38 si5332_0: si5332_0 { /* u17 */
37 compatible = "fixed-clock"; 39 compatible = "fixed-clock";
38 #clock-cells = <0>; 40 #clock-cells = <0>;
39 clock-frequency = <125000000>; 41 clock-frequency = <125000000>;
40 }; 42 };
41 43
42 si5332_1: si5332-1 { /* u17 */ !! 44 si5332_1: si5332_1 { /* u17 */
43 compatible = "fixed-clock"; 45 compatible = "fixed-clock";
44 #clock-cells = <0>; 46 #clock-cells = <0>;
45 clock-frequency = <25000000>; 47 clock-frequency = <25000000>;
46 }; 48 };
47 49
48 si5332_2: si5332-2 { /* u17 */ !! 50 si5332_2: si5332_2 { /* u17 */
49 compatible = "fixed-clock"; 51 compatible = "fixed-clock";
50 #clock-cells = <0>; 52 #clock-cells = <0>;
51 clock-frequency = <48000000>; 53 clock-frequency = <48000000>;
52 }; 54 };
53 55
54 si5332_3: si5332-3 { /* u17 */ !! 56 si5332_3: si5332_3 { /* u17 */
55 compatible = "fixed-clock"; 57 compatible = "fixed-clock";
56 #clock-cells = <0>; 58 #clock-cells = <0>;
57 clock-frequency = <24000000>; 59 clock-frequency = <24000000>;
58 }; 60 };
59 61
60 si5332_4: si5332-4 { /* u17 */ !! 62 si5332_4: si5332_4 { /* u17 */
61 compatible = "fixed-clock"; 63 compatible = "fixed-clock";
62 #clock-cells = <0>; 64 #clock-cells = <0>;
63 clock-frequency = <26000000>; 65 clock-frequency = <26000000>;
64 }; 66 };
65 67
66 si5332_5: si5332-5 { /* u17 */ !! 68 si5332_5: si5332_5 { /* u17 */
67 compatible = "fixed-clock"; 69 compatible = "fixed-clock";
68 #clock-cells = <0>; 70 #clock-cells = <0>;
69 clock-frequency = <27000000>; 71 clock-frequency = <27000000>;
70 }; 72 };
71 }; 73 };
72 74
73 &i2c1 { /* I2C_SCK C23/C24 - MIO from SOM */ <<
74 #address-cells = <1>; <<
75 #size-cells = <0>; <<
76 pinctrl-names = "default", "gpio"; <<
77 pinctrl-0 = <&pinctrl_i2c1_default>; <<
78 pinctrl-1 = <&pinctrl_i2c1_gpio>; <<
79 scl-gpios = <&gpio 24 (GPIO_ACTIVE_HIG <<
80 sda-gpios = <&gpio 25 (GPIO_ACTIVE_HIG <<
81 <<
82 u14: ina260@40 { /* u14 */ <<
83 compatible = "ti,ina260"; <<
84 #io-channel-cells = <1>; <<
85 label = "ina260-u14"; <<
86 reg = <0x40>; <<
87 }; <<
88 /* u27 - 0xe0 - STDP4320 DP/HDMI split <<
89 }; <<
90 <<
91 /* DP/USB 3.0 and SATA */ 75 /* DP/USB 3.0 and SATA */
92 &psgtr { 76 &psgtr {
93 status = "okay"; 77 status = "okay";
94 /* pcie, usb3, sata */ 78 /* pcie, usb3, sata */
95 clocks = <&si5332_5>, <&si5332_4>, <&s 79 clocks = <&si5332_5>, <&si5332_4>, <&si5332_0>;
96 clock-names = "ref0", "ref1", "ref2"; 80 clock-names = "ref0", "ref1", "ref2";
97 }; 81 };
98 82
99 &sata { 83 &sata {
100 status = "okay"; 84 status = "okay";
101 /* SATA OOB timing settings */ 85 /* SATA OOB timing settings */
102 ceva,p0-cominit-params = /bits/ 8 <0x1 86 ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
103 ceva,p0-comwake-params = /bits/ 8 <0x0 87 ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
104 ceva,p0-burst-params = /bits/ 8 <0x13 88 ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
105 ceva,p0-retry-params = /bits/ 16 <0x96 89 ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
106 ceva,p1-cominit-params = /bits/ 8 <0x1 90 ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
107 ceva,p1-comwake-params = /bits/ 8 <0x0 91 ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
108 ceva,p1-burst-params = /bits/ 8 <0x13 92 ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
109 ceva,p1-retry-params = /bits/ 16 <0x96 93 ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
110 phy-names = "sata-phy"; 94 phy-names = "sata-phy";
111 phys = <&psgtr 3 PHY_TYPE_SATA 1 2>; 95 phys = <&psgtr 3 PHY_TYPE_SATA 1 2>;
112 }; 96 };
113 97
114 &zynqmp_dpsub { 98 &zynqmp_dpsub {
115 status = "okay"; 99 status = "okay";
116 phy-names = "dp-phy0", "dp-phy1"; 100 phy-names = "dp-phy0", "dp-phy1";
117 phys = <&psgtr 1 PHY_TYPE_DP 0 0>, <&p 101 phys = <&psgtr 1 PHY_TYPE_DP 0 0>, <&psgtr 0 PHY_TYPE_DP 1 0>;
118 assigned-clock-rates = <27000000>, <25 102 assigned-clock-rates = <27000000>, <25000000>, <300000000>;
119 }; 103 };
120 104
121 &zynqmp_dpdma { 105 &zynqmp_dpdma {
122 status = "okay"; 106 status = "okay";
123 assigned-clock-rates = <600000000>; 107 assigned-clock-rates = <600000000>;
124 }; 108 };
125 109
126 &usb0 { 110 &usb0 {
127 status = "okay"; 111 status = "okay";
128 pinctrl-names = "default"; 112 pinctrl-names = "default";
129 pinctrl-0 = <&pinctrl_usb0_default>; 113 pinctrl-0 = <&pinctrl_usb0_default>;
130 phy-names = "usb3-phy"; 114 phy-names = "usb3-phy";
131 phys = <&psgtr 2 PHY_TYPE_USB3 0 1>; 115 phys = <&psgtr 2 PHY_TYPE_USB3 0 1>;
132 /* missing usb5744 - u43 */ 116 /* missing usb5744 - u43 */
133 }; 117 };
134 118
135 &dwc3_0 { 119 &dwc3_0 {
136 status = "okay"; 120 status = "okay";
137 dr_mode = "host"; 121 dr_mode = "host";
138 snps,usb3_lpm_capable; 122 snps,usb3_lpm_capable;
139 maximum-speed = "super-speed"; 123 maximum-speed = "super-speed";
140 }; 124 };
141 125
142 &sdhci1 { /* on CC with tuned parameters */ 126 &sdhci1 { /* on CC with tuned parameters */
143 status = "okay"; 127 status = "okay";
144 pinctrl-names = "default"; 128 pinctrl-names = "default";
145 pinctrl-0 = <&pinctrl_sdhci1_default>; 129 pinctrl-0 = <&pinctrl_sdhci1_default>;
146 /* 130 /*
147 * SD 3.0 requires level shifter and t 131 * SD 3.0 requires level shifter and this property
148 * should be removed if the board has 132 * should be removed if the board has level shifter and
149 * need to work in UHS mode 133 * need to work in UHS mode
150 */ 134 */
151 no-1-8-v; 135 no-1-8-v;
152 disable-wp; 136 disable-wp;
153 xlnx,mio-bank = <1>; 137 xlnx,mio-bank = <1>;
154 assigned-clock-rates = <187498123>; 138 assigned-clock-rates = <187498123>;
155 bus-width = <4>; 139 bus-width = <4>;
156 }; 140 };
157 141
158 &gem3 { !! 142 &gem3 { /* required by spec */
159 status = "okay"; 143 status = "okay";
160 pinctrl-names = "default"; 144 pinctrl-names = "default";
161 pinctrl-0 = <&pinctrl_gem3_default>; 145 pinctrl-0 = <&pinctrl_gem3_default>;
162 phy-handle = <&phy0>; 146 phy-handle = <&phy0>;
163 phy-mode = "rgmii-id"; 147 phy-mode = "rgmii-id";
164 assigned-clock-rates = <250000000>; <<
165 148
166 mdio: mdio { 149 mdio: mdio {
167 #address-cells = <1>; 150 #address-cells = <1>;
168 #size-cells = <0>; 151 #size-cells = <0>;
169 152
170 phy0: ethernet-phy@1 { 153 phy0: ethernet-phy@1 {
171 #phy-cells = <1>; 154 #phy-cells = <1>;
172 reg = <1>; 155 reg = <1>;
173 compatible = "ethernet 156 compatible = "ethernet-phy-id2000.a231";
174 ti,rx-internal-delay = 157 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
175 ti,tx-internal-delay = 158 ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_75_NS>;
176 ti,fifo-depth = <DP838 159 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
177 ti,dp83867-rxctrl-stra 160 ti,dp83867-rxctrl-strap-quirk;
178 reset-assert-us = <100 161 reset-assert-us = <100>;
179 reset-deassert-us = <2 162 reset-deassert-us = <280>;
180 reset-gpios = <&gpio 3 163 reset-gpios = <&gpio 38 GPIO_ACTIVE_LOW>;
181 }; 164 };
182 }; 165 };
183 }; 166 };
184 167
185 &pinctrl0 { !! 168 &pinctrl0 { /* required by spec */
186 status = "okay"; 169 status = "okay";
187 170
188 pinctrl_gpio0_default: gpio0-default { <<
189 conf { <<
190 groups = "gpio0_38_grp <<
191 bias-pull-up; <<
192 power-source = <IO_STA <<
193 }; <<
194 <<
195 mux { <<
196 groups = "gpio0_38_grp <<
197 function = "gpio0"; <<
198 }; <<
199 <<
200 conf-tx { <<
201 pins = "MIO38"; <<
202 bias-disable; <<
203 output-enable; <<
204 }; <<
205 }; <<
206 <<
207 pinctrl_uart1_default: uart1-default { 171 pinctrl_uart1_default: uart1-default {
208 conf { 172 conf {
209 groups = "uart1_9_grp" 173 groups = "uart1_9_grp";
210 slew-rate = <SLEW_RATE 174 slew-rate = <SLEW_RATE_SLOW>;
211 power-source = <IO_STA 175 power-source = <IO_STANDARD_LVCMOS18>;
212 drive-strength = <12>; 176 drive-strength = <12>;
213 }; 177 };
214 178
215 conf-rx { 179 conf-rx {
216 pins = "MIO37"; 180 pins = "MIO37";
217 bias-high-impedance; 181 bias-high-impedance;
218 }; 182 };
219 183
220 conf-tx { 184 conf-tx {
221 pins = "MIO36"; 185 pins = "MIO36";
222 bias-disable; 186 bias-disable;
223 output-enable; <<
224 }; 187 };
225 188
226 mux { 189 mux {
227 groups = "uart1_9_grp" 190 groups = "uart1_9_grp";
228 function = "uart1"; 191 function = "uart1";
229 }; 192 };
230 }; 193 };
231 194
232 pinctrl_i2c1_default: i2c1-default { 195 pinctrl_i2c1_default: i2c1-default {
233 conf { 196 conf {
234 groups = "i2c1_6_grp"; 197 groups = "i2c1_6_grp";
235 bias-pull-up; 198 bias-pull-up;
236 slew-rate = <SLEW_RATE 199 slew-rate = <SLEW_RATE_SLOW>;
237 power-source = <IO_STA 200 power-source = <IO_STANDARD_LVCMOS18>;
238 }; 201 };
239 202
240 mux { 203 mux {
241 groups = "i2c1_6_grp"; 204 groups = "i2c1_6_grp";
242 function = "i2c1"; 205 function = "i2c1";
243 }; 206 };
244 }; 207 };
245 208
246 pinctrl_i2c1_gpio: i2c1-gpio-grp { !! 209 pinctrl_i2c1_gpio: i2c1-gpio {
247 conf { 210 conf {
248 groups = "gpio0_24_grp 211 groups = "gpio0_24_grp", "gpio0_25_grp";
249 slew-rate = <SLEW_RATE 212 slew-rate = <SLEW_RATE_SLOW>;
250 power-source = <IO_STA 213 power-source = <IO_STANDARD_LVCMOS18>;
251 }; 214 };
252 215
253 mux { 216 mux {
254 groups = "gpio0_24_grp 217 groups = "gpio0_24_grp", "gpio0_25_grp";
255 function = "gpio0"; 218 function = "gpio0";
256 }; 219 };
257 }; 220 };
258 221
259 pinctrl_gem3_default: gem3-default { 222 pinctrl_gem3_default: gem3-default {
260 conf { 223 conf {
261 groups = "ethernet3_0_ 224 groups = "ethernet3_0_grp";
262 slew-rate = <SLEW_RATE 225 slew-rate = <SLEW_RATE_SLOW>;
263 power-source = <IO_STA 226 power-source = <IO_STANDARD_LVCMOS18>;
264 }; 227 };
265 228
266 conf-rx { 229 conf-rx {
267 pins = "MIO70", "MIO72 230 pins = "MIO70", "MIO72", "MIO74";
268 bias-high-impedance; 231 bias-high-impedance;
269 low-power-disable; 232 low-power-disable;
270 }; 233 };
271 234
272 conf-bootstrap { 235 conf-bootstrap {
273 pins = "MIO71", "MIO73 236 pins = "MIO71", "MIO73", "MIO75";
274 bias-disable; 237 bias-disable;
275 output-enable; <<
276 low-power-disable; 238 low-power-disable;
277 }; 239 };
278 240
279 conf-tx { 241 conf-tx {
280 pins = "MIO64", "MIO65 242 pins = "MIO64", "MIO65", "MIO66",
281 "MIO67", "MIO6 243 "MIO67", "MIO68", "MIO69";
282 bias-disable; 244 bias-disable;
283 output-enable; <<
284 low-power-enable; 245 low-power-enable;
285 }; 246 };
286 247
287 conf-mdio { 248 conf-mdio {
288 groups = "mdio3_0_grp" 249 groups = "mdio3_0_grp";
289 slew-rate = <SLEW_RATE 250 slew-rate = <SLEW_RATE_SLOW>;
290 power-source = <IO_STA 251 power-source = <IO_STANDARD_LVCMOS18>;
291 bias-disable; 252 bias-disable;
292 output-enable; <<
293 }; 253 };
294 254
295 mux-mdio { 255 mux-mdio {
296 function = "mdio3"; 256 function = "mdio3";
297 groups = "mdio3_0_grp" 257 groups = "mdio3_0_grp";
298 }; 258 };
299 259
300 mux { 260 mux {
301 function = "ethernet3" 261 function = "ethernet3";
302 groups = "ethernet3_0_ 262 groups = "ethernet3_0_grp";
303 }; 263 };
304 }; 264 };
305 265
306 pinctrl_usb0_default: usb0-default { 266 pinctrl_usb0_default: usb0-default {
307 conf { 267 conf {
308 groups = "usb0_0_grp"; 268 groups = "usb0_0_grp";
309 power-source = <IO_STA 269 power-source = <IO_STANDARD_LVCMOS18>;
310 }; 270 };
311 271
312 conf-rx { 272 conf-rx {
313 pins = "MIO52", "MIO53 273 pins = "MIO52", "MIO53", "MIO55";
314 bias-high-impedance; 274 bias-high-impedance;
315 drive-strength = <12>; 275 drive-strength = <12>;
316 slew-rate = <SLEW_RATE 276 slew-rate = <SLEW_RATE_FAST>;
317 }; 277 };
318 278
319 conf-tx { 279 conf-tx {
320 pins = "MIO54", "MIO56 280 pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
321 "MIO60", "MIO61", "MIO 281 "MIO60", "MIO61", "MIO62", "MIO63";
322 bias-disable; 282 bias-disable;
323 output-enable; <<
324 drive-strength = <4>; 283 drive-strength = <4>;
325 slew-rate = <SLEW_RATE 284 slew-rate = <SLEW_RATE_SLOW>;
326 }; 285 };
327 286
328 mux { 287 mux {
329 groups = "usb0_0_grp"; 288 groups = "usb0_0_grp";
330 function = "usb0"; 289 function = "usb0";
331 }; 290 };
332 }; 291 };
333 292
334 pinctrl_sdhci1_default: sdhci1-default 293 pinctrl_sdhci1_default: sdhci1-default {
335 conf { 294 conf {
336 groups = "sdio1_0_grp" 295 groups = "sdio1_0_grp";
337 slew-rate = <SLEW_RATE 296 slew-rate = <SLEW_RATE_SLOW>;
338 power-source = <IO_STA 297 power-source = <IO_STANDARD_LVCMOS18>;
339 bias-disable; 298 bias-disable;
340 output-enable; <<
341 }; 299 };
342 300
343 conf-cd { 301 conf-cd {
344 groups = "sdio1_cd_0_g 302 groups = "sdio1_cd_0_grp";
345 bias-high-impedance; 303 bias-high-impedance;
346 bias-pull-up; 304 bias-pull-up;
347 slew-rate = <SLEW_RATE 305 slew-rate = <SLEW_RATE_SLOW>;
348 power-source = <IO_STA 306 power-source = <IO_STANDARD_LVCMOS18>;
349 }; 307 };
350 308
351 mux-cd { 309 mux-cd {
352 groups = "sdio1_cd_0_g 310 groups = "sdio1_cd_0_grp";
353 function = "sdio1_cd"; 311 function = "sdio1_cd";
354 }; 312 };
355 313
356 mux { 314 mux {
357 groups = "sdio1_0_grp" 315 groups = "sdio1_0_grp";
358 function = "sdio1"; 316 function = "sdio1";
359 }; 317 };
360 }; 318 };
361 }; <<
362 <<
363 &gpio { <<
364 status = "okay"; <<
365 pinctrl-names = "default"; <<
366 pinctrl-0 = <&pinctrl_gpio0_default>; <<
367 }; 319 };
368 320
369 &uart1 { 321 &uart1 {
370 status = "okay"; 322 status = "okay";
371 pinctrl-names = "default"; 323 pinctrl-names = "default";
372 pinctrl-0 = <&pinctrl_uart1_default>; 324 pinctrl-0 = <&pinctrl_uart1_default>;
373 }; 325 };
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