1 // SPDX-License-Identifier: GPL-2.0 1 // SPDX-License-Identifier: GPL-2.0
2 /* 2 /*
3 * dts file for KV260 revA Carrier Card 3 * dts file for KV260 revA Carrier Card
4 * 4 *
5 * (C) Copyright 2020 - 2022, Xilinx, Inc. 5 * (C) Copyright 2020 - 2022, Xilinx, Inc.
6 * (C) Copyright 2022 - 2023, Advanced Micro D 6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
7 * 7 *
8 * SD level shifter: 8 * SD level shifter:
9 * "A" - A01 board un-modified (NXP) 9 * "A" - A01 board un-modified (NXP)
10 * "Y" - A01 board modified with legacy interp 10 * "Y" - A01 board modified with legacy interposer (Nexperia)
11 * "Z" - A01 board modified with Diode interpo 11 * "Z" - A01 board modified with Diode interposer
12 * 12 *
13 * Michal Simek <michal.simek@amd.com> 13 * Michal Simek <michal.simek@amd.com>
14 */ 14 */
15 15
16 #include <dt-bindings/gpio/gpio.h> 16 #include <dt-bindings/gpio/gpio.h>
17 #include <dt-bindings/net/ti-dp83867.h> 17 #include <dt-bindings/net/ti-dp83867.h>
18 #include <dt-bindings/phy/phy.h> 18 #include <dt-bindings/phy/phy.h>
19 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h 19 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
20 20
21 /dts-v1/; 21 /dts-v1/;
22 /plugin/; 22 /plugin/;
23 23
24 &{/} { 24 &{/} {
25 compatible = "xlnx,zynqmp-sk-kv260-rev 25 compatible = "xlnx,zynqmp-sk-kv260-revA",
26 "xlnx,zynqmp-sk-kv260-rev 26 "xlnx,zynqmp-sk-kv260-revY",
27 "xlnx,zynqmp-sk-kv260-rev 27 "xlnx,zynqmp-sk-kv260-revZ",
28 "xlnx,zynqmp-sk-kv260", " 28 "xlnx,zynqmp-sk-kv260", "xlnx,zynqmp";
29 model = "ZynqMP KV260 revA"; 29 model = "ZynqMP KV260 revA";
30 30
31 ina260-u14 { 31 ina260-u14 {
32 compatible = "iio-hwmon"; 32 compatible = "iio-hwmon";
33 io-channels = <&u14 0>, <&u14 33 io-channels = <&u14 0>, <&u14 1>, <&u14 2>;
34 }; 34 };
35 35
36 si5332_0: si5332-0 { /* u17 */ 36 si5332_0: si5332-0 { /* u17 */
37 compatible = "fixed-clock"; 37 compatible = "fixed-clock";
38 #clock-cells = <0>; 38 #clock-cells = <0>;
39 clock-frequency = <125000000>; 39 clock-frequency = <125000000>;
40 }; 40 };
41 41
42 si5332_1: si5332-1 { /* u17 */ 42 si5332_1: si5332-1 { /* u17 */
43 compatible = "fixed-clock"; 43 compatible = "fixed-clock";
44 #clock-cells = <0>; 44 #clock-cells = <0>;
45 clock-frequency = <25000000>; 45 clock-frequency = <25000000>;
46 }; 46 };
47 47
48 si5332_2: si5332-2 { /* u17 */ 48 si5332_2: si5332-2 { /* u17 */
49 compatible = "fixed-clock"; 49 compatible = "fixed-clock";
50 #clock-cells = <0>; 50 #clock-cells = <0>;
51 clock-frequency = <48000000>; 51 clock-frequency = <48000000>;
52 }; 52 };
53 53
54 si5332_3: si5332-3 { /* u17 */ 54 si5332_3: si5332-3 { /* u17 */
55 compatible = "fixed-clock"; 55 compatible = "fixed-clock";
56 #clock-cells = <0>; 56 #clock-cells = <0>;
57 clock-frequency = <24000000>; 57 clock-frequency = <24000000>;
58 }; 58 };
59 59
60 si5332_4: si5332-4 { /* u17 */ 60 si5332_4: si5332-4 { /* u17 */
61 compatible = "fixed-clock"; 61 compatible = "fixed-clock";
62 #clock-cells = <0>; 62 #clock-cells = <0>;
63 clock-frequency = <26000000>; 63 clock-frequency = <26000000>;
64 }; 64 };
65 65
66 si5332_5: si5332-5 { /* u17 */ 66 si5332_5: si5332-5 { /* u17 */
67 compatible = "fixed-clock"; 67 compatible = "fixed-clock";
68 #clock-cells = <0>; 68 #clock-cells = <0>;
69 clock-frequency = <27000000>; 69 clock-frequency = <27000000>;
70 }; 70 };
71 }; 71 };
72 72
73 &i2c1 { /* I2C_SCK C23/C24 - MIO from SOM */ 73 &i2c1 { /* I2C_SCK C23/C24 - MIO from SOM */
74 #address-cells = <1>; 74 #address-cells = <1>;
75 #size-cells = <0>; 75 #size-cells = <0>;
76 pinctrl-names = "default", "gpio"; 76 pinctrl-names = "default", "gpio";
77 pinctrl-0 = <&pinctrl_i2c1_default>; 77 pinctrl-0 = <&pinctrl_i2c1_default>;
78 pinctrl-1 = <&pinctrl_i2c1_gpio>; 78 pinctrl-1 = <&pinctrl_i2c1_gpio>;
79 scl-gpios = <&gpio 24 (GPIO_ACTIVE_HIG 79 scl-gpios = <&gpio 24 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
80 sda-gpios = <&gpio 25 (GPIO_ACTIVE_HIG 80 sda-gpios = <&gpio 25 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
81 81
82 u14: ina260@40 { /* u14 */ 82 u14: ina260@40 { /* u14 */
83 compatible = "ti,ina260"; 83 compatible = "ti,ina260";
84 #io-channel-cells = <1>; 84 #io-channel-cells = <1>;
85 label = "ina260-u14"; 85 label = "ina260-u14";
86 reg = <0x40>; 86 reg = <0x40>;
87 }; 87 };
88 /* u27 - 0xe0 - STDP4320 DP/HDMI split 88 /* u27 - 0xe0 - STDP4320 DP/HDMI splitter */
89 }; 89 };
90 90
91 /* DP/USB 3.0 and SATA */ 91 /* DP/USB 3.0 and SATA */
92 &psgtr { 92 &psgtr {
93 status = "okay"; 93 status = "okay";
94 /* pcie, usb3, sata */ 94 /* pcie, usb3, sata */
95 clocks = <&si5332_5>, <&si5332_4>, <&s 95 clocks = <&si5332_5>, <&si5332_4>, <&si5332_0>;
96 clock-names = "ref0", "ref1", "ref2"; 96 clock-names = "ref0", "ref1", "ref2";
97 }; 97 };
98 98
99 &sata { 99 &sata {
100 status = "okay"; 100 status = "okay";
101 /* SATA OOB timing settings */ 101 /* SATA OOB timing settings */
102 ceva,p0-cominit-params = /bits/ 8 <0x1 102 ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
103 ceva,p0-comwake-params = /bits/ 8 <0x0 103 ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
104 ceva,p0-burst-params = /bits/ 8 <0x13 104 ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
105 ceva,p0-retry-params = /bits/ 16 <0x96 105 ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
106 ceva,p1-cominit-params = /bits/ 8 <0x1 106 ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
107 ceva,p1-comwake-params = /bits/ 8 <0x0 107 ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
108 ceva,p1-burst-params = /bits/ 8 <0x13 108 ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
109 ceva,p1-retry-params = /bits/ 16 <0x96 109 ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
110 phy-names = "sata-phy"; 110 phy-names = "sata-phy";
111 phys = <&psgtr 3 PHY_TYPE_SATA 1 2>; 111 phys = <&psgtr 3 PHY_TYPE_SATA 1 2>;
112 }; 112 };
113 113
114 &zynqmp_dpsub { 114 &zynqmp_dpsub {
115 status = "okay"; 115 status = "okay";
116 phy-names = "dp-phy0", "dp-phy1"; 116 phy-names = "dp-phy0", "dp-phy1";
117 phys = <&psgtr 1 PHY_TYPE_DP 0 0>, <&p 117 phys = <&psgtr 1 PHY_TYPE_DP 0 0>, <&psgtr 0 PHY_TYPE_DP 1 0>;
118 assigned-clock-rates = <27000000>, <25 118 assigned-clock-rates = <27000000>, <25000000>, <300000000>;
119 }; 119 };
120 120
121 &zynqmp_dpdma { 121 &zynqmp_dpdma {
122 status = "okay"; 122 status = "okay";
123 assigned-clock-rates = <600000000>; 123 assigned-clock-rates = <600000000>;
124 }; 124 };
125 125
126 &usb0 { 126 &usb0 {
127 status = "okay"; 127 status = "okay";
128 pinctrl-names = "default"; 128 pinctrl-names = "default";
129 pinctrl-0 = <&pinctrl_usb0_default>; 129 pinctrl-0 = <&pinctrl_usb0_default>;
130 phy-names = "usb3-phy"; 130 phy-names = "usb3-phy";
131 phys = <&psgtr 2 PHY_TYPE_USB3 0 1>; 131 phys = <&psgtr 2 PHY_TYPE_USB3 0 1>;
132 /* missing usb5744 - u43 */ 132 /* missing usb5744 - u43 */
133 }; 133 };
134 134
135 &dwc3_0 { 135 &dwc3_0 {
136 status = "okay"; 136 status = "okay";
137 dr_mode = "host"; 137 dr_mode = "host";
138 snps,usb3_lpm_capable; 138 snps,usb3_lpm_capable;
139 maximum-speed = "super-speed"; 139 maximum-speed = "super-speed";
140 }; 140 };
141 141
142 &sdhci1 { /* on CC with tuned parameters */ 142 &sdhci1 { /* on CC with tuned parameters */
143 status = "okay"; 143 status = "okay";
144 pinctrl-names = "default"; 144 pinctrl-names = "default";
145 pinctrl-0 = <&pinctrl_sdhci1_default>; 145 pinctrl-0 = <&pinctrl_sdhci1_default>;
146 /* 146 /*
147 * SD 3.0 requires level shifter and t 147 * SD 3.0 requires level shifter and this property
148 * should be removed if the board has 148 * should be removed if the board has level shifter and
149 * need to work in UHS mode 149 * need to work in UHS mode
150 */ 150 */
151 no-1-8-v; 151 no-1-8-v;
152 disable-wp; 152 disable-wp;
153 xlnx,mio-bank = <1>; 153 xlnx,mio-bank = <1>;
154 assigned-clock-rates = <187498123>; 154 assigned-clock-rates = <187498123>;
155 bus-width = <4>; 155 bus-width = <4>;
156 }; 156 };
157 157
158 &gem3 { 158 &gem3 {
159 status = "okay"; 159 status = "okay";
160 pinctrl-names = "default"; 160 pinctrl-names = "default";
161 pinctrl-0 = <&pinctrl_gem3_default>; 161 pinctrl-0 = <&pinctrl_gem3_default>;
162 phy-handle = <&phy0>; 162 phy-handle = <&phy0>;
163 phy-mode = "rgmii-id"; 163 phy-mode = "rgmii-id";
164 assigned-clock-rates = <250000000>; 164 assigned-clock-rates = <250000000>;
165 165
166 mdio: mdio { 166 mdio: mdio {
167 #address-cells = <1>; 167 #address-cells = <1>;
168 #size-cells = <0>; 168 #size-cells = <0>;
169 169
170 phy0: ethernet-phy@1 { 170 phy0: ethernet-phy@1 {
171 #phy-cells = <1>; 171 #phy-cells = <1>;
172 reg = <1>; 172 reg = <1>;
173 compatible = "ethernet 173 compatible = "ethernet-phy-id2000.a231";
174 ti,rx-internal-delay = 174 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
175 ti,tx-internal-delay = 175 ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_75_NS>;
176 ti,fifo-depth = <DP838 176 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
177 ti,dp83867-rxctrl-stra 177 ti,dp83867-rxctrl-strap-quirk;
178 reset-assert-us = <100 178 reset-assert-us = <100>;
179 reset-deassert-us = <2 179 reset-deassert-us = <280>;
180 reset-gpios = <&gpio 3 180 reset-gpios = <&gpio 38 GPIO_ACTIVE_LOW>;
181 }; 181 };
182 }; 182 };
183 }; 183 };
184 184
185 &pinctrl0 { 185 &pinctrl0 {
186 status = "okay"; 186 status = "okay";
187 187
188 pinctrl_gpio0_default: gpio0-default { 188 pinctrl_gpio0_default: gpio0-default {
189 conf { 189 conf {
190 groups = "gpio0_38_grp 190 groups = "gpio0_38_grp";
191 bias-pull-up; 191 bias-pull-up;
192 power-source = <IO_STA 192 power-source = <IO_STANDARD_LVCMOS18>;
193 }; 193 };
194 194
195 mux { 195 mux {
196 groups = "gpio0_38_grp 196 groups = "gpio0_38_grp";
197 function = "gpio0"; 197 function = "gpio0";
198 }; 198 };
199 199
200 conf-tx { 200 conf-tx {
201 pins = "MIO38"; 201 pins = "MIO38";
202 bias-disable; 202 bias-disable;
203 output-enable; 203 output-enable;
204 }; 204 };
205 }; 205 };
206 206
207 pinctrl_uart1_default: uart1-default { 207 pinctrl_uart1_default: uart1-default {
208 conf { 208 conf {
209 groups = "uart1_9_grp" 209 groups = "uart1_9_grp";
210 slew-rate = <SLEW_RATE 210 slew-rate = <SLEW_RATE_SLOW>;
211 power-source = <IO_STA 211 power-source = <IO_STANDARD_LVCMOS18>;
212 drive-strength = <12>; 212 drive-strength = <12>;
213 }; 213 };
214 214
215 conf-rx { 215 conf-rx {
216 pins = "MIO37"; 216 pins = "MIO37";
217 bias-high-impedance; 217 bias-high-impedance;
218 }; 218 };
219 219
220 conf-tx { 220 conf-tx {
221 pins = "MIO36"; 221 pins = "MIO36";
222 bias-disable; 222 bias-disable;
223 output-enable; 223 output-enable;
224 }; 224 };
225 225
226 mux { 226 mux {
227 groups = "uart1_9_grp" 227 groups = "uart1_9_grp";
228 function = "uart1"; 228 function = "uart1";
229 }; 229 };
230 }; 230 };
231 231
232 pinctrl_i2c1_default: i2c1-default { 232 pinctrl_i2c1_default: i2c1-default {
233 conf { 233 conf {
234 groups = "i2c1_6_grp"; 234 groups = "i2c1_6_grp";
235 bias-pull-up; 235 bias-pull-up;
236 slew-rate = <SLEW_RATE 236 slew-rate = <SLEW_RATE_SLOW>;
237 power-source = <IO_STA 237 power-source = <IO_STANDARD_LVCMOS18>;
238 }; 238 };
239 239
240 mux { 240 mux {
241 groups = "i2c1_6_grp"; 241 groups = "i2c1_6_grp";
242 function = "i2c1"; 242 function = "i2c1";
243 }; 243 };
244 }; 244 };
245 245
246 pinctrl_i2c1_gpio: i2c1-gpio-grp { 246 pinctrl_i2c1_gpio: i2c1-gpio-grp {
247 conf { 247 conf {
248 groups = "gpio0_24_grp 248 groups = "gpio0_24_grp", "gpio0_25_grp";
249 slew-rate = <SLEW_RATE 249 slew-rate = <SLEW_RATE_SLOW>;
250 power-source = <IO_STA 250 power-source = <IO_STANDARD_LVCMOS18>;
251 }; 251 };
252 252
253 mux { 253 mux {
254 groups = "gpio0_24_grp 254 groups = "gpio0_24_grp", "gpio0_25_grp";
255 function = "gpio0"; 255 function = "gpio0";
256 }; 256 };
257 }; 257 };
258 258
259 pinctrl_gem3_default: gem3-default { 259 pinctrl_gem3_default: gem3-default {
260 conf { 260 conf {
261 groups = "ethernet3_0_ 261 groups = "ethernet3_0_grp";
262 slew-rate = <SLEW_RATE 262 slew-rate = <SLEW_RATE_SLOW>;
263 power-source = <IO_STA 263 power-source = <IO_STANDARD_LVCMOS18>;
264 }; 264 };
265 265
266 conf-rx { 266 conf-rx {
267 pins = "MIO70", "MIO72 267 pins = "MIO70", "MIO72", "MIO74";
268 bias-high-impedance; 268 bias-high-impedance;
269 low-power-disable; 269 low-power-disable;
270 }; 270 };
271 271
272 conf-bootstrap { 272 conf-bootstrap {
273 pins = "MIO71", "MIO73 273 pins = "MIO71", "MIO73", "MIO75";
274 bias-disable; 274 bias-disable;
275 output-enable; 275 output-enable;
276 low-power-disable; 276 low-power-disable;
277 }; 277 };
278 278
279 conf-tx { 279 conf-tx {
280 pins = "MIO64", "MIO65 280 pins = "MIO64", "MIO65", "MIO66",
281 "MIO67", "MIO6 281 "MIO67", "MIO68", "MIO69";
282 bias-disable; 282 bias-disable;
283 output-enable; 283 output-enable;
284 low-power-enable; 284 low-power-enable;
285 }; 285 };
286 286
287 conf-mdio { 287 conf-mdio {
288 groups = "mdio3_0_grp" 288 groups = "mdio3_0_grp";
289 slew-rate = <SLEW_RATE 289 slew-rate = <SLEW_RATE_SLOW>;
290 power-source = <IO_STA 290 power-source = <IO_STANDARD_LVCMOS18>;
291 bias-disable; 291 bias-disable;
292 output-enable; 292 output-enable;
293 }; 293 };
294 294
295 mux-mdio { 295 mux-mdio {
296 function = "mdio3"; 296 function = "mdio3";
297 groups = "mdio3_0_grp" 297 groups = "mdio3_0_grp";
298 }; 298 };
299 299
300 mux { 300 mux {
301 function = "ethernet3" 301 function = "ethernet3";
302 groups = "ethernet3_0_ 302 groups = "ethernet3_0_grp";
303 }; 303 };
304 }; 304 };
305 305
306 pinctrl_usb0_default: usb0-default { 306 pinctrl_usb0_default: usb0-default {
307 conf { 307 conf {
308 groups = "usb0_0_grp"; 308 groups = "usb0_0_grp";
309 power-source = <IO_STA 309 power-source = <IO_STANDARD_LVCMOS18>;
310 }; 310 };
311 311
312 conf-rx { 312 conf-rx {
313 pins = "MIO52", "MIO53 313 pins = "MIO52", "MIO53", "MIO55";
314 bias-high-impedance; 314 bias-high-impedance;
315 drive-strength = <12>; 315 drive-strength = <12>;
316 slew-rate = <SLEW_RATE 316 slew-rate = <SLEW_RATE_FAST>;
317 }; 317 };
318 318
319 conf-tx { 319 conf-tx {
320 pins = "MIO54", "MIO56 320 pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
321 "MIO60", "MIO61", "MIO 321 "MIO60", "MIO61", "MIO62", "MIO63";
322 bias-disable; 322 bias-disable;
323 output-enable; 323 output-enable;
324 drive-strength = <4>; 324 drive-strength = <4>;
325 slew-rate = <SLEW_RATE 325 slew-rate = <SLEW_RATE_SLOW>;
326 }; 326 };
327 327
328 mux { 328 mux {
329 groups = "usb0_0_grp"; 329 groups = "usb0_0_grp";
330 function = "usb0"; 330 function = "usb0";
331 }; 331 };
332 }; 332 };
333 333
334 pinctrl_sdhci1_default: sdhci1-default 334 pinctrl_sdhci1_default: sdhci1-default {
335 conf { 335 conf {
336 groups = "sdio1_0_grp" 336 groups = "sdio1_0_grp";
337 slew-rate = <SLEW_RATE 337 slew-rate = <SLEW_RATE_SLOW>;
338 power-source = <IO_STA 338 power-source = <IO_STANDARD_LVCMOS18>;
339 bias-disable; 339 bias-disable;
340 output-enable; 340 output-enable;
341 }; 341 };
342 342
343 conf-cd { 343 conf-cd {
344 groups = "sdio1_cd_0_g 344 groups = "sdio1_cd_0_grp";
345 bias-high-impedance; 345 bias-high-impedance;
346 bias-pull-up; 346 bias-pull-up;
347 slew-rate = <SLEW_RATE 347 slew-rate = <SLEW_RATE_SLOW>;
348 power-source = <IO_STA 348 power-source = <IO_STANDARD_LVCMOS18>;
349 }; 349 };
350 350
351 mux-cd { 351 mux-cd {
352 groups = "sdio1_cd_0_g 352 groups = "sdio1_cd_0_grp";
353 function = "sdio1_cd"; 353 function = "sdio1_cd";
354 }; 354 };
355 355
356 mux { 356 mux {
357 groups = "sdio1_0_grp" 357 groups = "sdio1_0_grp";
358 function = "sdio1"; 358 function = "sdio1";
359 }; 359 };
360 }; 360 };
361 }; 361 };
362 362
363 &gpio { 363 &gpio {
364 status = "okay"; 364 status = "okay";
365 pinctrl-names = "default"; 365 pinctrl-names = "default";
366 pinctrl-0 = <&pinctrl_gpio0_default>; 366 pinctrl-0 = <&pinctrl_gpio0_default>;
367 }; 367 };
368 368
369 &uart1 { 369 &uart1 {
370 status = "okay"; 370 status = "okay";
371 pinctrl-names = "default"; 371 pinctrl-names = "default";
372 pinctrl-0 = <&pinctrl_uart1_default>; 372 pinctrl-0 = <&pinctrl_uart1_default>;
373 }; 373 };
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